KR20140061786A - Liquid crystal display device and manufacturing method the same - Google Patents

Abstract

The present invention provides a liquid crystal display device which includes: a transistor substrate; a gate electrode which is formed on the transistor substrate; an insulation layer which is formed on the gate electrode; a first semiconductor layer and a second semiconductor layer which are separately formed on the insulation layer; source and drain electrodes which are formed on the first semiconductor layer; source and drain metals which are formed on the second semiconductor layer; a pixel electrode which is formed on the insulation layer and is connected to the drain electrode; a protection layer which is formed on the insulation layer and covers the source and drain electrodes, the source and drain metals, and the pixel electrode; a column spacer which is formed on the protection layer and is located in a region corresponding to the gate electrode and a column spacer layer which is located in a region corresponding to the source and drain metals; and a common electrode which is formed in a region corresponding to the column spacer layer and the pixel electrode.

Description

[0001] The present invention relates to a liquid crystal display device and a method of manufacturing the same,

The present invention relates to a liquid crystal display and a method of manufacturing the same.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, a flat panel display (FPD) such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display and a plasma liquid crystal display (PDP) ) Have been increasing. Among them, liquid crystal display devices capable of realizing high resolution and capable of not only miniaturization but also enlargement are widely used.

The liquid crystal display device comprises a transistor substrate on which thin film transistors and the like are formed, a color filter substrate on which color filters and the like are formed, and a liquid crystal layer interposed therebetween. In a method such as IPS (In Plane Switching) or FFS (Fringe Field Switching) mode among the liquid crystal display devices, a common electrode and a pixel electrode are formed on a thin film transistor substrate.

In a liquid crystal display device such as an IPS or FFS mode, a parasitic capacitor and a driving voltage of a data line must be reduced in order to reduce power consumption. To this end, a protective layer is formed thick (about 6000 angstroms) in order to reduce parasitic capacitors formed between the data line and the common electrode. The parasitic capacitor and the driving voltage have a trade off relationship depending on the thickness of the protective film. That is, in order to reduce the power consumption, the thickness of the protective film must be increased to lower the parasitic capacitors. However, in this case, since the thickness between the pixel electrode and the common electrode also increases, there is no effect in reducing power consumption due to an increase in driving voltage. Therefore, a liquid crystal display device of the same type as the IPS or FFS mode is required to reduce driving voltage and reduce power consumption.

In order to solve the above-described problems, the present invention provides a liquid crystal display device capable of reducing power consumption and a driving voltage, and a method of manufacturing the same.

According to the present invention, there is provided a semiconductor device comprising: a transistor substrate; A gate electrode formed on the transistor substrate; An insulating film formed on the gate electrode; A first semiconductor layer and a second semiconductor layer formed on the insulating film; Source and drain electrodes formed on the first semiconductor layer; Source and drain metals formed on the second semiconductor layer; A pixel electrode formed on the insulating film and connected to the drain electrode; A protective film formed on the insulating film and covering the source and drain electrodes, the source and drain metal, and the pixel electrode; A column spacer formed on the protective film and located in a region corresponding to the gate electrode, and a column spacer layer located in a region corresponding to the source and drain metals; And a common electrode formed in a region corresponding to the pixel electrode and the column spacer layer.

The column spacer layer may be formed of the same material and the same process as the column spacer.

The thickness of the column spacer layer may be thinner than the thickness of the column spacer.

The thickness of the column spacer layer and the thickness of the protective film may have an inverse relationship.

The thickness of the column spacer layer may be in the range of 4000 Å to 15000 Å.

The column spacer and the column spacer layer may be formed of a black-based resin.

In another aspect, the present invention provides a method of manufacturing a transistor, comprising: forming a gate electrode on a transistor substrate; Forming an insulating film on the gate electrode; Forming a first semiconductor layer and a second semiconductor layer apart from each other on an insulating film; Forming source and drain electrodes on the first semiconductor layer and forming source and drain metals on the second semiconductor layer; Forming a pixel electrode connected to the drain electrode on the insulating film; Forming a protective film covering the source and drain electrodes, the source and drain metals, and the pixel electrode on the insulating film; Forming a column spacer layer located in a region corresponding to the gate electrode on the protective film and a column spacer layer located in a region corresponding to the source and drain metals; And forming a common electrode in a region corresponding to the column spacer layer and the pixel electrode.

The column spacer layer and the column spacer may be formed using the same material and the same process using a halftone mask.

The thickness of the column spacer layer can be made thinner than the thickness of the column spacer.

The thickness of the column spacer layer and the thickness of the protective film are inversely proportional to each other, and the thickness of the column spacer layer may be in the range of 4000 Å to 15000 Å.

The present invention relates to a liquid crystal display device capable of lowering a parasitic capacitor generated in a structure in which a transparent electrode such as ITO is formed on a data line such as an IPS and an FFS structure and lowering a driving voltage by lowering a thickness between a pixel electrode and a common electrode, There is an effect of providing a manufacturing method thereof. That is, the present invention has the effect of reducing the power consumption and the driving voltage.

1 is a block diagram schematically showing a liquid crystal display device.
Fig. 2 is a schematic view showing the subpixel shown in Fig. 1. Fig.
3 is a perspective view schematically showing a liquid crystal panel;
4 is a plan view of a subpixel according to an embodiment of the present invention.
5 is a cross-sectional view of the region A1-A2 of Fig.
6 is a structure diagram of a data line according to an embodiment;
7 is a structure diagram of a data line according to a comparative example;
8 to 11 are partial cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to an embodiment of the present invention.
12 is a plan view of a sub-pixel having two domains;
13 is a plan view of a sub-pixel having one domain;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram schematically showing a liquid crystal display device, FIG. 2 is a schematic view showing subpixels shown in FIG. 1, and FIG. 3 is a perspective view schematically showing a liquid crystal panel.

The liquid crystal display device includes a timing controller 130, a gate driver 140, a data driver 150, a liquid crystal panel 160, and a backlight unit 170.

The timing controller 130 receives a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a clock signal CLK and a data signal DATA from the outside. The timing controller 130 controls the operation timings of the data driver 150 and the gate driver 140 using timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal. The timing controller 130 can determine the frame period by counting the data enable signal of one horizontal period, so that the vertical synchronizing signal and the horizontal synchronizing signal supplied from the outside can be omitted. The control signals generated by the timing controller 130 include a gate timing control signal GDC for controlling the operation timing of the gate driver 140 and a data timing control signal DDC for controlling the operation timing of the data driver 150. [ ) May be included. The gate timing control signal GDC includes a gate start pulse GSP, a gate shift clock GSC and a gate output enable signal GOE. The gate start pulse GSP is supplied to a gate drive IC (Integrated Circuit) generating the first gate signal. The gate shift clock GSC is a clock signal commonly input to the gate drive ICs, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs. The data timing control signal DDC includes source start pulses (Source, Start Pulse, SSP), Source Sampling Clock (SSC), Source Output Enable (SOE), and the like. The source start pulse SSP controls the data sampling start timing of the data driver 150. The source sampling clock SSC is a clock signal for controlling the sampling operation of data in the data driver 150 based on the rising or falling edge. The source output enable signal SOE controls the output of the data driver 150. Meanwhile, the source start pulse SSP supplied to the data driver 150 may be omitted depending on the data transfer method. The timing controller 130 supplies the data driver 150 with the data signal DATA along with the data timing control signal DDC.

The gate driver 140 outputs a gate signal while shifting the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing controller 130. The gate driver 140 supplies a gate signal to the liquid crystal panel 160 through the gate lines GL. The gate driver 140 may be formed in the form of an IC or a gate in panel in the liquid crystal panel 160.

The data driver 150 samples and latches the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 130, and converts the sampled data signal into a gamma reference voltage. The data driver 150 supplies the data signal DATA to the liquid crystal panel 160 through the data lines DL. The data driver 150 is formed in an IC form.

The liquid crystal panel 160 displays an image corresponding to the gate signal supplied from the gate driver 140 and the data signal DATA supplied from the data driver 150. The liquid crystal panel 160 includes subpixels SP for controlling light provided through the backlight unit 170. [

One sub-pixel includes a switching transistor TFT, a storage capacitor Cst, and a liquid crystal layer Clc. The gate electrode of the switching transistor TFT is connected to the gate line GL1 and the source electrode thereof is connected to the data line DL1. One end of the storage capacitor Cst is connected to the drain electrode of the switching transistor TFT and the other end is connected to the common voltage line Vcom. The liquid crystal layer Clc is formed between the pixel electrode 1 connected to the drain electrode of the switching transistor TFT and the common electrode 2 connected to the common voltage line Vcom.

The liquid crystal panel 160 includes a transistor substrate 160a on which thin film transistors and the like are formed, a color filter substrate 160b on which color filters are formed, and a liquid crystal layer interposed therebetween. A lower polarizer 181 is attached to the lower surface of the transistor substrate 160a and an upper polarizer 185 is attached to the upper surface of the color filter substrate 160b. The liquid crystal panel 160 is implemented in IPS (In Plane Switching) mode or FFS (Fringe Field Switching) mode in which the pixel electrode 1 and the common electrode 2 are formed on a transistor substrate.

The backlight unit 170 provides light to the liquid crystal panel 160. The backlight unit 170 includes a light emitting diode (hereinafter, LED), an LED driver for driving the LED, a light guide plate for converting light emitted from the LED into a surface light source, and optical sheets for condensing and diffusing light emitted from the light guide plate .

Hereinafter, a structure of a liquid crystal display device according to an embodiment of the present invention will be described.

FIG. 4 is a plan view of a subpixel according to an embodiment of the present invention, FIG. 5 is a cross-sectional view of the region A1-A2 in FIG. 4, FIG. 6 is a structure diagram of a data line according to an embodiment, Fig.

The structure of one subpixel in a plane will be described as follows. The switching transistor TFT has a source electrode S connected to the first data line DL1 and a gate electrode G connected to the first gate line GL1 and a drain electrode D connected to the pixel electrode 168 . The storage capacitor Cst is formed in a region where the common electrode 165 and the pixel electrode 168 overlap.

The structure of one subpixel on a section will be described below. A gate electrode 161 is formed on the transistor substrate 160a. The gate electrode 161 becomes the gate electrode 161 of the switching transistor TFT and simultaneously becomes the first gate line GL1. An insulating film 162 is formed on the gate electrode 161.

On the insulating film 162, the first semiconductor layer 163a and the second semiconductor layer 163b are formed apart from each other. The first semiconductor layer 163a is formed in a region corresponding to the gate electrode 161 and the second semiconductor layer 163b is formed in a region defined by the first data line DL1. A source electrode 164a and a drain electrode 164b are formed on the first semiconductor layer 163a. Source and drain metal 164c are formed on the second semiconductor layer 163b. The source electrode 164a and the drain electrode 164b formed on the first semiconductor layer 163a become the source electrode 164a and the drain electrode 164b of the switching transistor TFT. The source and drain metal 164c formed on the second semiconductor layer 163b become the first data line DL1.

A pixel electrode 165 is formed on the insulating layer 162 to be connected to the drain electrode 164b. The pixel electrode 165 is formed on the insulating film 162 in the form of a front electrode. A protective film 166 is formed on the insulating film 162 to cover the source electrode 164a, the drain electrode 164b, the source and drain metal 164c, and the pixel electrode 165. [

On the protective film 166, a column spacer 167a and a column spacer layer 167b are formed. The column spacer 167a is formed in a region corresponding to the gate electrode 161 and the column spacer layer 167b is formed in a region corresponding to the first data line DL1. Here, the column spacer 167a is formed in an island shape, and the column spacer layer 167b is formed in a long bar shape (or a stripe shape) along the first data line DL1. The thickness of the column spacer layer 167b is formed thinner than the thickness of the column spacer 167a. The column spacer layer 167b is used as a factor for controlling the parasitic capacitance, and the column spacer 167a is used as a spacer for maintaining the cell gap of the liquid crystal panel.

A common electrode 168 is formed on the column spacer layer 167b and the protective film 166. [ The common electrode 168 is divided into a plurality of regions corresponding to the pixel electrodes 165. [ The common electrode 168 is separated in the direction of the first data line DL1 but is not parallel to the first data line DL1 but has a shape separated in the diagonal direction.

In the liquid crystal panel according to the embodiment of the present invention, a column spacer layer 167b formed of the same material as the column spacer 167a is formed on the first data line DL1 (see FIG. 6). On the other hand, The protective layer 166 is formed on the first data line DL1.

In a liquid crystal display device such as the IPS mode or the FFS mode, the parasitic capacitor Cdc of the data line and the driving voltage must be reduced in order to reduce power consumption. The parasitic capacitor Cdc and the driving voltage have a trade-off relationship depending on the thickness of the protective film. Therefore, in order to reduce the power consumption and the driving voltage, the thickness of the protective film must be adjusted.

Since the column spacer layer 167b is inserted into the liquid crystal panel according to the embodiment of the present invention, the thickness H12 of the protective film 166 located below the column spacer 167a can be reduced by the thickness of the column spacer 167a. As a result, an embodiment of the present invention can reduce the thickness between the pixel electrode 165 and the common electrode 168, while maintaining the thickness between the first data line DL1 and the common electrode 168 at a level equivalent to that of the comparative example have.

On the other hand, since the liquid crystal panel according to the comparative example uses only the protective film 166, the thickness between the first data line DL1 and the common electrode 168 can be increased. However, as the thicknesses H21 and H22 of the protective film 166 increase, the thickness between the pixel electrode 165 and the common electrode 168 also increases, and the rise of the driving voltage does not have an effect on power consumption reduction.

For example, in the comparative example, only the protective film 166 is used. Therefore, in order to reduce the parasitic capacitor Cdc between the first data line DL1 and the common electrode 168, the thicknesses H21 and H22 of the protective film 166 should be about 6000 ANGSTROM. However, the comparative example can reduce only parasitic capacitors due to its structural characteristics.

On the other hand, an embodiment of the present invention uses a protective film 166 and a column spacer layer 167b. Therefore, even if the thickness H11 of the column spacer layer 167b is formed to about 4000 ANGSTROM and the thickness H12 of the protective film 166 is about 2000 ANGSTROM, parasitic capacitors between the first data line DL1 and the common electrode 168 Cdc) can be reduced. In addition, since the protective film 166 is formed thin, the driving voltage can be lowered. Here, when forming the column spacer layer 167b, it is preferable to form the column spacer layer 167b narrower than the width of the common electrode 168 in order to prevent a decrease in transmittance.

In an embodiment of the present invention, the thickness H11 of the column spacer layer 167b may be in the range of 3000 Å to 15000 Å. More specifically, the thickness H11 of the column spacer layer 167b may be in the range of 4000 Å to 15000 Å. The thickness H11 of the column spacer layer 167b and the thickness H12 of the protective film 166 are in inverse proportion to each other.

For example, when the thickness H11 of the column spacer layer 167b is 4000 or more, the thickness H12 of the protective film 166 can be reduced to 2000 angstroms. When the thickness H11 of the column spacer layer 167b is set to 15000A or less, the thickness H12 of the protective film 166 can be lowered to 2000 ANGSTROM or less to minimize the thickness between the pixel electrode 165 and the common electrode 168 . In this case, the power consumption and the driving voltage of the data driver for driving the liquid crystal display device can be drastically reduced.

The following equation is used in relation to the power consumption of the data driver driving the liquid crystal display device.

[Equation 1]

In Equation (1), f is a driving frequency-related factor, n is the number of data lines and gate lines, C is a capacitance, and V is a valid voltage.

When the thickness of the protective film increases, the capacitance between the data line and the common electrode decreases but the driving voltage increases. When the thickness of the protective film decreases, the capacitance between the data line and the common electrode increases but the driving voltage decreases.

Therefore, one embodiment of the present invention can reduce the power consumption and reduce the driving voltage by forming the column spacer layer 167b on the first data line DL1 when the column spacer 167a is formed.

Hereinafter, a method of manufacturing a liquid crystal display device according to an embodiment of the present invention will be described.

8 to 11 are partial cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to an embodiment of the present invention.

First, a gate metal is formed on the transistor substrate 160a. The gate metal may be any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper Or an alloy thereof. The gate metal becomes the gate electrode 161 of the switching transistor and simultaneously becomes the first gate line.

Next, an insulating film 162 is formed on the gate metal. The insulating film 162 may be formed of silicon oxide (SiOx), silicon nitride (SiNx), or the like.

Next, semiconductor layers 163a and 163b are formed on the insulating film 162. Then, The semiconductor layers 163a and 163b are formed of the same material and have a first semiconductor layer 163a located in a region corresponding to the gate electrode 161 and a second semiconductor layer 163b located in a region defined by the first data line ).

Next, source and drain metals are formed on the semiconductor layers 163a and 163b. The source and drain metals are formed of the same material and are located in regions corresponding to the source electrode 164a and the drain electrode 164b located in the region corresponding to the first semiconductor layer 163a and the second semiconductor layer 163b Source and drain metal 164c. In other words, one source and drain layers 164a and 164b are the source electrode 164a and the drain electrode 164b of the switching transistor, and the other source and drain layers 164c are the first data line DL1. The source and drain metals may be selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) One or an alloy thereof.

Next, the pixel electrode 165 is formed on the insulating film 162. Next, The pixel electrode 165 is formed on the insulating film 162 to be connected to the drain electrode 164b. The pixel electrode 165 is formed on the insulating film 162 in the form of a front electrode. The pixel electrode 165 may be formed of a transparent metal such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

Next, a protective film 166 is formed on the insulating film 162. The protective film 166 is formed on the insulating film 162 so as to cover the source electrode 164a, the drain electrode 164b, the source and drain metal 164c, and the pixel electrode 165. [ The protective film 166 may be formed of silicon oxide (SiOx), silicon nitride (SiNx) or the like.

Next, a column spacer material is formed on the protective film 166. The column spacer material is separated into a column spacer 167a located in the region corresponding to the gate electrode 161 and a column spacer layer 167b located in the region corresponding to the first data line DL1. Here, the column spacer 167a is formed in an island shape, and the column spacer layer 167b is formed in a long bar shape (or a stripe shape) along the first data line DL1. And the thickness of the column spacer layer 167b is formed thinner than the thickness of the column spacer 167a. The column spacer layer 167b is used as a factor for controlling the parasitic capacitance, and the column spacer 167a is used as a spacer for maintaining the cell gap of the liquid crystal panel.

The column spacer material may be formed of a photosensitive organic material. The column spacer material may be patterned by a halftone mask (HTM). The halftone mask HTM has a transmissive portion, a semi-transmissive portion, and a blocking portion. The region corresponding to the transmissive portion is completely exposed, the region corresponding to the semi-transmissive portion is only partially exposed, and the region corresponding to the blocking portion is not exposed. Accordingly, in order to form the thicknesses of the column spacer layer 167b and the column spacer 167a as described above, the transflective portion may correspond to the column spacer layer 167b and the column spacer 167a.

However, the method of forming the column spacer layer 167b and the column spacer 167a may vary depending on whether the material is a positive type or a negative type. On the other hand, the column spacer material is formed in the non-aperture region, not the aperture region of the subpixel. Accordingly, the column spacer material can be composed of a black series resin. In this case, the column spacer layer 167b may be formed in a long bar shape along the first data line DL1 to efficiently prevent the light leakage in the corresponding region.

Next, the common electrode 168 is formed on the protective film 166. The common electrode 168 is formed in a region corresponding to the column spacer layer 167b and the pixel electrode 165. [ The common electrode 168 is divided into a plurality of regions corresponding to the pixel electrodes 165. [ The common electrode 168 is separated in the first data line DL1 direction but is not parallel to the first data line DL1 and has a shape divided in the oblique direction. The common electrode 168 may be formed of a transparent metal such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

When the transistor substrate 160a is fabricated by the above process, a color filter substrate is manufactured, and a liquid crystal panel for forming a liquid crystal layer is formed by rubbing the alignment film inside the two substrates. When the gate driver, the data driver, and the timing controller are electrically connected to the liquid crystal panel, the manufacture of the liquid crystal display device is completed.

Meanwhile, the liquid crystal display device according to an embodiment of the present invention may be variously configured according to the structure of the subpixel, and an example thereof will be described.

FIG. 12 is a plan view of a sub-pixel having two domains, and FIG. 13 is a plan view of a sub-pixel having one domain.

The liquid crystal display device according to an embodiment of the present invention is applicable to a structure having two domains in one subpixel and a structure having one domain in one subpixel. Both of the structures are rubbed in the y-direction. Orientation film rubbing can use UV (Ultra Violet) or rubbing cloth.

A structure having two domains in one subpixel is arranged in an equilateral (<) form in which the first data line DL1 is inclined with respect to the center of the opening region of each subpixel. Therefore, in the first and second subpixels SP01 and SP11, two domains are formed on the upper and lower sides with respect to the center of the opening region. In this structure, the switching transistors TFT included in the first and second sub-pixels SP01 and SP11 are arranged in the same direction.

The structure having one domain in one subpixel is arranged in a straight line without arranging the first data lines DL1 in a slanted form. Therefore, one domain is formed in the opening region of the first and second sub-pixels SP01 and SP11. In this structure, the switching transistors TFT included in the first and second sub-pixels SP01 and SP11 are arranged alternately to the left and right sides of the line.

Both structures can form a column spacer layer on the data lines in addition to forming the column spacer 167a on the gate electrode of the switching transistor (TFT). However, a structure having two domains in one subpixel may cause a certain amount of light leakage since the rubbing between the data line and the alignment layer is not completely matched and is bent. On the other hand, a structure having one domain in one subpixel has no possibility of causing light leakage because the rubbing between the data line and the alignment layer is completely matched. That is, one embodiment of the present invention can provide a structure optimized for a structure having one domain in one subpixel, but it is also applicable to a structure having two domains in one subpixel.

As described above, the present invention has an effect of lowering a parasitic capacitor generated in a structure in which a transparent electrode such as ITO is formed on a data line, such as an IPS and an FFS structure, and lowering the driving voltage by lowering the thickness between the pixel electrode and the common electrode . That is, the present invention provides a liquid crystal display device capable of reducing power consumption and a driving voltage, and a manufacturing method thereof.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

130: timing controller 140: gate driver
150: data driver 160: liquid crystal panel
170: backlight unit 168: pixel electrode
165: common electrode 166:
167a: column spacer 167b: column spacer layer

Claims (10)

Transistor substrate;
A gate electrode formed on the transistor substrate;
An insulating film formed on the gate electrode;
A first semiconductor layer and a second semiconductor layer formed on the insulating layer;
Source and drain electrodes formed on the first semiconductor layer;
Source and drain metals formed on the second semiconductor layer;
A pixel electrode formed on the insulating film and connected to the drain electrode;
A protective film formed on the insulating film and covering the source and drain electrodes, the source and drain electrodes, and the pixel electrode;
A column spacer formed on the protective film and located in a region corresponding to the gate electrode, and a column spacer layer located in a region corresponding to the source and drain metals; And
And a common electrode formed on the column spacer layer and a region corresponding to the pixel electrode. The method according to claim 1,
The column spacer layer
And the liquid crystal layer is formed of the same material and the same process as the column spacer. The method according to claim 1,
The thickness of the column spacer layer
Wherein a thickness of the column spacer is smaller than a thickness of the column spacer. The method according to claim 1,
Wherein a thickness of the column spacer layer and a thickness of the protective film are inversely proportional to each other. The method according to claim 1,
The thickness of the column spacer layer
And the second electrode is formed in a range of 4000 ANGSTROM to 15000 ANGSTROM. The method according to claim 1,
The column spacer and the column spacer layer
And a black-based resin. Forming a gate electrode on the transistor substrate;
Forming an insulating film on the gate electrode;
Forming a first semiconductor layer and a second semiconductor layer apart from each other on the insulating film;
Forming source and drain electrodes on the first semiconductor layer and source and drain metals on the second semiconductor layer;
Forming a pixel electrode connected to the drain electrode on the insulating film;
Forming a protective film covering the source and drain electrodes, the source and drain electrodes, and the pixel electrode on the insulating film;
Forming a column spacer on the protective film in a region corresponding to the gate electrode and a column spacer layer in a region corresponding to the source and drain metals; And
And forming a common electrode in a region corresponding to the column spacer layer and the pixel electrode. 8. The method of claim 7,
Wherein the column spacer layer and the column spacer are formed using the same material and the same process using a halftone mask. 8. The method of claim 7,
The thickness of the column spacer layer
Wherein a thickness of the column spacer is smaller than a thickness of the column spacer. 8. The method of claim 7,
The thickness of the column spacer layer and the thickness of the protective film are inversely proportional to each other,
Wherein the thickness of the column spacer layer is in a range of about 4000 ANGSTROM to about 15000 ANGSTROM.

Images