KR20140031143A - Thin film transistor substrate having a light absorbing layer for shielding metal oxide semiconductor layer from light and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a thin film transistor substrate having a light absorbing layer for shielding a metal oxide semiconductor layer from a light, and a method for manufacturing the same. The thin film transistor substrate having a metal oxide semiconductor according to the present invention comprises: a substrate; a thin film transistor formed on the substrate; a light absorbing layer having a size corresponding to the thin film transistor in between the substrate and the thin film transistor; a protecting film for covering the thin film transistor; and the light absorbing layer having a size corresponding to the thin film transistor on the protecting film. The present invention allows maintenance of the characteristics of the thin film transistor by preventing the influx of light into a channel region of the semiconductor material which has an excellent light absorption rate.

Description

Thin Film Transistor Substrate Having A Light Absorbing Layer For Shielding Metal Oxide Semiconductor Layer From Light And Method For Manufacturing The Same

The present invention relates to a thin film transistor substrate having a light absorbing layer for protecting a metal oxide semiconductor layer from external light and a method of manufacturing the same. In particular, the present invention provides a thin film transistor for a flat panel display device having a light absorbing layer for preventing light from flowing outside the metal oxide semiconductor channel layer in a thin film transistor having a top gate structure or a bottom gate structure. A substrate and a method of manufacturing the same.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. As a result, it has rapidly developed into a flat panel display device (FPD) capable of replacing a bulky cathode ray tube (CRT) with a thin, light and large area. The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display (OLED), and an electrophoretic display device : ED) have been developed and utilized.

A display panel (DP) constituting a flat panel display device includes a thin film transistor substrate on which thin film transistors allocated in pixel regions arranged in a matrix manner are arranged. For example, a liquid crystal display device (LCD) displays an image by adjusting the light transmittance of a liquid crystal using an electric field. Such a liquid crystal display device is divided into a vertical electric field type and a horizontal electric field type in accordance with the direction of the electric field driving the liquid crystal.

A vertical electric field type liquid crystal display device drives a liquid crystal of a TN (Twisted Nematic) mode by a vertical electric field formed between a pixel electrode and a common electrode arranged opposite to upper and lower substrates. Such a vertical electric field type liquid crystal display device has a disadvantage that the aperture ratio is large, but the viewing angle is narrow to about 90 degrees.

The horizontal electric field type liquid crystal display device forms a horizontal electric field between a pixel electrode and a common electrode arranged in parallel to a lower substrate to drive an in plane switching (IPS) mode liquid crystal. Such an IPS mode liquid crystal display device has a wide viewing angle of about 160 degrees, but has a disadvantage of low aperture ratio and low transmittance. Specifically, in the IPS mode liquid crystal display device, in order to form the in-plane field, the interval between the common electrode and the pixel electrode is formed to be wider than the interval between the upper and lower substrates. In order to obtain an electric field of proper intensity, The electrodes are formed in a band shape having a constant width. An electric field substantially parallel to the substrate is formed between the pixel electrode and the common electrode in the IPS mode, but no electric field is formed in the liquid crystal above the pixel electrode and the common electrode. That is, the liquid crystal molecules placed on the pixel electrode and the common electrode are not driven and maintain the initial alignment state. The liquid crystal that maintains the initial state can not transmit light, which causes a decrease in aperture ratio and transmittance.

A fringe field switching (FFS) type liquid crystal display device operated by a fringe field has been proposed to overcome the disadvantage of the IPS mode liquid crystal display device. The FFS-type liquid crystal display device has a common electrode and a pixel electrode in each pixel region with an insulating film interposed therebetween. The interval between the common electrode and the pixel electrode is narrower than the interval between the upper and lower substrates, To form a parabolic fringe field. The liquid crystal molecules interposed between the upper and lower substrates are operated by the fringe field, so that the aperture ratio and the transmittance can be improved.

1 is a plan view showing a thin film transistor (TFT) substrate constituting a flat panel display panel having an oxide semiconductor layer included in a conventional fringe field type liquid crystal display device. FIG. 2 is a cross-sectional view taken along the cutting line I-I 'in the thin film transistor substrate of the flat panel display shown in FIG.

The thin film transistor substrate shown in FIGS. 1 and 2 includes a gate wiring GL and a data wiring DL intersecting each other with a gate insulating film GI interposed therebetween on a lower substrate SUB and a thin film transistor T). A pixel region is defined by the intersection structure of the gate line GL and the data line DL. The pixel region includes a pixel electrode PXL and a common electrode COM formed with a protective film PAS therebetween to form a fringe field. The pixel electrode PXL has a substantially rectangular shape corresponding to the pixel region, and the common electrode COM is formed into a plurality of parallel strips.

The common electrode COM is connected to the common wiring CL arranged in parallel with the gate wiring. The common electrode COM is supplied with a reference voltage (or common voltage) for liquid crystal driving through the common line CL.

The thin film transistor T responds to the gate signal of the gate line GL so that the pixel signal of the data line DL is charged and held in the pixel electrode PXL. To this end, the thin film transistor T opposes the source electrode S and the source electrode S branched from the gate electrode G branched from the gate line GL, the data line DL, and the pixel electrode PXL, And a semiconductor layer A which overlaps the gate electrode G on the gate insulating film GI and forms a channel between the source electrode S and the drain electrode D. And may further include an ohmic contact layer for ohmic contact between the semiconductor layer (A) and the source electrode (S) and between the semiconductor layer (A) and the drain electrode (D).

Particularly, when the semiconductor layer (A) is formed of an oxide semiconductor material, it is advantageous for a large-area thin film transistor substrate having a high charging capacity due to high charge mobility characteristics. However, it is preferable that the oxide semiconductor material further includes an etch stopper (ES) for protecting the upper surface from the etchant in order to secure the stability of the device. More specifically, the process of separating the source electrode S and the drain electrode D by an etching process includes forming an etch stopper ES to protect the semiconductor layer A from the etchant flowing through the source electrode S and the drain electrode D desirable.

One end of the gate line GL includes a gate pad GP for receiving a gate signal from the outside. The gate pad GP contacts the gate pad terminal GPT through the gate pad contact hole GPH passing through the gate insulating film GI and the protective film PAS. Meanwhile, one end of the data line DL includes a data pad DP for receiving a pixel signal from the outside. The data pad DP contacts the data pad terminal DPT through the data pad contact hole DPH passing through the protective film PAS.

The pixel electrode PXL is connected to the drain electrode D on the gate insulating film GI. On the other hand, the common electrode COM is formed so as to overlap the pixel electrode PXL with the protective film PAS covering the pixel electrode PXL interposed therebetween. An electric field is formed between the pixel electrode (PXL) and the common electrode (COM), and the liquid crystal molecules arranged in the horizontal direction between the TFT substrate and the color filter substrate rotate due to dielectric anisotropy. The transmittance of light passing through the pixel region is varied according to the degree of rotation of the liquid crystal molecules, thereby realizing the gradation.

In the thin film transistor substrate for a flat panel display device having the oxide semiconductor layer A, an oxide semiconductor layer A region that occupies between boundary lines facing each other of the source electrode S and the drain electrode D becomes a channel region. In FIG. 1 and FIG. 2, the areas indicated by hatched lines represent the channel areas. When the channel region includes a metal oxide semiconductor material, the thin film transistor T has excellent characteristics. However, the characteristics of the thin film transistor T through which light penetrates into the channel region from outside repeatedly for a long time are changed, which may cause a problem in the proper operation of the display device.

1 and 2, in a thin film transistor substrate having a bottom gate structure in which the gate electrode G is located below, the gate electrode G may cover a channel region of the semiconductor layer A. Referring to FIG. Therefore, the external light flowing from the lower portion can be blocked to some extent. However, there is no way to block external light flowing from the top. In this case, the light shielding layer LS may further include a light blocking layer LS to block light from the upper portion of the thin film transistor T to block external light flowing from the upper portion.

3 is a cross-sectional view illustrating paths through which external light flows in a thin film transistor substrate further including a light blocking layer on the thin film transistor illustrated in FIG. 1. In this case, the light blocking layer LS is formed of the same material as the gate electrode G. The light blocking layer LS may be connected to the gate electrode G to have a double gate structure. That is, the semiconductor channel layer A may be interposed between the gate electrode G and the light blocking layer LS to protect from external light flowing from the upper and lower portions.

However, since the light blocking layer LS and the gate electrode G include a metal material, and the source-drain electrodes S and D also include a metal material, there is a problem in blocking external light completely. For example, a small amount of external light incident between the gate electrode G and the source-drain electrodes S and D may reflect and flow into the channel region. In addition, the external light incident from the lower portion to the light blocking layer LS may be reflected by the light blocking layer LS and introduced into the channel region.

This is due to the extremely low light transmittance of the metal, which is effective in blocking external light directly. However, since the light reflectance is very high, the metal reflects the light flowing into the side gap and leads to the channel region. Therefore, in the case of a thin film transistor substrate for a flat panel display device using the metal oxide semiconductor layer A as a channel layer, an efficient method for preventing external light from penetrating into the channel region is required.

SUMMARY OF THE INVENTION An object of the present invention is to overcome the problems caused by the prior art, and to provide a thin film transistor substrate for a flat panel display and a method of manufacturing the same, which prevents light from entering into a channel region including a metal oxide semiconductor material. have. Another object of the present invention is to provide a thin film transistor substrate for a flat panel display and a method of manufacturing the same, which prevent external light from being reflected into a channel region including a metal oxide semiconductor material and flowing into the channel region.

A thin film transistor substrate including a metal oxide semiconductor according to the present invention for achieving the object of the present invention, the substrate; A thin film transistor formed on the substrate; A lower light absorbing layer having a size corresponding to the thin film transistor between the substrate and the thin film transistor; A protective film covering the thin film transistor; And an upper light absorbing layer having a size corresponding to the thin film transistor on the passivation layer.

At least one of the lower light absorbing layer and the upper light absorbing layer is a semiconductor material including at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and copper (Cu) and zinc (Zn) It is characterized in that formed with at least one of the oxide semiconductor material containing at least one of.

At least one of the lower light absorbing layer and the upper light absorbing layer has a thickness of 100 kPa to 5000 kPa.

At least one of the lower light absorbing layer and the upper light absorbing layer may include a material having a lower light reflectance than the metal material.

In addition, the method of manufacturing a thin film transistor substrate including a metal oxide semiconductor according to the present invention includes forming a lower light absorbing layer on the substrate; Forming a buffer layer covering the light absorbing layer; Forming a thin film transistor in an area overlapping the light absorbing layer; Forming a protective film covering the thin film transistor; And forming an upper light absorbing layer having a size corresponding to the thin film transistor on the passivation layer.

At least one of the lower light absorbing layer and the upper light absorbing layer is a semiconductor material including at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and copper (Cu) and zinc (Zn) It is characterized in that formed with at least one of the oxide semiconductor material containing at least one of.

At least one of the lower light absorbing layer and the upper light absorbing layer may be formed to have a thickness of 100 kPa to 5000 kPa.

At least one of the lower light absorbing layer and the upper light absorbing layer is formed of a material having a lower light reflectance than the metal material.

The present invention is characterized in that each of the lower and upper portions of the thin film transistor including the metal oxide semiconductor material is provided with a light absorbing layer including a semiconductor material having a low light reflectance and a high light absorbance. Therefore, not only the direct irradiation from the outside to the channel region can be prevented, but also light absorbed from the inner surface can be prevented from being induced to the channel region by the light reflection from the inside. That is, the present invention can maintain the characteristics of the thin film transistor by preventing almost no light from flowing into the channel region as a semiconductor material having excellent light absorption. In addition, since the light absorbing layers disposed on the upper and lower portions of the thin film transistor are non-metallic materials, charge accumulation due to the optoelectronic effect or the like does not occur in the light absorbing layer. Therefore, parasitic capacitance does not occur even when the light absorbing layer is electrically floated, so that the thin film transistor is not affected. As a result, in an organic light emitting display device in which a plurality of thin film transistors are arranged per unit pixel cell, the light absorbing layer can be formed in a wide range over the entire area except the opening area.

1 is a plan view showing a thin film transistor substrate constituting a flat panel display panel having an oxide semiconductor layer included in a conventional fringe field type liquid crystal display device.
2 is a cross-sectional view taken along the cutting line I-I 'in the thin film transistor substrate of the flat panel display shown in FIG.
3 is a cross-sectional view illustrating paths through which external light flows in a thin film transistor substrate further including a light blocking layer on an upper portion of the thin film transistor illustrated in FIG. 1.
4 is a plan view illustrating a thin film transistor substrate having an oxide semiconductor layer included in a fringe field type liquid crystal display device according to a first embodiment of the present invention.
FIG. 5 is a cross-sectional view taken along the line II-II ′ of the thin film transistor substrate of the flat panel display shown in FIG. 4. FIG.
6A through 6C are cross-sectional views illustrating a process of forming a thin film transistor substrate having an oxide semiconductor layer according to a first embodiment of the present invention illustrated in FIG. 5.
7 is a plan view illustrating a thin film transistor substrate having an oxide semiconductor layer included in an organic light emitting diode display according to a second exemplary embodiment of the present invention.
FIG. 8 is a cross-sectional view taken along the line III-III ′ of a thin film transistor substrate of the organic light emitting diode display illustrated in FIG. 7.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

Hereinafter, a thin film transistor substrate constituting a flat panel display panel having an oxide semiconductor layer according to a first embodiment of the present invention will be described with reference to FIGS. 4 to 5. 4 is a plan view illustrating a thin film transistor substrate having an oxide semiconductor layer included in a fringe field type liquid crystal display device according to a first embodiment of the present invention. FIG. 5 is a cross-sectional view taken along the line II-II ′ of the thin film transistor substrate of the liquid crystal display shown in FIG. 4.

The thin film transistor substrate shown in FIGS. 4 and 5 includes a gate wiring GL and a data wiring DL intersecting each other with a gate insulating film GI interposed therebetween on a lower substrate SUB and a thin film transistor T). A pixel region is defined by the intersection structure of the gate line GL and the data line DL. The pixel region includes a pixel electrode PXL and a common electrode COM formed with a protective film PAS therebetween to form a fringe field. The pixel electrode PXL has a substantially rectangular shape corresponding to the pixel region, and the common electrode COM is formed into a plurality of parallel strips.

The common electrode COM is connected to the common wiring CL arranged in parallel with the gate wiring. The common electrode COM is supplied with a reference voltage (or common voltage) for liquid crystal driving through the common line CL.

The thin film transistor T responds to the gate signal of the gate line GL so that the pixel signal of the data line DL is charged and held in the pixel electrode PXL. To this end, the thin film transistor T opposes the source electrode S and the source electrode S branched from the gate electrode G branched from the gate line GL, the data line DL, and the pixel electrode PXL, And a semiconductor layer A which overlaps the gate electrode G on the gate insulating film GI and forms a channel between the source electrode S and the drain electrode D. And may further include an ohmic contact layer for ohmic contact between the semiconductor layer (A) and the source electrode (S) and between the semiconductor layer (A) and the drain electrode (D).

In particular, when the semiconductor layer A is formed of an oxide semiconductor material including a metal oxide such as indium gallium zinc oxide (IGZO), it is advantageous for a large area thin film transistor substrate having a large charge capacity due to its high charge mobility property. However, it is preferable that the oxide semiconductor material further includes an etch stopper (ES) for protecting the upper surface from the etchant in order to secure the stability of the device. More specifically, the process of separating the source electrode S and the drain electrode D by an etching process includes forming an etch stopper ES to protect the semiconductor layer A from the etchant flowing through the source electrode S and the drain electrode D desirable.

One end of the gate line GL includes a gate pad GP for receiving a gate signal from the outside. The gate pad GP contacts the gate pad terminal GPT through the gate pad contact hole GPH passing through the gate insulating film GI and the protective film PAS. Meanwhile, one end of the data line DL includes a data pad DP for receiving a pixel signal from the outside. The data pad DP contacts the data pad terminal DPT through the data pad contact hole DPH passing through the protective film PAS.

The pixel electrode PXL is connected to the drain electrode D on the gate insulating film GI. On the other hand, the common electrode COM is formed so as to overlap the pixel electrode PXL with the protective film PAS covering the pixel electrode PXL interposed therebetween. An electric field is formed between the pixel electrode (PXL) and the common electrode (COM), and the liquid crystal molecules arranged in the horizontal direction between the TFT substrate and the color filter substrate rotate due to dielectric anisotropy. The transmittance of light passing through the pixel region is varied according to the degree of rotation of the liquid crystal molecules, thereby realizing the gradation.

In the first embodiment of the present invention, the channel layer A including the metal oxide semiconductor material, particularly the channel region, is further provided with an absorbing layer for absorbing light from the outside. The channel region is an oxide semiconductor layer A region that occupies between boundary lines of the source electrode S and the drain electrode D facing each other. In the semiconductor channel layers A of FIGS. 4 and 5, regions indicated by hatched lines represent channel regions.

For example, the lower light absorbing layer LLA is disposed under the gate electrode G in order to block and absorb light flowing from the lower surface of the substrate SUB. The size of the lower light absorbing layer LLA is preferably at least larger than the channel region. In order to effectively prevent the light flowing from the outside, it is preferable to have a size capable of covering the entire thin film transistor T in a range that does not invade the opening region formed by the pixel electrode PXL and the common electrode COM.

In addition, in order to block and absorb light flowing from the upper surface of the substrate SUB, an upper light absorbing layer ULA is disposed on the thin film transistor T. In particular, it is preferable to form the passivation layer PAS covering the upper light absorbing layer ULA source-drain electrode S-D. The size of the upper light absorbing layer ULA is preferably at least larger than the channel region. In order to effectively prevent the light flowing from the outside, it is preferable to have a size capable of covering the entire thin film transistor T in a range that does not invade the opening region formed by the pixel electrode PXL and the common electrode COM.

The lower light absorbing layer LLA and the upper light absorbing layer ULA may include a material having a lower reflectance of light than a metal material. Therefore, the lower light absorbing layer LLA and the upper light absorbing layer ULA preferably include a non-metallic material. In addition, the lower light absorbing layer (LLA) and the upper light absorbing layer (ULA) preferably include a material having a high light absorption rate. To this end, the lower light absorbing layer (LLA) and the upper light absorbing layer (ULA) may be formed of a semiconductor material composed of a combination of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), silicon (Si), or germanium (Ge). It is preferable to form at least one of a semiconductor material made of a single material and an oxide semiconductor material including at least one of copper (Cu) and zinc (Zn).

Meanwhile, the lower light absorbing layer LLA and the upper light absorbing layer ULA should have low light transmittance. The transmission of light is determined by the thickness of the thin film while taking into account the intrinsic properties of the material. Therefore, when the lower light absorbing layer LLA and the upper light absorbing layer ULA are formed of a semiconductor material, the lower light absorbing layer LLA and the upper light absorbing layer LUL are preferably formed to have a thickness of 100 nm (10 nm) to 5000 nm (500 nm).

Hereinafter, a method of manufacturing a thin film transistor substrate constituting a flat panel display panel having an oxide semiconductor layer included in a fringe field type liquid crystal display device according to a first embodiment of the present invention. 6A through 6C are cross-sectional views illustrating a process of forming a thin film transistor substrate having an oxide semiconductor layer according to a first embodiment of the present invention illustrated in FIG. 5.

Semiconductor material composed of a combination of silicon (Si), germanium (Ge) and silicon-germanium (SiGe) on a transparent glass substrate (SUB), a semiconductor material made of a single material of silicon (Si) or germanium (Ge), and copper ( At least one of the oxide semiconductor materials including at least one of Cu) and zinc (Zn) is applied to a thickness of 100 kPa to 5000 kPa and patterned to form a lower light absorbing layer LLA. In this case, the lower light absorbing layer LLA is preferably formed to have a size corresponding to the size of the thin film transistor T to be formed in the future. The buffer layer BF is coated with silicon oxide (SiOx) or silicon nitride (SiNx) on the entire upper surface of the substrate SUB on which the lower light absorbing layer LLA is formed. (FIG. 6A)

The thin film transistor T is disposed on the gate layer GL, the data line DL, and the intersection of the gate line GL and the data line DL on the buffer layer BF. The passivation layer PAS is coated on the entire surface of the substrate SUB on which the thin film transistor T is formed. The pixel electrode PXL connected to the drain electrode D of the thin film transistor T is formed of a transparent conductive material on the passivation layer PAS. In the case of a horizontal electric field type thin film transistor substrate, a common electrode COM is further formed. (Fig. 6B)

On the passivation layer (PAS), a semiconductor material composed of a combination of silicon (Si), germanium (Ge) and silicon-germanium (SiGe), a semiconductor material composed of a single material of silicon (Si) or germanium (Ge), and copper (Cu) ) And at least one of an oxide semiconductor material including at least one of zinc (Zn) and a pattern of 100 μm to 5000 μm to form a top light absorbing layer (ULA) to overlap the thin film transistor (T). In this case, the upper light absorbing layer ULA preferably has a size corresponding to the size of the thin film transistor T formed thereunder. (Fig. 6C)

Hereinafter, a thin film transistor substrate constituting a flat panel display panel having an oxide semiconductor layer according to a second embodiment of the present invention will be described with reference to FIGS. 7 and 8. 7 is a plan view illustrating a thin film transistor substrate having an oxide semiconductor layer included in an organic light emitting diode display according to a second exemplary embodiment of the present invention. FIG. 8 is a cross-sectional view taken along the line III-III ′ of the thin film transistor substrate of the organic light emitting diode display illustrated in FIG. 7.

7 and 8, a thin film transistor substrate for an organic light emitting display device includes a switching TFT (ST), a driving TFT (DT) connected to the switching TFT, and an anode electrode (ANO) of an organic light emitting diode connected to the driving TFT (DT). It includes. Although not illustrated, organic materials and cathode electrodes formed in the organic light emitting diode deposition process are stacked on the anode ANO.

On the glass substrate SUB, the switching TFT ST is formed at a position where the gate line GL and the data line DL cross each other. The switching TFT ST functions to select a pixel. The switching TFT ST includes a gate electrode SG branching from the gate line GL, a semiconductor channel layer SA, a source electrode SS, and a drain electrode SD. The driving TFT DT serves to drive the anode electrode ANO of the pixel selected by the switching TFT ST. The driving TFT DT includes a gate electrode DG connected to the drain electrode SD of the switching TFT ST, a source electrode DS connected to the semiconductor channel layer DA, the driving current transmission line VDD, and a drain. It includes an electrode DD. The drain electrode DD of the driving TFT DT is connected to the anode electrode ANO of the organic light emitting diode.

The thin film transistor illustrated in FIG. 8 has a top gate structure. Therefore, the semiconductor channel layer SA of the switching TFT ST and the semiconductor channel layers DA of the driving TFT DT are formed first, and the gate electrodes SG and DG are formed on the gate insulating layer GI covering the semiconductor channel layer SA. The semiconductor channel layers SA and DA are overlapped with each other. Meanwhile, source electrodes SS and DS and drain electrodes SD and DD are connected to both side surfaces of the semiconductor channel layers SA and DA through contact holes. The source electrodes SS and DS and the drain electrodes SD and DD are formed on the insulating layer INS covering the gate electrodes SG and DG.

A gate pad GP formed at one end of each gate line GL and a data pad DP formed at one end of each data line DL are formed in the outer periphery of the display region where the pixel region is disposed, A driving current pad VDP formed at one end of the current transfer wiring VDD is disposed. The protective film PAS is entirely coated on the substrate SUB on which the switching TFT ST and the driving TFT DT are formed. A contact hole exposing the gate pad GP, the data pad DP, the driving current pad VDP, and the drain electrode DD of the driving TFT DT is formed. Then, a flattening film PL is applied onto the display area of the substrate SUB. The planarization layer PL serves to uniformize the roughness of the substrate surface in order to apply the organic material constituting the organic light emitting diode in a smooth planar state.

An anode electrode ANO is formed on the planarizing film PL in contact with the drain electrode DD of the driving TFT DT through the contact hole. The gate pad GP, the data pad DP, and the gate formed on the driving current pad VDP, which are exposed through the contact hole formed in the passivation film PAS, are formed on the outer periphery of the display region where the planarization film PL is not formed. A pad terminal GPT, a data pad terminal DPT, and a driving current pad terminal VDPT, respectively. The bank BA is formed on the substrate SUB except for the pixel region in the display region. The spacer SP is further formed on a portion of the bank BA.

In a second embodiment of the present invention, the channel layer A including the metal oxide semiconductor material, particularly, the channel region, is further provided with an absorbing layer for absorbing light flowing from the outside. In the case of the second embodiment, since the thin film transistor has a top gate structure, the channel region may include the gate electrodes SG and DG disposed between the source electrodes SS and DS and the drain electrodes SD and DD. Overlapping oxide semiconductor layers SA and DA regions. 7 and 8 represent regions indicated by hatched lines of the semiconductor channel layers SA and DA.

For example, the lower light absorbing layer LLA is disposed under the gate electrodes SG and DG to block and absorb light flowing from the lower surface of the substrate SUB. In particular, in an organic light emitting display device, two or more thin film transistors are disposed. Therefore, the lower light absorbing layer LLA preferably has an area including the semiconductor layers SA and DA of all the thin film transistors ST and DT. In order to effectively prevent light flowing from the outside, it is preferable that the thin film transistors ST and DT be sized to cover the entire thin film transistors ST and DT in a range that does not invade the opening region occupied by the pixel electrode PXL. In FIG. 7, the entire non-opening region except for the pixel electrode PXL is formed.

In addition, the upper light absorbing layer ULA is disposed on the thin film transistors ST and DT in order to block and absorb light flowing from the upper surface of the substrate SUB. In particular, it is preferable to form the passivation layer PAS covering the upper light absorbing layer ULA source-drain electrodes SS-SD and DS-DD. The size of the upper light absorbing layer ULA is preferably at least larger than the channel region. In order to effectively prevent light flowing from the outside, it is preferable that the thin film transistors ST and DT be sized to cover the entire thin film transistors ST and DT in a range that does not invade the opening region occupied by the pixel electrode PXL. In FIG. 7, the sizes of the lower light absorbing layer LLA and the upper light absorbing layer ULA are the same.

The lower light absorbing layer LLA and the upper light absorbing layer ULA may include a material having a lower reflectance of light than a metal material. Therefore, the lower light absorbing layer LLA and the upper light absorbing layer ULA preferably include a non-metallic material. In addition, the lower light absorbing layer (LLA) and the upper light absorbing layer (ULA) preferably include a material having a high light absorption rate. To this end, the lower light absorbing layer (LLA) and the upper light absorbing layer (ULA) may be formed of a semiconductor material composed of a combination of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), silicon (Si), or germanium (Ge). It is preferable to form at least one of a semiconductor material made of a single material and an oxide semiconductor material including at least one of copper (Cu) and zinc (Zn).

Meanwhile, the lower light absorbing layer LLA and the upper light absorbing layer ULA should have low light transmittance. The transmission of light is determined by the thickness of the thin film while taking into account the intrinsic properties of the material. Accordingly, the lower light absorbing layer (LLA) and the upper light absorbing layer (ULA) may be formed of a semiconductor material, silicon, silicon, or germanium (Ge), which are composed of a combination of silicon (Si), germanium (Ge), and silicon-germanium (SiGe). In the case of forming at least one of a semiconductor material made of a material and an oxide semiconductor material including at least one of copper (Cu) and zinc (Zn), the thickness is preferably formed in a thickness of 100 kPa to 5000 kPa.

The light absorbing layer according to the present invention has extremely low light reflectance compared to the metal material, the light transmittance is similar to the metal material, and the light absorbance is superior to the metal material. Therefore, since the light that can enter the semiconductor channel layer from the outside can be blocked more efficiently than the light blocking layer formed of the metal material, the characteristics of the thin film transistor element using the metal oxide semiconductor material can be maintained for a long time.

In particular, the light absorbing layer according to the present invention is characterized in that it is formed of a semiconductor material rather than a metal material. When forming the light absorbing layer with the metal, the charge may be induced by the optoelectronic effect and / or a similar phenomenon while the metal blocks the light. In this case, the channel characteristics of the thin film transistors above or below may be affected to deteriorate device characteristics. If the light absorbing layer is formed even to a region other than the channel region, the capacitance is further generated and the conditions of the element operation greatly change. Therefore, the metal light absorbing layer should be formed as small as possible.

In addition, in order to prevent charges from being induced in the light absorbing layer made of metal, it is necessary to connect the wirings to release the charged charges to the outside. If the light absorbing layer is formed to a minimum size, the light flowing through the reflection path cannot be effectively prevented. In addition, when the light absorbing layer is connected to the wiring to discharge the induced charges, a contact hole must be formed, which causes the opening area to be reduced.

However, as in the present invention, when the light absorbing layer is formed of a semiconductor material, since the semiconductor has an energy band gap, even in the case of having a conductive property such as metal, the channel layer of the thin film transistor disposed in the lower and upper portions by the charge is induced. The problem does not occur. Therefore, since the area of the light absorbing layer can be formed to the maximum area, it is possible to effectively block all light introduced by the reflection path. In addition, since it is not necessary to form a contact hole for connecting the wiring for discharging the electric charge, the opening area can be secured to the maximum.

As the semiconductor material used as the light absorbing layer in the present invention, any of P type and N type may be used. Moreover, any kind, such as amorphous, microcrystal, and polycrystal, may be sufficient. In addition, the semiconductor material can adjust the resistivity by doping impurities. For example, in the process of forming the semiconductor material to be used for the light absorbing layer described above by the deposition or sputtering method, the impurity doping concentration is adjusted to be low, so that the formed light absorbing layer may have a specific resistance of an insulator level such as an insulating layer. The non-conductive thin film can form a light shielding layer meeting the object of the present invention.

As another example, after depositing a semiconductor material to be used for the light absorbing layer, it may be formed into a light absorbing layer having a specific resistance of the metal level through thermal surface treatment, plasma treatment or impurity implantation. In this case, the thin film transistor having a double gate structure may be implemented by using the gate electrode as an additional gate electrode. Alternatively, it may be used as an electrode of a storage capacitor.

As another example, if necessary, a semiconductor material to be used for the light absorbing layer may be deposited under general semiconductor deposition process conditions to form a light absorbing layer having a semiconductor-specific resistivity. As described above, the light absorption layer formed of the semiconductor material has a specific resistance of 0.1 ohm · cm to 1.0 × ^{10 7} so as to have electrical properties of any one of non-conductor, semiconductor, and conductor, without causing problems in metals. It can be adjusted randomly in the ohm · cm range.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the present invention should not be limited to the details described in the detailed description but should be defined by the claims.

T: Thin film transistor SUB: Substrate
GL: Gate wiring CL: Common wiring
DL: data wiring PXL: pixel electrode
COM: common electrode GP: gate pad
DP: Data pad GPT: Gate pad terminal
DPT: Data pad terminal GPH: Gate pad contact hole
DPH: Data pad contact hole ES: Etch stopper
G: gate electrode S: source electrode
D: drain electrode A: semiconductor channel layer
GI: gate insulating film PAS: protective film
LS: light blocking layer
LLA: lower light absorbing layer ULA: upper light absorbing layer

Claims (8)

Board;
A thin film transistor formed on the substrate;
A lower light absorbing layer having a size corresponding to the thin film transistor between the substrate and the thin film transistor;
A passivation layer covering the thin film transistor; And
And an upper light absorbing layer having a size corresponding to the thin film transistor on the passivation layer.
The method of claim 1,
At least one of the lower light absorbing layer and the upper light absorbing layer is a semiconductor material including at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and copper (Cu) and zinc (Zn) A thin film transistor substrate, characterized in that formed with at least one of the oxide semiconductor material including at least one of.
The method of claim 1,
At least one of the lower light absorbing layer and the upper light absorbing layer has a thickness of 100 kPa to 5000 kPa.
The method of claim 1,
At least one of the lower light absorbing layer and the upper light absorbing layer comprises a material having a lower light reflectance than a metal material.
Forming a lower light absorbing layer on the substrate;
Forming a buffer layer covering the light absorbing layer;
Forming a thin film transistor in an area overlapping the light absorbing layer;
Forming a protective film covering the thin film transistor; And
And forming an upper light absorbing layer having a size corresponding to the thin film transistor on the passivation layer.
The method of claim 5, wherein
At least one of the lower light absorbing layer and the upper light absorbing layer is a semiconductor material including at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and copper (Cu) and zinc (Zn) And forming at least one of an oxide semiconductor material including at least one of the above.
The method of claim 5, wherein
At least one of the lower light absorbing layer and the upper light absorbing layer is formed to have a thickness of 100 kPa to 5000 kPa.
The method of claim 5, wherein
At least one of the lower light absorbing layer and the upper light absorbing layer is formed of a material having a light reflectance lower than that of a metal material.

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