KR20130092341A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to improve the operation properties of a memory device by enhancing the interface property between a charge trap layer and a charge blocking layer. CONSTITUTION: A word line and an interlayer insulating layer (22) are laminated alternately on substrate. A vertical channel layer (26) is protruded from the substrate and penetrates the word line and interlayer insulating layer. A tunnel insulating layer (25) surrounds the vertical channel layer. A charge trap layer (24A) comprises a first area at a position corresponding to a conductive layer (30) and a second part at a position corresponding to the interlayer insulating layer. A first charge blocking layer (28) surrounds the first area of the charge trap layer.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor device,

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a three-dimensional nonvolatile memory device and a manufacturing method thereof.

A non-volatile memory device is a memory device in which stored data is retained even if power supply is interrupted. Recently, as the degree of integration of a memory device having a two-dimensional structure that manufactures a memory device in a single layer on a silicon substrate has reached a limit, a non-volatile memory device having a three-dimensional structure in which memory cells are stacked vertically from a silicon substrate has been proposed. .

Hereinafter, a structure of a 3D nonvolatile memory device according to the related art will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of a nonvolatile memory device having a three-dimensional structure according to the prior art, in particular, a region in which memory cells are stacked.

As shown in FIG. 1, a three-dimensional nonvolatile memory device according to the prior art includes a plurality of memories stacked along vertical channel films CH and vertical channel films CH protruding from a substrate (not shown). It contains cells.

A brief description of a method of forming a memory cell is as follows. First, the sacrificial layers and the interlayer insulating layers 11 are alternately formed, and then the channel holes are formed by etching them. Subsequently, after the vertical channel layers CH are formed in the channel holes, the sacrificial layers and the interlayer insulating layers 11 are etched to form slits between the vertical channel layers CH. Subsequently, open regions are formed by removing the sacrificial layers exposed on the inner walls of the slits, and the memory layer 12 is formed along the inner surfaces of the open regions. Here, the memory film 12 includes a charge blocking film, a charge trap film, and a tunnel insulating film, and each film is formed using a deposition process. Subsequently, the conductive film 13 is buried in open regions in which the memory film 12 is formed. As a result, a plurality of memory cells stacked on the substrate are formed.

However, according to the related art as described above, since the conductive film 13 is embedded after the memory film 12 is formed in the open regions, the height of the stacked films is increased, which makes it difficult to improve the integration degree of the memory device. . In addition, since the insulating film deposited by the chemical vapor deposition method is used as the charge blocking film, the film quality of the charge blocking film is low, thereby deteriorating the characteristics of the memory device.

An embodiment of the present invention provides a semiconductor device suitable for improving the degree of integration of a memory device by lowering the height of stacked films and a method of manufacturing the same.

According to an embodiment of the present invention, word lines and interlayer insulating layers are alternately stacked on a substrate; Vertical channel layers protruding from the substrate and penetrating the word lines and the interlayer insulating layers; A tunnel insulating layer surrounding the vertical channel layers; A charge trap film surrounding the tunnel insulating film, wherein a first region between the tunnel insulating film and the word lines has a thickness thinner than a second region between the tunnel insulating film and the interlayer insulating films; And first charge blocking layer patterns surrounding the first region of the charge trap layer.

According to another embodiment of the present invention, the steps of alternately forming the first material film and the second material film; Etching the first material layers and the second material layers to form channel holes; Forming vertical channel layers, a tunnel insulating layer surrounding the vertical channel layers, and a charge trap layer surrounding the tunnel insulating layer in the channel holes; Etching the first material layers and the second material layers to form a slit between adjacent channel holes; Removing the first material films exposed in the slit; Forming a first charge blocking layer pattern by partially oxidizing the charge trap layer exposed to a region where the first material layers are removed; And forming a conductive film in a region from which the first material films are removed.

According to another embodiment of the present invention, the steps of alternately forming the first material film and the second material film; Etching the first material layers and the second material layers to form channel holes; Forming first charge blocking layer patterns by partially oxidizing the first material layers exposed to inner surfaces of the channel holes; And forming vertical channel layers, a tunnel insulating layer surrounding the vertical channel layers, and a charge trap layer surrounding the tunnel insulating layer in the channel holes.

The semiconductor device includes a charge blocking film formed by partially oxidizing a first material film or a charge trap film. Therefore, compared with the related art, the height of the stacked layers can be lowered to improve the degree of integration of the memory device. In addition, by forming the charge blocking film by the oxidation method, the film quality of the charge blocking film can be improved, and the interface characteristics between the charge trap film and the charge blocking film can be improved, thereby improving the operating characteristics of the memory device.

1 is a cross-sectional view of a nonvolatile memory device having a three-dimensional structure according to the prior art.
2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.
3 and 4 are cross-sectional views of a semiconductor device to which the first embodiment of the present invention is applied.
5A through 5C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.
6 and 7 are cross-sectional views of a semiconductor device to which a second embodiment of the present invention is applied.
8A to 8C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention.
9 and 10 are cross-sectional views of a semiconductor device to which a third embodiment of the present invention is applied.
11 is a graph illustrating erase characteristics of a semiconductor device to which at least one of the first to third embodiments of the present invention is applied.
12 is a configuration diagram illustrating a configuration of a memory system according to an embodiment of the present invention.
13 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present invention.

Hereinafter, the most preferred embodiment of the present invention will be described. In the drawings, the thickness and the spacing are expressed for convenience of explanation, and can be exaggerated relative to the actual physical thickness. In describing the present invention, known configurations irrespective of the gist of the present invention may be omitted. It should be noted that, in the case of adding the reference numerals to the constituent elements of the drawings, the same constituent elements have the same number as much as possible even if they are displayed on different drawings.

2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention, and show regions in which memory cells are stacked.

As shown in FIG. 2A, first material layers 21 and second material layers 22 are alternately formed on a substrate (not shown) on which a desired lower structure is formed. Here, the lower structure may be a source region, a pipe gate, or the like.

Here, the first material layer 21 is for forming word lines, selection lines, and the like, and the second material layer 22 is for electrically separating the stacked word lines, selection lines, and the like. The first material film 21 and the second material film 22 are formed of a material having a high etch selectivity. In the first embodiment, the first material film is formed of a sacrificial film such as a nitride film, and the second material films 22 are formed of an interlayer insulating film such as an oxide film.

Subsequently, the first material layers 21 and the second material layers 22 are etched to form channel holes. The channel holes are for forming vertical channel layers and may be arranged in a matrix form.

Subsequently, the charge trap film 24 is formed on the inner walls of the channel holes. Here, the charge trap film 24 is formed to have a uniform thickness along the inner walls of the channel holes, and is formed to a sufficient thickness in consideration of the thickness to be oxidized during the subsequent first charge blocking film forming process. The charge trap layer 24 includes a first region at a position corresponding to the conductive layers 30 and a second region at a position corresponding to the second material layers 22, and the first region and the second region may be Alternately arranged.

Subsequently, a tunnel insulating film 25 is formed on the charge trap film 24. The tunnel insulation layer 25 may be formed using a deposition process, or may be formed by partially oxidizing the charge trap layer 24. When the tunnel insulating film 25 is formed by the oxidation process, the interface between the tunnel insulating film 25 and the charge trap film 24 is not exposed to the outside, so that the interface characteristics can be improved.

Next, a vertical channel film 26 is formed on the tunnel insulating film 25. Here, the vertical channel layer 26 may be formed of a semiconductor film, or the like, and may be formed in the form of a tube in which the center region is open, or in a form completely filled up to the center region. When the center region is open, an insulating film 27 such as a fluid oxide film is embedded in the open center region.

Meanwhile, before forming the charge trap layer 24, the buffer layer 23 may be formed on the inner walls of the channel holes. When the buffer layer 23 is formed in this manner, it is possible to prevent the charge trap layer 24 and the like from being damaged during the subsequent process of removing the first material layer 21.

As shown in FIG. 2B, the first material layers 21 and the second material layers 22 are etched to form slits S between the vertical channel layers 26. In this case, all of the slits S may be formed between the vertical channel layers 26, or only a portion thereof.

Subsequently, the first material layers 21 exposed on the inner wall of the slits S are removed to form an open region. The open area is an area where a word line or a selection line is to be formed. For example, when the first material layers 21 are formed of a nitride film and the second material layers 22 are formed of an oxide film, the first material layers 22 remain while using the phosphoric acid solution. The films 21 may be selectively removed.

In this case, as the first material layers 21 are removed, the first region of the charge trap layer 24 is exposed. For reference, as described above, when the buffer layer 23 is formed on the inner walls of the channel holes, the buffer layer 23 is exposed by removing the first material layers 21. Accordingly, the exposed buffer layer 23 is etched to expose the first region of the charge trap layer 24. In this case, the buffer layer patterns 23A remain between the charge trap layer 24 and the second material layers 22. That is, buffer layer patterns 23A surrounding the second region of the charge trap layer 24 are formed.

Subsequently, the first material layers 21 are removed to partially oxidize the exposed charge trap layer 24 to form first charge blocking layer patterns 28. As such, when the charge trap layer 24 is oxidized to form the first charge blocking layer patterns 28, the interface between the charge trap layer 24 and the first charge blocking layer patterns 28 is not exposed to the outside. The interface property can be improved.

At this time, since only the exposed portions of the charge trap film 24 are removed by oxidizing, the outer surface of the charge trap film 24 has irregularities. For example, the oxidized first region is recessed, and the other second regions are recessed in the form of iron.

As illustrated in FIG. 2C, after the conductive film 30 is filled in the open regions in which the first charge blocking film patterns 28 are formed, the insulating film 31 is embedded in the slits S. Referring to FIG. Here, the conductive film 30 may be used as a word line or a selection line, and may be a metal film such as tungsten.

Meanwhile, before forming the conductive film 30, the second charge blocking films 29 may be further formed along the inner surfaces of the open regions in which the first charge blocking film patterns 28 are formed. In this case, second charge blocking layers 29 are formed between the first charge blocking layer patterns and the conductive layers 30 and between the conductive layers 30 and the second material layers 22. Here, the second charge blocking layer 29 may be formed of a dielectric film having a high dielectric constant such as aluminum oxide film (Al ₂ O ₃ ), or may be formed by stacking a dielectric film having a silicon oxide film (SiO ₂ ) and a high dielectric constant. In this manner, by further forming the second charge blocking film 29, the erase characteristic can be further improved.

As a result, memory cells stacked along the vertical channel layers 26 are formed. That is, the conductive layers 30 and the second material layers 22 alternately stacked on the substrate (not shown) may protrude from the substrate to form the conductive layers 30 and the second material layers 22. The first region between the tunnel insulating layer 25 and the conductive layers 30 surrounding the vertical channel layers 26, the tunnel insulating layer 25 surrounding the vertical channel layers 26, and the tunnel insulating layer 25 is formed. The charge trap film 24A having a thickness thinner than the second area between the tunnel insulating film 25 and the second material films 22, and the first charge blocking film patterns surrounding the first area of the charge trap film 24A. 28 is formed.

According to the first embodiment as described above, the first material films are removed to oxidize the exposed charge trap film to form a charge blocking film. Therefore, since the charge blocking film is not formed on the surface of the interlayer insulating film in the open region, the height of the laminated films can be reduced as compared with the related art. In addition, the film quality of the interface between the charge trap film and the charge blocking film can be improved.

3 is a cross-sectional view of a three-dimensional nonvolatile memory device to which memory cells described with reference to the first embodiment of the present invention are applied.

As shown in FIG. 3, the three-dimensional nonvolatile memory device according to the second exemplary embodiment of the present invention may include word lines WL and word lines stacked on the pipe gate PG and the pipe gate PG. Selection lines SL stacked on at least one layer on WL). In addition, the channel film CH of the memory device is formed to include a pipe channel film P_CH and at least one vertical channel film V_CH connected to the pipe channel film P_CH formed in the pipe gate PG. According to such a structure, the strings are arranged in a U shape.

A brief description of a method of manufacturing a memory device is as follows.

First, trenches are formed by etching the pipe gate PG. Subsequently, after filling the sacrificial layers in the trenches, the first material layers 21 and the second material layers 22 are alternately formed. Subsequently, the first material layers 21 and the second material layers 22 are etched to form channel holes connected to the trenches. In this case, channel holes are formed to connect each trench to at least one pair of channel holes. Subsequently, after the sacrificial film exposed to the bottom of the channel holes is removed, the charge trap film, the tunnel insulating film, and the channel film are formed on the inner surfaces of the trench and the channel holes. Subsequently, the process of forming the slits and removing the first material layers 21 to form the first charge blocking layer patterns 28 may be performed in the same manner as described in the first embodiment.

According to this process, the tunnel insulating film 25 and the charge trap film 24A surrounding the vertical channel films V_CH are formed to further surround the pipe channel film P_CH. In addition, when the buffer film 23A is formed before the charge trap film 24A is formed, the tunnel insulation film 25, the charge trap film 24A, and the buffer film 23A may surround the pipe channel film P_CH. Is formed. Here, the tunnel insulating film 25, the charge trap film 24A, and the buffer film 23A surrounding the pipe channel film P_CH are used as the gate insulating film of the pipe transistor, so that the gate insulating film is controlled by adjusting the thickness of the buffer film 23A. The thickness of can be adjusted easily.

4 is a cross-sectional view of a three-dimensional nonvolatile memory device to which the memory cells described with reference to the first embodiment of the present invention are applied.

As shown in FIG. 4, in the three-dimensional nonvolatile memory device according to the third embodiment of the present invention, at least one lower select line LSL sequentially stacked on the substrate 40 having the source region S. FIG. ), Word lines WL and at least one layer top select line USL.

The lower select line LSL, the word lines WL, and the upper select line USL may be simultaneously formed or respectively formed. When the lower select line LSL, the word lines WL, and the upper select line USL are simultaneously formed, the tunnel insulating layer 25, the charge trap layer 24A, and the first charge of the lower select transistor and the upper select transistor are formed. The blocking layer patterns 28 are used as the gate insulating layer.

5A through 5C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention, and show regions in which memory cells are stacked. Hereinafter, descriptions that overlap with the above description will be omitted.

As shown in FIG. 5A, first material layers 51 and second material layers 52 are alternately formed on a substrate (not shown) on which a desired lower structure is formed.

For example, the first material film 51 may be formed of a conductive film such as a polysilicon film, and the second material film 52 may be formed of an insulating film such as an oxide film. As another example, the first material film 51 may be formed of a conductive film such as a doped polysilicon film or a doped amorphous silicon film, and the second material film 52 may be an undoped polysilicon film or an undoped amorphous silicon film. It may be formed as a sacrificial film. As another example, the first material film 51 may be formed of a sacrificial film such as a nitride film, and the second material film 52 may be formed of an insulating film such as an oxide film.

In the second embodiment, a case in which the first material film 51 is formed of a sacrificial film such as a nitride film and the second material film 52 is formed of an insulating film such as an oxide film will be described.

Subsequently, the first material layers 51 and the second material layers 52 are etched to form channel holes H, and then the first material layers 51 exposed on the inner surfaces of the channel holes H are formed. Is oxidized to some thickness. As a result, the first charge blocking layer patterns 53 are formed.

In this case, after the sacrificial layer (not shown) is formed on the inner walls of the channel holes H, the first material layers 51 may be partially oxidized. Here, the sacrificial film may be formed of a nitride film, a silicon film, or the like, and may be formed to a thickness of 5 to 50 microseconds. In this case, the first material layers 51 and the sacrificial layers are simultaneously oxidized by an oxidation process, and a charge blocking layer formed by oxidizing the sacrificial layers is further formed on the inner walls of the channel holes H.

Subsequently, after the charge trap film 54 is formed on the inner wall of the channel holes H, the tunnel insulating film 55 is formed on the charge trap film 54. The tunnel insulation layer 55 may be formed using a deposition process, or may be formed by partially oxidizing the charge trap layer 54.

Subsequently, after the vertical channel film 56 is formed on the tunnel insulating film 55, an insulating film 57 such as a fluid oxide film is buried in the open center region of the vertical channel film 56.

As shown in FIG. 5B, the first material layers 51 and the second material layers 52 are etched to form slits S between the vertical channel layers 56. Subsequently, the first material layers 51 exposed to the inner wall of the slits S are selectively removed to form open regions. In this case, the first charge blocking layer patterns 53 remain without being removed.

For example, when the first material layers 51 are formed of a nitride film and the first charge blocking layer patterns 53 are formed of an oxide film, the first material layers 51 may be selectively removed using phosphoric acid. Can be. In this case, the first charge blocking layer patterns 53 are left without being etched. The first charge blocking layer patterns 53 formed by the oxidation method have a lower etching rate than the charge blocking layers formed by the deposition method. Therefore, it is possible to prevent the first charge blocking layer patterns 53 from being damaged in the process of removing the first material layers 51.

As shown in FIG. 5C, the second charge blocking layer 58 is formed along the inner surface of the open regions. In this case, the first charge blocking layer patterns 53 may be removed before the second charge blocking layer 58 is formed.

Subsequently, after the conductive film 59 is filled in the open regions in which the second charge blocking film 58 is formed, the insulating film 60 is embedded in the slits S. As a result, memory cells stacked along the vertical channel layers 56 are formed.

Meanwhile, according to the second embodiment, the first material film 51 may be formed of a conductive film such as a polysilicon film, and the second material film 52 may be formed of an insulating film such as an oxide film. In this case, the first material blocking layer 51 formed of the conductive layer is partially oxidized to form first charge blocking layer patterns 53. In addition, after the slits S are formed, the first material layers 51 exposed by the slits S are silicided without being removed. Subsequently, by filling the insulating film 59 in the slits S, the memory cell manufacturing process is completed.

Further, according to the second embodiment, the first material film 51 may be formed of a conductive film such as a doped polysilicon film, and the second material film 52 may be formed of a sacrificial film such as an undoped polysilicon film. It is possible. In this case, the first material blocking layer 51 formed of the conductive layer is partially oxidized to form first charge blocking layer patterns 53. In addition, after the slits S are formed, the second material layers 52 are removed instead of the first material layers 51. Subsequently, the insulating cell 59 is filled in the regions and the slits S from which the second material layers 52 are removed, thereby completing the memory cell manufacturing process.

Here, in the process of partially oxidizing the first material layer 51, the second material layers 52 may also be partially oxidized. The oxidized portion may be removed together or remain when the second material layers 52 are removed. Even if the oxidized portion remains, it acts as an interlayer insulating film and thus does not affect the device characteristics.

6 is a cross-sectional view of a three-dimensional nonvolatile memory device to which memory cells described with reference to the second embodiment of the present invention are applied. Hereinafter, duplicated description will be omitted.

As shown in FIG. 6, the 3D nonvolatile memory device to which the second embodiment of the present invention is applied includes a pipe gate film PG and a pipe channel film P_CH formed in the pipe gate PG, and includes a pipe channel film ( And a tunnel insulating film 55, a charge trap film 54, and a gate insulating film 61 surrounding P_CH.

Here, the gate insulating layer 61 is formed together in the process of forming the first charge blocking layer patterns 53. For example, after the channel holes H are formed, the sacrificial layer embedded in the trench is removed. Subsequently, the thickness of the first material layers 51 exposed to the inner surfaces of the channel holes H is partially oxidized using an oxidation process, and at the same time, the thickness of the conductive film for the pipe gate exposed to the inner surfaces of the trench is partially oxidized. As a result, the first charge blocking layer patterns 53 and the gate insulating layer 61 may be simultaneously formed.

For example, when the first material film 51 is formed of a nitride film and the pipe gate conductive film is formed of a polysilicon film, the pipe gate conductive film is oxidized about 1.5 times faster than the first material film 51. . Accordingly, the gate insulating layer 61 may be formed to have a thickness D1 <D2 greater than the first charge blocking layer patterns 53, thereby improving characteristics of the pipe transistor.

7 is a cross-sectional view of a three-dimensional nonvolatile memory device to which memory cells described with reference to the second embodiment of the present invention are applied. Hereinafter, duplicated description will be omitted.

As shown in FIG. 7, in the three-dimensional nonvolatile memory device to which the second embodiment of the present invention is applied, at least one lower selection line LSL, which is sequentially stacked on the substrate 70 having the source region S, is sequentially stacked. , Word lines WL and at least one layer of upper select line USL.

The lower select transistor and the upper select transistor may gate the tunnel insulation layer 55, the charge trap layer 54, the first charge blocking layer patterns 53, and the second charge blocking layer 58 surrounding the vertical channel layer 56. Used as an insulating film.

8A to 8C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention, and show regions in which memory cells are stacked. Hereinafter, descriptions that overlap with the above description will be omitted.

As shown in FIG. 8A, first material layers 81 and second material layers 82 are alternately formed on a substrate (not shown) on which a desired lower structure is formed. In the third embodiment, a case in which the first material film 81 is formed of a sacrificial film such as a nitride film and the second material film 82 is formed of an insulating film such as an oxide film will be described.

Subsequently, after the first material layers 81 and the second material layers 82 are etched to form channel holes, the first material layers 81 exposed on the inner surfaces of the channel holes are partially oxidized. As a result, the first charge blocking layer patterns 83 are formed.

Subsequently, a charge trap film 84, a tunnel insulating film 85, and a vertical channel film 86 are formed on inner walls of the channel holes. When the center region of the vertical channel film 86 is opened, an insulating film 87 such as a fluid oxide film is buried in the open center region.

As shown in FIG. 8B, the first material layers 81 and the second material layers 82 are etched to form slits S between the channel holes. Subsequently, the first material layers 81 exposed to the inner wall of the slits S are selectively removed to form an open region.

Next, the second charge blocking layer patterns 88 are formed by partially oxidizing a surface of the charge trap layer 84 in contact with the first charge blocking layer patterns 83 using an oxidation process. As a result, the charge trap film 84A has a thinner first region than the second region. In addition, the second charge blocking layer patterns 83 are formed to surround the first region of the charge trap layer 84A.

As shown in FIG. 8C, after the conductive film 89 is embedded in the open regions, the insulating film 90 is embedded in the slits S. Referring to FIG. In this case, before filling the conductive layer 89, a third charge blocking layer (not shown) may be further formed along inner surfaces of the open regions. As a result, memory cells stacked along the vertical channel layers 86 are formed.

9 is a cross-sectional view of a three-dimensional nonvolatile memory device to which memory cells described with reference to the third embodiment of the present invention are applied. Hereinafter, duplicated description will be omitted.

As shown in FIG. 9, the three-dimensional nonvolatile memory device to which the third embodiment of the present invention is applied includes a pipe gate PG and a pipe channel film P_CH formed in the pipe gate PG, and includes a pipe channel film ( And a tunnel insulating film 85, a charge trap film 84A, and a gate insulating film 91 surrounding P_CH.

10 is a cross-sectional view of a three-dimensional nonvolatile memory device to which memory cells described with reference to the third embodiment of the present invention are applied. Hereinafter, duplicated description will be omitted.

As shown in FIG. 10, in the three-dimensional nonvolatile memory device to which the third embodiment of the present invention is applied, at least one lower selection line LSL, which is sequentially stacked on the substrate 70 having the source region S, is sequentially stacked. , Word lines WL and at least one layer of upper select line USL.

The lower select transistor and the upper select transistor may include the tunnel insulating layer 85, the charge trap layer 84A, the first charge blocking layer patterns 83, and the second charge blocking layer patterns 88 surrounding the vertical channel layer 86. Is used as the gate insulating film.

11 is a graph illustrating erase characteristics of a semiconductor device to which at least one of the first to third embodiments of the present invention is applied. In particular, as a graph showing a change in the threshold voltage according to the erase voltage, the x axis represents the level of the erase voltage applied during the erase operation, and the y axis represents the threshold voltage of the memory cell.

Here, A1 to A5 represent the erasing characteristics of the semiconductor device according to the prior art, and represent the erasing state of the memory cell when the charge blocking film is formed by the deposition method. B1 to B5 show the erased state of the memory cell when the charge blocking film is formed by the oxidation method. In addition, V _E1 , V _E2 , V _E3 , V _E4 , and V _E5 represent erase voltages (V _E1 <V _E2 <V _E3 <V _E4 <V _E5 ).

The memory cells are increased in threshold voltage by a program operation. In addition, when the erase voltage is applied to the source line or the source region during the erase operation, the threshold voltages of the memory cells in the program state P are lowered to be the erase states A1 to A5 and B1 to B5.

At this time, the threshold voltage fluctuation range of the memory cells is affected by the film quality of the charge blocking film and the interface characteristics of the charge trap film and the charge blocking film. That is, as the film quality of the charge blocking film and the interface characteristics of the charge trap film and the charge blocking film are improved, the variation range of the threshold voltage increases during the erase operation, thereby improving the erase characteristic of the memory device.

Referring to the graph, it can be seen that when the charge blocking film is formed by the oxidation method, the threshold voltage of the memory cell is significantly reduced during the erase operation as compared with forming the charge blocking film by the deposition method. In addition, it can be seen that as the level of the erase voltage increases, the variation range of the threshold voltage increases. Therefore, when the semiconductor device is manufactured by applying at least one of the first to third embodiments of the present invention, it can be seen that the operating characteristics of the memory device are improved.

12 is a configuration diagram illustrating a configuration of a memory system according to an embodiment of the present invention.

As shown in FIG. 12, the memory system 100 according to an embodiment of the present invention includes a nonvolatile memory device 120 and a memory controller 110.

The nonvolatile memory device 120 is configured to include the memory cells described above with reference to the first to third embodiments. In addition, the nonvolatile memory device 120 may be a multi-chip package composed of a plurality of flash memory chips.

The memory controller 110 is configured to control the non-volatile memory element 120 and may include an SRAM 111, a CPU 112, a host interface 113, an ECC 114, a memory interface 115 . The SRAM 111 is used as an operation memory of the CPU 112 and the CPU 112 performs all control operations for data exchange of the memory controller 110 and the host interface 113 is connected to the memory system 100 And a host computer. In addition, the ECC 114 detects and corrects errors contained in the data read from the non-volatile memory element 120, and the memory interface 115 performs interfacing with the non-volatile memory element 120. In addition, the memory controller 110 may further include an RCM that stores code data for interfacing with the host.

As described above, the memory system 100 having the configuration may be a memory card or a solid state disk (SSD) in which the nonvolatile memory element 120 and the controller 110 are combined. For example, if the memory system 100 is an SSD, the memory controller 110 is external (eg, via one of various interface protocols, such as USB, MMC, PCI-E, SATA, PATA, SCSI, ESDI, IDE, etc.). For example, it can communicate with the host).

13 is a block diagram illustrating a configuration of a computing system according to an embodiment of the present invention.

As shown in FIG. 13, the computing system 200 according to an embodiment of the present invention includes a CPU 220, a RAM 230, a user interface 240, and a modem 250 electrically connected to a system bus 260. ), May include a memory system 210. In addition, when the computing system 200 is a mobile device, a battery for supplying an operating voltage to the computing system 200 may be further included, and an application chipset, a camera image processor (CIS), and a mobile DRAM may be further included. .

As described above with reference to FIG. 12, the memory system 210 may include a nonvolatile memory 212 and a memory controller 211.

It is to be noted that the technical spirit of the present invention has been specifically described in accordance with the above-described preferred embodiments, but it is to be understood that the above-described embodiments are intended to be illustrative and not restrictive. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

21: sacrificial film 22: interlayer insulating film
23: buffer film 24: charge trap film
25: tunnel insulation film 26: channel film
27: insulating film 28: first charge blocking film patterns
29: second charge blocking film 30: conductive film
31: insulating film

Claims (23)

Word lines and interlayer dielectric layers alternately stacked on a substrate;
Vertical channel layers protruding from the substrate and penetrating the word lines and the interlayer insulating layers;
A tunnel insulating layer surrounding the vertical channel layers;
A charge trap film surrounding the tunnel insulating film, wherein a first region between the tunnel insulating film and the word lines has a thickness thinner than a second region between the tunnel insulating film and the interlayer insulating films; And
First charge blocking layer patterns surrounding the first region of the charge trap layer
&Lt; / RTI &gt;
The method of claim 1,
The charge trap layer has an uneven surface on the outer surface
A semiconductor device.
The method of claim 1,
A second charge blocking layer formed between the first charge blocking layer patterns and the word lines and between the word lines and the interlayer insulating layers
Further comprising:
The method of claim 1,
Buffer layer patterns surrounding the second region of the charge trap layer
Further comprising:
The method of claim 1,
The tunnel insulating layer is formed by partially oxidizing the charge trap layer.
A semiconductor device.
The method of claim 1,
A pipe gate formed on the substrate; And
A pipe channel film formed in the pipe gate and connected to the vertical channel films and wrapped by the tunnel insulating film and the charge trap film.
Further comprising:
The method according to claim 6,
Buffer layer patterns interposed between the charge trap layer and the interlayer insulating layers and between the charge trap layer and the pipe gate.
Further comprising:
The method according to claim 6,
A gate insulating film interposed between the charge trap film and the pipe gate
Further comprising:
The method of claim 1,
An upper select line of at least one layer formed on the word lines; And
A bottom select line of at least one layer formed below the word lines
Further comprising:
Alternately forming first material layers and second material layers;
Etching the first material layers and the second material layers to form channel holes;
Forming vertical channel layers, a tunnel insulating layer surrounding the vertical channel layers, and a charge trap layer surrounding the tunnel insulating layer in the channel holes;
Etching the first material layers and the second material layers to form a slit between adjacent channel holes;
Removing the first material films exposed in the slit;
Forming a first charge blocking layer pattern by partially oxidizing the charge trap layer exposed to a region where the first material layers are removed; And
Forming a conductive film in a region where the first material films are removed
&Lt; / RTI &gt;
The method of claim 10,
Forming a second charge blocking layer along inner surfaces of regions from which the first material layers are removed;
A semiconductor device manufacturing method further comprising.
The method of claim 10,
Before forming the first material layers and the second material layers alternately, forming a conductive film for a pipe gate;
Etching the pipe gate conductive film to form a trench at a position connected to the channel holes;
Filling a sacrificial layer in the trench; And
Removing the sacrificial layer exposed on the bottom surfaces of the channel holes after forming the channel holes.
A semiconductor device manufacturing method further comprising.
Alternately forming first material layers and second material layers;
Etching the first material layers and the second material layers to form channel holes;
Forming first charge blocking layer patterns by partially oxidizing the first material layers exposed to inner surfaces of the channel holes; And
Forming vertical channel layers, a tunnel insulating layer surrounding the vertical channel layers, and a charge trap layer surrounding the tunnel insulating layer in the channel holes.
&Lt; / RTI &gt;
The method of claim 13,
Etching the first material layers and the second material layers to form a slit between adjacent channel holes;
Removing the first material films exposed in the slit; And
Forming a conductive film in a region where the first material films are removed
A semiconductor device manufacturing method further comprising.
15. The method of claim 14,
Forming a second charge blocking layer along inner surfaces of regions from which the first material layers are removed;
A semiconductor device manufacturing method further comprising.
15. The method of claim 14,
After removing the first material layers, forming a second charge blocking layer pattern by partially oxidizing the charge trap layer in contact with the first charge blocking layer patterns.
A semiconductor device manufacturing method further comprising.
The method of claim 13,
After forming the channel holes, forming a sacrificial layer on the inner wall of the channel holes
A semiconductor device manufacturing method further comprising.
18. The method of claim 17,
The sacrificial layer is oxidized together when the first material layers are partially oxidized.
A method of manufacturing a semiconductor device.
The method of claim 13,
Before forming the first material layers and the second material layers alternately, forming a conductive film for a pipe gate;
Etching the pipe gate conductive film to form a trench at a position connected to the channel holes;
Filling a sacrificial layer in the trench; And
Removing the sacrificial layer exposed on the bottom surfaces of the channel holes after forming the channel holes.
A semiconductor device manufacturing method further comprising.
20. The method of claim 19,
The forming of the first charge blocking layer patterns may include:
Forming the first charge blocking layer patterns and the gate insulating layer by partially oxidizing the first material layers exposed on the inner surfaces of the channel holes and the conductive film for the pipe gate exposed on the inner surface of the trench.
A method of manufacturing a semiconductor device.
14. The method according to claim 10 or 13,
Forming the vertical channel layers, the tunnel insulating layer, and the charge trap layer may include:
Forming the charge trap layer on inner walls of the channel holes;
Forming the tunnel insulating film on the charge trap film; And
Forming the vertical channel film on the tunnel insulating film;
A method of manufacturing a semiconductor device.
14. The method according to claim 10 or 13,
Forming the vertical channel layers, the tunnel insulating layer, and the charge trap layer may include:
Forming the charge trap layer on inner walls of the channel holes;
Partially oxidizing the charge trap film to form the tunnel insulating film; And
Forming the vertical channel film on the tunnel insulating film;
A method of manufacturing a semiconductor device.
14. The method according to claim 10 or 13,
Before forming the charge trap film, forming a buffer film along the inner surface of the channel holes
A semiconductor device manufacturing method further comprising.

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