KR20130083960A - Single-poly multi-time programmable memory - Google Patents

Abstract

PURPOSE: A single-poly multi-time programmable (MTP) memory is provided to supply the necessary voltage by a 7-step VPP charge pump and a 2-step charge pump circuit by an operation mode, thereby reducing the area corresponding to the extra charge pump. CONSTITUTION: A data input buffer and a data writing switch programs the program data of the data input in the designated MTP memory cell array (305). A word line driving circuit (304) supplies the voltage to the MTP memory cell array along an address. The MTP memory cell array is connected to a data input buffer, a data writing switch block, a word line driving circuit, a data reading switch, and a data-bus sensing ample block. A control logic circuit (306) is connected to the word line driving circuit, the data reading switch and data-bus sensing ample block. The control logic circuit generates a control signal by an operation mode. The reading data switch and the data-bus sensing ample (307) read the data of the MTP cell.

Description

Single-Poly Multi-Time Programmable Memory

The present invention relates to the MTP memory design, and in particular, to design a low-area memory, a word-line driver (simplified word-line driver) is designed. The V10V (= 10V) and V5V (= 5V) voltages required for both erase and program modes select the internal pumping node voltage of the seven-stage cross-coupled charge pump, eliminating the need for additional DC-DC converters. The present invention relates to a single-poly MTP memory including a circuit implemented by only one DC-DC converter.

Multi-Time Programmable Memory (MTP memory) is used for analog trimming and is used in many PMIC chips because of its simple process and cost effectiveness. PMIC (Power Management IC) is a chip that receives input power from information devices such as mobile phones, notebook PCs, TVs and monitors and converts it into stable and efficient power required by the system. Non-Volatile Memory cells (NVM cells) used in Power Management IC (PMIC) chips use single-poly EEPROM, double-poly EEPROM, flash, and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) cells. have

In general, NVM memory of several Kb or more in a PMIC chip uses a double-poly EEPROM, flash and SONOS cell with a bit cell size of several micrometers 2, and 5 to 8 extra mask layers are required for the BCD process. NVM memory of several Kb or less uses a MTP cell (Multi-Time Programmable Cell) having a single-poly EEPROM having a bit cell size of several tens of micrometers 2 or more, and mostly one or two mask layers are added. In addition, a low-area design is required for cost reduction, and an operating voltage range of 2.5V to 5.5V is required to cope with application devices such as notebook PCs, mobile phones, and monitors as shown in Table 1 with one multi-time programmable IP. A circuit design with a wide operating range voltage is required.

Multi-Time Programmable Cells (MTP Cells) used for MTP Memory (Multi-Time Programmable Memory) are single-poly EEPROMs as shown in FIG. N) It consists of a capacitor, a sense transistor, and a select transistor. 1 shows a circuit diagram of a multi-time programmable (MTP) cell. The operation of emitting electrons to the floating gate of FIG. 1 is an erase mode, and the operation of injecting electrons to the floating gate is a program mode. Deletion and programming of EEPROM cells is accomplished by FN-tunneling through tunnel oxide under the floating gate. In the write mode of the MTP (Multi-Time Programmable), the program mode should always be performed after the erase mode.

2 illustrates a bias voltage condition for each node according to an operation mode of a multi-time programmable (MTP) cell according to the present invention. In the erase mode, 0 V is applied to the word line WL and 15 V to the bit line BL of the selected cell to emit electrons in the floating gate node by FN-tunneling. In the program mode, 18.5 V is applied to the word line of the selected cell and 0 V is applied to the BL to inject electrons into the floating gate node by FN-tunneling. The source lines SL are all floating in the write mode and 0V in the read mode.

The selected word line WL has different voltages such as 0 V, VPP (= 18.5 V) and VRD (= 3.3 V) in erase mode, program mode and read mode, respectively. Use the method to provide it. On the other hand, unselected word lines use the method of outputting voltages of V10V (= 10V), V5V (= 5V), and 0V in erase mode, program mode, and read mode. . V10V and V5V are the voltages to prevent data disturb. V10V is the voltage to prevent the unselected cells from being erased. V5V is the voltage to prevent the unselected cells from being programmed. For the voltage.

As shown in FIG. 3, the threshold voltage of the deleted cell is 1.9 V or less, and the threshold voltage of the programmed cell is 5.0 V or more. In read mode, a 3.3V VRD voltage is applied to the word line. The erased cell outputs 0V to BL, while the programmed cell outputs VDD. The voltages required for a multi-time programmable IP design require VPP, V10V (= 10V), V5V (= 5V), VRD (= 3.3V), and VDD. VPP is 18.5V in program mode and 15V in erase mode.

Conventional EEPROM circuits share one row address decoder for every two word-line drivers, and the final address decoding in each word-line driver A circuit for address decoding is used. In this case, the area occupied by the CMOS logic circuit is large. In addition, a VPPL selection circuit for supplying a voltage lower than VPP using an internal pumping node voltage of a positive charge pump circuit generating a boosted voltage (VPP) voltage has been disclosed. In this case, the layout area occupied by the HW switching circuit for selecting two pumping node voltages is large.

The technical problem to be solved by the present invention is to design a word-line driver (Word-Line Driver) to simplify the decoding logic circuit to design a low- area multi-time programmable (MTP) IP in the MTP memory design, The required VPP, V10V, V5V and VRD voltages, depending on the mode, are supplied by a seven-stage VPP charge pump and a two-stage VRD charge pump circuit to reduce the area corresponding to extra charge pumps. To provide.

The single-poly MTP memory according to the present invention for achieving the above technical problem is a data input buffer and data write switch for programming the program data of the data input to the specified MTP memory (Multi-Time Programmable Memory) cell array, the data input buffer And a DC-DC converter connected to the data write switch and supplying a plurality of voltages, a word line driving circuit connected to the DC-DC converter and supplying a voltage to an MTP memory (Multi-Time Programmable Memory) cell array according to an address; A multi-time programmable memory (MTP) memory array coupled to the data input buffer and the data write switch block, the word line driver circuit and the data read switch and the data-bus sense amplifier block, the word line driver circuit and the data read switch; Connected to and operated by the data-bus detection amplifier block And a read data switch and a data-bus sense amplifier connected to the control logic circuit for generating a control signal and for reading data of a multi-time programmable (MTP) cell. In the DC converter, a plurality of voltages are implemented using only one VPP charge pump by using an internal pumping node voltage of a seven-stage VPP charge pump.

The single-poly MTP memory according to the present invention has designed a word-line driver that simplifies the decoding logic circuit to design a low area MTP (Multi-Time Programmable) IP. The VPP, V10V, V5V and VRD voltages can be supplied by a seven-stage VPP charge pump and a two-stage VRD charge pump circuit, thereby reducing the area corresponding to extra charge pumps.

1 is a circuit diagram of a multi-time programmable (MTP) cell according to the prior art.
2 illustrates a bias voltage condition for each node according to an operation mode of a multi-time programmable (MTP) cell according to the prior art.
3 is a threshold voltage of a cell that has been erased and programmed according to the prior art.
4 is a block diagram of an MTP memory (Multi-Time Programmable Memory) according to the present invention.
5 is a diagram illustrating a word-line driver circuit according to the present invention.
Figure 6 shows the output voltage of the switching power supply for each operation mode according to the present invention.
7 is a view showing a data-bus detection amplifier according to the present invention.
8 is a voltage of the DC-DC converter for each operation mode according to the present invention.
9 is a block diagram of a proposed DC-DC converter according to the present invention.
10 is a diagram illustrating a seven-stage VPP charge pump circuit diagram according to the present invention.
11 is a view showing a VRD precharging circuit of the precharging circuit of the DC-DC converter according to the present invention.
12 is a view showing a V10V switching power circuit according to the present invention.
FIG. 13 is a diagram illustrating an MTP memory (Multi-Time Programmable Memory) layout image according to the present invention. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

4 is a block diagram of an MTP memory (Multi-Time Programmable Memory) according to the present invention.

 MTP memory (Multi-Time Programmable Memory) is composed as follows. 32 rows x 8 columns of memory cell array 305, a word that selects one of 32 rows according to address A [4: 0] to supply voltage to the word line node A line driving circuit 304, a read data switch for reading data of a multi-time programmable cell, a data-bus sense amplifier 307, and a program for data input There is a data input buffer and a write data switch 303 for programming program data to a designated MTP cell (Multi-Time Programmable Cell), and generating a control signal according to an operation mode. There is a control logic circuit 306 to make.

Input control signals include data read, data erase, and program signals. Meanwhile, the DC-DC converter 302 supplies VPP, V10V, V5V, and VRD voltages. The V10V and V5V voltages required for both erase and program modes select the internal pumping node voltage of the seven-stage boosted voltage (VPP) charge pump, so they are implemented as a single VPP charge pump without additional charge pumps. The layout area can be reduced. One byte of 32 bytes is selected by five addresses A [4: 0], and data reading and writing are performed in byte units.

5 is a diagram illustrating a word line driver circuit according to the present invention.

The word line driver circuit includes a NAND gate 503 for receiving a drive input 1 and a drive input 2, a first inverter 504 for receiving an output of the NAND gate, a first terminal for receiving a reverse control signal 1, and a control signal 1. A first switch 501 including a second terminal receiving a second terminal, a third terminal receiving the output of the first inverter, and a fourth terminal connected to an input of the differential amplifier 505, a second receiving the reverse control signal 2; A second switch 502 including a first terminal, a second terminal receiving a control signal 2, a third terminal receiving the output of the NAND gate, and a fourth terminal connected to an input of the differential amplifier 505, a switching power supply A high " High " signal ROW_HW of which is connected to the differential amplifier 505 received from the first switch and the second switch, and a high " High " signal " ROW_HW " 1 terminal, a second stage receiving the output of the differential amplifier 505 And the second; and a second inverter 506, a third terminal connected to a low "Low" signal (ROW_LW) of the switching power supply.

The row decoding logic of the word line driver circuit designed in the present invention decodes the predecoded input drive input 1 and drive input 2. The drive input 1 is a pre-decoded input of A4 and A3 of five addresses A [4: 0], and the drive input 2 is a pre-decoded input of A2, A1 and A0 of five addresses A [4: 0].

Figure 6 shows the output voltage of the switching power supply for each operation mode according to the present invention.

Since the ROW_HV voltage supplies voltages of 10 V, 18.5 V, and 3.3 V in erase mode, program mode, and read mode, respectively, the VDD-to-ROW_HV voltage level as shown in FIG. 5. A converter circuit is needed. The voltage level converter circuit is designed using a high voltage transistor because a high voltage of up to 18.5V is applied.

7 is a view showing a data-bus detection amplifier according to the present invention.

MP1, a PMOS transistor, enters the read mode and raises the data busline to VDD by the DB_LOADb (Data Bus LOAD bar) signal. When the word line is activated, the data busline voltage connected to a cell programmed with a logic '1' whose threshold voltage of the MTP cell (Multi-Time Programmable Cell) is 5.0V or higher is maintained at VDD, while the MTP Cell (Multi-Time Programmable cell) is A cell programmed with a logic '0' whose threshold voltage is less than or equal to 1.9V discharges the data busline to 0V by the turned on MTP cell (Multi-Time Programmable Cell).

When the BL data is sufficiently raised on the data bus line, the clock inverter of FIG. 7 senses a voltage on the data bus and outputs the voltage to the output data port.

The output data buffer detects and outputs read data of the data bus during a section in which the SAENb (Sense Amplifier Enable bar) signal is 'low' and outputs the read signal in the 'high' section. Traps the data detected by The high impedance PMOS load transistor MP1, when approaching a cell programmed with '1', prevents the BL from dropping to 'low' due to the turned off leakage current of an unselected cell connected to the BL. To avoid this, the BL and data buslines must be held sufficiently high.

8 is a voltage of the DC-DC converter for each operation mode according to the present invention. The voltages used in the MTP memory design are VPP, V10V, V5V and VRD as the output voltage of the DC-DC converter, and VDD and VREG as the input voltage of the DC-DC converter. Therefore, DC-DC converter circuits are generally used to make voltages of VPP, V10V, V5V, and VRD.

9 is a block diagram of a proposed DC-DC converter according to the present invention.

The DC-DC converter 900 receives a reference voltage generator 901, a VPP level detector 902 receiving VREF and VPP generated from the reference voltage generator 901, and a VPP ring receiving an output of the VPP level detector 902. An oscillator 903, a VPP control logic 904 that receives the output of the VPP ring oscillator 903, a VPP charge pump 905 that receives the output of the VPP control logic 904, and the VPP charge pump 905. V10V selection circuit 906 for receiving V10V_ERS and V10V_PGM among the outputs of the output, the VREF_VRD generated from the reference voltage generator and the VRD level detector receiving the VRD of the VRD charge pump, the VRD ring oscillator receiving the output of the VRD level detector, VRD control logic receiving the output of the VRD ring oscillator, VRD charge pump receiving the output of the VRD control logic, each capacitor connected to one or more output lines of any one of VPP, VRD, V10V and V5V It is characterized by

In the present invention, a DC-DC converter circuit for supplying VPP, V10V, V5V, and VRD voltages using only the DCPP DC pump and the VRD charge pump circuit is proposed. The DC-DC converter should be supplied with the VPP, V10V and V5V voltages necessary for the write mode of the present invention.

In DC-DC converters, the VRD charge pump uses VREG as the input voltage and supplies 3.3V of amplified voltage by a two-stage cross-coupled charge pump. A VRD voltage of 3.3V is required to apply to the selected wordline driver in read mode.

The VPP charge pump circuit of the present invention uses a seven stage VPP charge pump.

10 is a diagram illustrating a seven-step VPP charge pump circuit diagram 1000 according to the present invention.

The VPP charge pump circuit 1000 may include a first charge pump 1001 receiving the output of the VPP control logic, a second charge pump 1002 connected to an output of the first charge pump 1001, and the second charge pump 1002. A third charge pump 1003 connected to the output of the third charge pump, a fourth charge pump 1004 connected to the output of the third charge pump 1003, and a fifth charge pump connected to the output of the fourth charge pump 1004. 1005), a sixth charge pump 1006 connected to the output of the fifth charge pump 1005, a seventh charge pump 1007 connected to the output of the sixth charge pump 1006, and the seven respective charge pumps Each of the other seven VRD precharging circuits 1008 connected to an output terminal of the first charge pump 1001, the second charge pump 1002 and the VRD precharging circuit 1008. Outputs V5V and V10 in a line to which the third charge pump 1003, the fourth charge pump 1004, and the VRD precharging circuit 1008 are connected. Outputs V_PGM, outputs V10V_ERS on the line to which the fourth charge pump 1004, the fifth charge pump 1005 and the VRD precharge circuit 1008 are connected, and the seventh charge pump and the VRD precharge circuit 1008. ) Outputs the VPP at the line to which it is connected.

Among the voltages output from the DC-DC converter, VPP is supplied by a seven stage cross coupled charge pump. V10V and V5V were implemented by selecting the internal pumping node voltage of the seven-stage cross-coupled charge pump.

First, V5V uses the output voltage of the first pumping node of the seven-stage cross-coupled charge pump circuit, and V10V is switched by a V10V power switching circuit that selects the V10V_ERS voltage and the V10V_PGM voltage according to the write mode.

11 is a view showing a VRD precharging circuit of the precharging circuit of the DC-DC converter according to the present invention.

FIG. 11 shows a circuit for precharging the output voltage node voltage and the V10V voltage as the VRD voltage, which are the output voltages of the pumping stages of the VPP charge pump in the standby state.

The VRD precharging includes a first switch 1101 having a first terminal connected to a VRD, a second terminal and a fourth terminal connected to an output voltage, a first terminal and a fourth terminal connected to an output voltage, and a second terminal connected to a third terminal. A second switch 1102 connected to a first terminal of the switch 1103, a first terminal connected to the second terminal of the second switch 1102, and a second terminal and a fourth terminal connected to ground The third terminal of the third switch 1103, the second switch 1102, and the third switch 1103 is connected to VPP_ONb, and the third terminal of the first switch 1101 is the second switch 1102. ) And the third switch 1103 is input from the connected line.

12 is a view showing a V10V switching power circuit according to the present invention.

V10V_PGM with V10V_PGM and V10V_ERS voltage of VPP charge pump, V10V_PGM through turn-on MP0 in program mode and V10V_ERS voltage through turn-on MP1 in erase mode. A power switching circuit was used. VRD is the voltage that must be supplied in read mode.

The V10V selection circuit includes a differential amplifier 1207 that receives a PGMD signal, an inverter 1208 that receives an output of a differential amplifier 1207, a first terminal of V10V_PGM, a second terminal of V10V, and a third terminal of an output of the inverter. A first switch 1201 connected to the second terminal of the third switch, a first terminal connected to the output of the differential amplifier, a third terminal connected to the output of the differential amplifier, and a third terminal connected to the output of the differential amplifier. Is a second switch 1202 connected to the second terminal of the fifth switch 1205, the first terminal is connected to the fourth terminal of the first switch 1201, V10V_PGM, the second terminal and the fourth terminal, A third switch 1203 having three terminals connected to V10V, a first terminal connected to a fourth terminal of the first switch 1201, a first terminal V10V, a second terminal and a fourth terminal, and a third terminal connected to a V10V_PGM 4 switch 1204, the first terminal is V10V, the second terminal and the fourth terminal is connected to the fourth terminal of the second switch 1202, the third terminal is V10V_PG The fifth switch 1205 connected with M, the first terminal is V10V_PGM, the second terminal and the fourth terminal is connected to the fourth terminal of the second switch 1202, the third switch is connected to V10V 1206) and a capacitor coupled to V10V.

FIG. 13 is a diagram illustrating an MTP memory (Multi-Time Programmable Memory) layout image according to the present invention.

While the present invention has been described in connection with what is presently considered to be the most practical and preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the scope of the present invention.

302: DC-DC converter
303: write data switch
304: Word-line driver
305: memory cell array
306: Control Logic
307: Read Data Switch and Data-Bus Sense Amplifier

Claims (7)

A data input buffer and a data write switch for programming the program data of the data input into a designated multi-time programmable memory cell array;
A DC-DC converter connected to the data input buffer and the data write switch and supplying a plurality of voltages;
A word line driver circuit connected to the DC-DC converter and supplying a voltage to a multi-time programmable memory (MTP) cell array according to an address;
A multi-time programmable memory (MTP) cell array coupled to the data input buffer and data write switch block, the word line driver circuit and the data read switch and data-bus sense amplifier block;
A control logic circuit connected to the word line driver circuit, a data read switch, and a data-bus sense amplifier block to generate a control signal according to an operation mode; And
The read data switch and a data-bus sense amplifier connected to the control logic circuit to read data of a multi-time programmable (MTP) cell; Lt; / RTI >
In the DC-DC converter, a plurality of output voltages are implemented as a single charge pump using only the internal pumping node voltage of the 7-step charge pump. The DC-DC converter of claim 1, wherein
A reference voltage generator;
A level detector receiving a first signal generated by a reference voltage generator and a first output voltage of the first charge pump;
A first ring oscillator receiving an output of the first level detector;
First control logic to receive an output of the first ring oscillator;
A first charge pump configured to receive an output of the first control logic and output the first output voltage and a third output voltage;
A first selection circuit receiving the second signal and the third signal of the first charge pump and outputting a second output voltage;
A second level detector configured to receive a fourth signal generated by the reference voltage generator and a fourth output voltage of the second charge pump;
A second ring oscillator receiving an output of the second level sensor;
Second control logic to receive an output of the second ring oscillator;
A second charge pump configured to receive an output of the second control logic;
And a single capacitor connected to one or more output lines of the first output voltage, the second output voltage, the third output voltage, and the fourth output voltage. The method of claim 2, wherein the first charge pump is
A first charge pump receiving an output of the first control logic;
A second charge pump connected to the output of the first charge pump;
A third charge pump connected to the output of the second charge pump;
A fourth charge pump connected to the output of the third charge pump;
A fifth charge pump connected to the output of the fourth charge pump;
A sixth charge pump connected to the output of the fifth charge pump;
A seventh charge pump connected to the output of the sixth charge pump; And
Each of the other seven precharging circuits is connected to an output of each of the seven charge pumps,
Outputting the third output voltage from a line to which the first charge pump, the second charge pump and the precharge circuit are connected;
Outputting the second signal from a line to which the third charge pump, the fourth charge pump and the precharge circuit are connected;
Outputting the third signal from a line to which the fourth charge pump, the fifth charge pump, and the precharge circuit are connected;
Single-poly MTP memory, characterized in that for outputting a first output voltage from the line connected to the seventh charge pump and precharging circuit 4. The precharging circuit of claim 3, wherein the precharging circuit
A first switch having a first terminal connected with a fourth output voltage of the DC-DC converter as a power source, and a second terminal and a fourth terminal connected with an output voltage;
A second switch having a first terminal and a fourth terminal connected to the output voltage and a second terminal connected to the first terminal of the third switch;
A third switch having a first terminal connected to the second terminal of the second switch and a second terminal and a fourth terminal connected to ground;
The third terminal of the second switch and the third switch is connected to a control signal,
Single-poly MTF memory, characterized in that the third terminal of the first switch is input from the line connected to the second switch and the third switch 3. The circuit of claim 2, wherein the first selection circuit is
A differential amplifier receiving a program data signal;
An inverter receiving the output of the differential amplifier;
The first terminal is connected to the third signal of the DC-DC converter, the second terminal is connected to the second output voltage of the DC-DC converter, the third terminal is connected to the output of the inverter, and the fourth terminal is connected to the second signal of the third switch. A first switch connected to the terminal;
The first terminal is connected to the second output voltage of the DC-DC converter, the second terminal is connected to the third signal of the DC-DC converter, the third terminal is connected to the output of the differential amplifier, and the fourth terminal is connected to the fifth switch of the fifth switch. A second switch connected to two terminals;
A first terminal connected to a third signal of the DC-DC converter, a second terminal and a fourth terminal to a fourth terminal of the first switch, and a third terminal connected to a second output voltage of the DC-DC converter. 3 switch;
The first terminal is connected to the second output voltage of the DC-DC converter, the second terminal and the fourth terminal is connected to the fourth terminal of the first switch, the third terminal is connected to the third signal of the DC-DC converter A fourth switch;
The first terminal is connected to the second output voltage of the DC-DC converter, the second terminal and the fourth terminal is connected to the fourth terminal of the second switch, and the third terminal is connected to the second signal of the DC-DC converter. A fifth switch;
A first terminal connected to a second signal of the DC-DC converter, a second terminal and a fourth terminal to a fourth terminal of the second switch, and a third terminal connected to a second output voltage of the DC-DC converter. 6 switch; And
And a capacitor connected to the second output voltage of the DC-DC converter. The word line driver circuit of claim 1, wherein the word line driver circuit comprises:
A NAND gate receiving the driving input 1 and the driving input 2;
A first inverter receiving an output of the NAND gate;
A first switch including a first terminal receiving the reverse control signal 1, a second terminal receiving the control signal 1, a third terminal receiving the output of the first inverter, and a fourth terminal connected to an input of the differential amplifier;
A second switch including a first terminal receiving the reverse control signal 2, a second terminal receiving the control signal 2, a third terminal receiving the output of the NAND gate, and a fourth terminal connected to an input of the differential amplifier;
The differential amplifier using a high " High " signal of a switching power supply as a power source and received from the first switch and the second switch;
A second terminal including a first terminal connected to a high "High" signal of the switching power supply, a second terminal receiving an output of the differential amplifier, and a third terminal connected to a low "Low" signal of the switching power supply Single-poly MTP memory comprising an inverter 7. The single-poly MTP memory according to claim 6, wherein a user can arbitrarily determine a high " High " signal and a low " Low " signal of the switching power supply.

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