KR20130065256A - Method for fabricating array substrate for fringe field switching mode liquid crystal display device - Google Patents

Abstract

PURPOSE: A method for manufacturing array substrates for FFS mode liquid crystal display devices implements FFS mode liquid crystal display device manufacturing with four-time mask processes by using one mask to form a gate wiring and pixel electrode and by using one mask to form an active layer, source electrode and drain electrode. CONSTITUTION: A first photosensitive layer pattern is used as a etching mask to form a gate line and pixel electrode, etching exposed parts of a first conductive metal layer pattern, a first transparent conductive material layer pattern , a second conductive metal layer pattern (105b), and a second transparent conductive material layer pattern (103b). After removing the first photosensitive pattern, a data line is formed on a substrate (101) along with a gate insulating layer, and active layer, source electrode, and drain electrode. [Reference numerals] (AA) Secondary etching

Description

Manufacturing method of array board for FPS type liquid crystal display device {METHOD FOR FABRICATING ARRAY SUBSTRATE FOR FRINGE FIELD SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing an array substrate for a FFS (Fringe Field Switching) type liquid crystal display device.

Generally, the driving principle of a liquid crystal display device utilizes the optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal has a long structure, it has a directionality in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Therefore, when the molecular alignment direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular alignment direction of the liquid crystal by optical anisotropy, so that image information can be expressed.

Currently, an active matrix liquid crystal display (AM-LCD: liquid crystal display) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has excellent resolution and moving picture performance, It is attracting attention.

The liquid crystal display comprises a color filter substrate (i.e., an upper substrate) on which a common electrode is formed, an array substrate (i.e., a lower substrate) on which pixel electrodes are formed, and a liquid crystal filled between the upper substrate and the lower substrate. In the device, the liquid crystal is driven by an electric field in which the common electrode and the pixel electrode are arranged in an up-down direction, and the characteristics such as transmittance and aperture ratio are excellent.

However, liquid crystal driving by an electric field applied in an up-down direction has a disadvantage that the viewing angle characteristic is not excellent. Therefore, in order to overcome the above disadvantages, a newly proposed technique is a liquid crystal driving method using a transverse electric field. The liquid crystal driving method using the transverse electric field has an advantage of excellent viewing angle characteristics.

Although not shown in the drawings, such a transverse electric field type liquid crystal display device has a color filter substrate and a thin film transistor substrate facing each other, and a liquid crystal layer interposed between the color filter substrate and the thin film transistor substrate.

A thin film transistor, a common electrode, and a pixel electrode are formed for each of a plurality of pixels defined in the thin film transistor substrate. At this time, the common electrode and the pixel electrode are formed on the same substrate in parallel to each other.

In the color filter substrate, a black matrix is formed at a portion corresponding to a gate wiring formed on the thin film transistor substrate, a data wiring and a thin film transistor formed at a crossing point of the wiring, and a color filter is provided corresponding to the pixel .

Therefore, the liquid crystal layer is driven by the horizontal electric field between the common electrode and the pixel electrode.

In the transverse electric field liquid crystal display device having the above configuration, the common electrode and the pixel electrode are formed as transparent electrodes in order to secure luminance, but by design, the common electrode and the pixel are separated by a distance between the common electrode and the pixel electrode. Only a part of both ends of the electrode contribute to the improvement of brightness, and most areas result in light blocking.

Therefore, the proposed technique for maximizing such brightness improvement effect is FFS (Fringe Field Switching) technology. The FFS technique is characterized in that there is no color shift and a high contrast ratio can be obtained by precisely controlling the liquid crystal, so that it is possible to realize a high screen quality compared with a general transverse electric field technique.

The FFS type liquid crystal display according to the related art having the advantage of realizing such high screen quality will be described with reference to FIGS. 1 to 3 as follows.

1 is a plan view of a thin film transistor substrate for a conventional FPS type liquid crystal display device.

FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1, and is a schematic cross-sectional view of a thin film transistor substrate for a FPS type liquid crystal display device according to the prior art.

In the conventional FFF type liquid crystal display, as shown in FIGS. 1 and 2, a plurality of gate wirings 15 extending in one direction and spaced in parallel to each other are disposed on the transparent insulating substrate 11. A gate electrode 15a extending from the gate wiring 15; A gate insulating film 17 formed on an entire surface of the substrate including the gate electrode 13a; A plurality of data lines 23 formed on the gate insulating layer 17 and defining pixel regions in an area intersecting the gate lines 13; It is provided at the intersection of the gate wiring 15 and the data wiring 23, and is spaced apart from the active layer 19 and the ohmic contact layer 21 on the gate electrode 15a and the gate insulating layer 17. And a thin film transistor T composed of a source electrode 23a and a drain electrode 23b.

Here, a large area pixel electrode 13 is disposed on the substrate 11 of the pixel region where the gate wiring 15 and the data wiring 23 intersect, and a gate insulating film (above the pixel electrode 23). 17 and a plurality of rod-shaped transparent common electrodes 29a and 29b spaced apart from each other with the passivation film 25 interposed therebetween.

In addition, the pixel electrode 23 overlaps the plurality of common electrodes 29a and is directly connected to the drain electrode 23b.

In addition, the common electrode 29b is disposed to overlap the data line 23.

According to the above configuration, when a data signal is supplied to the pixel electrode 13 via the thin film transistor T, the common electrodes 29a supplied with the common voltage form a fringe field to form the fringe field. ) And the liquid crystal molecules arranged in the horizontal direction between the color filter substrate (not shown) are rotated by the dielectric anisotropy. The light transmittance of the liquid crystal molecules passing through the pixel region changes according to the degree of rotation, thereby realizing the gradation.

A method of manufacturing a fringe field (FFS) type liquid crystal display device according to the related art having the above configuration will be described in detail with reference to FIGS. 3A to 3F.

3A to 3F are cross-sectional views illustrating a manufacturing process of a conventional FPS type liquid crystal display device.

First, a transparent insulating substrate 11 defining a plurality of pixel regions including a switching region is prepared.

3A, an ITO layer (Indium Tin Oxide) (not shown), which is a first transparent conductive material, is deposited on the entire surface of the insulating substrate 11, and then the ITO layer is formed through a first mask process. By selectively patterning, a pixel electrode 13 having a large area is formed in the pixel region of the insulating substrate 11.

Subsequently, as illustrated in FIG. 3B, a first conductive metal layer (not shown) is deposited on the entire surface of the insulating substrate 11 including the pixel electrode 13 by a sputtering method, and then a photolithography technique is used. The first conductive metal layer (not shown) is selectively patterned through a two-mask process to form a gate wiring 15, a gate electrode 15a protruding from the gate wiring 15, and a gate pad electrically connected to an external driving circuit. (Not shown) is formed. In addition, when the gate line 15 is formed, a common line (not shown in FIG. 1, FIG. 1B) spaced apart by a predetermined distance is formed in parallel with the gate line 15.

Next, as shown in FIG. 3C, a gate insulating film 17 is deposited on the entire surface of the substrate including the gate wiring 15. Then, an amorphous silicon layer (a-Si: H) (not shown) and impurities are deposited thereon. The amorphous silicon layer (n + or p +) (not shown) is sequentially deposited, and then the amorphous silicon layer (n + or p +) (not shown) containing the impurities is subjected to a third mask process using photolithography technology. And the amorphous silicon layer (a-Si: H) (not shown) are selectively etched to form an active layer 19 and an ohmic contact layer 21 on the gate insulating layer 17 on the gate electrode 15a. ).

Subsequently, as illustrated in FIG. 3D, a second conductive metal layer (not shown) is deposited on the gate insulating layer 17 including the ohmic contact layer 21 and the active layer 19.

Next, the second conductive metal layer (not shown), the ohmic contact layer 21, and the active layer 19 are selectively removed through a fourth mask process using a photolithography technique. The data wirings 23 perpendicularly intersecting, the source electrodes 23a and the drain electrodes 23b extending from the data wirings 23 are formed. At this time, when the data line 23 is formed, a data pad (not shown) extending from the data line 23 and electrically connected to the external driving circuit part is also formed.

Subsequently, as illustrated in FIG. 3E, a passivation film 25 is deposited on the entire substrate including the pixel electrode 23.

Next, the passivation layer 25 and the gate insulating layer 17 are selectively etched through a fifth mask process using a photolithography technique to expose the drain electrode 23b and the pixel electrode 13. A contact hole 27a is formed. At this time, when the contact hole 27a is formed, a common wiring contact hole (not shown, see 27b of FIG. 1) that exposes the common wiring (not shown, see 15b of FIG. 1) is also formed.

Subsequently, as illustrated in FIG. 3F, a second transparent conductive material layer (not shown) is deposited on the passivation layer 25 including the pixel electrode contact hole 27a and then the photolithography technique is used. The second transparent conductive material layer (not shown) may be selectively etched through a six mask process, and the drain electrode may be formed through the pixel electrode contact hole 27a together with the plurality of common electrodes 29a and 29b spaced apart from each other. A pixel electrode connection pattern 29c which electrically connects 23b with the pixel electrode 130 is formed.

In this manner, the thin film transistor array substrate manufacturing process for the F-type liquid crystal display device according to the prior art is completed.

Subsequently, although not shown in the drawing, a FPS type liquid crystal display device is manufactured by performing a process of filling a liquid crystal layer between the array substrate and the color filter substrate together with a color filter substrate manufacturing process.

As described above, according to the array substrate of the conventional FPS type liquid crystal display device, since the mask process is performed six times in manufacturing the array substrate for the FPS type liquid crystal display device, the manufacturing process time is long. The cost of the mask process is increased. In particular, in the conventional FFS (French Field Switching) type liquid crystal display, the number of mask processes is increased by using a separate mask to form the active layer and the pixel electrode.

Accordingly, the present invention is to solve the problems of the prior art, to reduce the number of mask processes in the manufacturing of the FPS (FFS) type liquid crystal display device, to reduce the tail (tail) of the transparent conductive material layer (ITO) The present invention provides a method for manufacturing an array substrate for a liquid crystal display (FFS) type liquid crystal display device capable of improving the residue of a conductive metal layer.

According to an aspect of the present invention, there is provided a method for manufacturing an array substrate for a liquid crystal display (FFS) type liquid crystal display device, comprising: sequentially stacking a transparent conductive material layer and a conductive metal layer on a substrate; Forming a first photoresist pattern having a first thickness and a second photoresist pattern having a second thickness thinner than the first thickness on the conductive metal layer; Simultaneously etching the conductive metal layer and the transparent conductive material layer using the first and second photoresist pattern as an etch mask to form first and second conductive layer patterns and first and second transparent conductive material layer patterns; A portion of the first photoresist layer pattern and all of the second photoresist layer pattern are etched to form side surfaces of the first conductive metal layer pattern and the first transparent conductive material layer pattern under the first photoresist layer pattern, and upper and second upper surfaces of the second conductive metal layer pattern. Exposing side surfaces of the transparent conductive material layer pattern; Using the remaining first photoresist pattern as an etch mask, the exposed first conductive metal layer pattern and the first transparent conductive material layer pattern, the exposed second conductive metal layer pattern, and the second transparent conductive material layer pattern Forming a pixel electrode including the gate wiring including the first conductive metal layer pattern and the first transparent conductive material layer pattern and the second transparent conductive material layer pattern; The first photoresist layer pattern is removed, and the gate insulating layer and the active layer are formed on the substrate including the gate wiring and the pixel electrode, and the source and drain electrodes are formed on the active layer and spaced apart from each other. Forming a data line; Forming a passivation film on the entire surface of the substrate including the data line; Selectively etching the passivation layer and the gate insulating layer thereunder to form a pixel electrode contact hole exposing the drain electrode and the pixel electrode on the passivation layer; And on the passivation layer

And forming a pixel electrode connection pattern electrically connecting the pixel electrode and the drain electrode through the pixel electrode contact hole together with a plurality of common electrodes overlapping the pixel electrode.

In fabricating an array substrate for a FPS type liquid crystal display device according to the present invention, the gate wiring and the pixel electrode can be formed using one mask, and the active layer, the source electrode and the drain electrode can be formed using one mask. Thus, the manufacturing of the FPS type liquid crystal display device is possible by using the four mask process instead of the conventional six mask process, thereby reducing the mask cost, thereby shortening the manufacturing process time and reducing the manufacturing cost.

In addition, according to the FPS type liquid crystal display array substrate according to the present invention, the transparent conductive material layer and the conductive metal layer laminated structure to form a gate wiring and a pixel electrode using the photoresist pattern as an etch mask, the transparent conductive material layer In the case of primary wet etching using an etchant for etching the conductive metal layer and the conductive metal layer, the transparent conductive material layer is etched later than the conductive metal layer due to the difference in the etch rate of the transparent conductive material layer and the conductive metal layer. As a result, a side of the transparent conductive material layer, for example, an ITO tail is generated, but after the first wet etching, the photoresist pattern is selectively removed through an ashing process, and the remaining photoresist pattern is etched. As a mask, the exposed portions of the transparent conductive material layer and the conductive metal layer may be secondarily formed using the etching solution used in the first wet etching process. By wet etching at the time, it is possible to etch the protrusions in bulk from the side and a transparent conductive material layer of the exposed electrically conductive metal layer, it is possible to reduce the ITO tail (tail).

 In addition, according to the array substrate for the FSF type liquid crystal display device according to the present invention, the transparent conductive material layer and the conductive metal layer are first wet-etched at the same time to form the gate wiring and the pixel electrode at the same time. By simultaneously wet etching the exposed portion of the metal layer with the etching solution used during the first wet etching, the conductive metal layer, for example, copper (Cu) residue can be improved.

1 is a plan view of a thin film transistor substrate for a conventional FPS type liquid crystal display device.
FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1, and is a schematic cross-sectional view of a thin film transistor substrate for a FPS type liquid crystal display device according to the prior art.
3A to 3F are cross-sectional views illustrating a manufacturing process of a conventional FPS type liquid crystal display device.
4 is a plan view of a thin film transistor substrate for a FPS type liquid crystal display device according to the present invention.
FIG. 5 is a cross-sectional view taken along the line VV of FIG. 4 and is a schematic cross-sectional view of a TFT substrate for a liquid crystal display device according to the present invention.
6A to 6R are cross-sectional views illustrating a manufacturing process of a FPS type liquid crystal display device according to the present invention.
7A to 7F are cross-sectional views schematically illustrating a process of removing an ITO tail when forming a gate wiring and a pixel electrode in the method of manufacturing a FPS type liquid crystal display device according to the present invention.

Hereinafter, an array substrate for a FPS type liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a plan view of a thin film transistor substrate for a FPS type liquid crystal display device according to the present invention.

FIG. 5 is a cross-sectional view taken along the line VV of FIG. 4 and is a schematic cross-sectional view of a TFT substrate for a liquid crystal display device according to the present invention.

As shown in FIGS. 4 to 5, an array substrate for a FPS type liquid crystal display device according to the present invention includes a gate wiring 106a formed on one surface of a transparent insulating substrate 101 in one direction and the gate wiring. A gate electrode 106b extending from 106a; The gate insulating film 111 formed on the insulating substrate 101 including the gate electrode 106b, the active layer 113a, and the source electrode 117b and the drain electrode formed on the active layer 113a and spaced apart from each other. 117c); A data line 117a formed on the gate insulating layer 111 and vertically intersecting with the gate line 106a; A pixel electrode 110 formed on the insulating substrate 101 corresponding to a pixel region where the gate wiring 106a and the data wiring 117a cross each other; A passivation film 123 formed on an entire surface of the insulating substrate 101 including the pixel electrode 110 and the data wiring 117a and exposing the pixel electrode 110 and the drain electrode 117c; A pixel electrode formed on the passivation layer 123 and electrically connecting the pixel electrode 110 and the drain electrode 117c with a plurality of common electrodes 129a and 129b overlapping the pixel electrode 110. It is configured to include a connection pattern (129c).

Here, the gate electrode 106b has a stacked structure of a transparent conductive material layer pattern 103b and a conductive metal layer pattern 105b. In this case, the transparent conductive material layer pattern 103b is formed of any one selected from a group of transparent materials including indium tin oxide (ITO) and indium zinc oxide (IZO). In the present invention, a case where ITO (Indium Tin Oxide) is used as the transparent conductive material layer pattern 103b will be described.

In addition, the conductive metal layer pattern 105b may be formed of aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), molybdenum tungsten (MoW), and molybdenum (MoTi). , At least one selected from the group of conductive metals including copper / mortitanium (Cu / MoTi). In the present invention, a case where copper (Cu) is used as the conductive metal layer pattern 105b will be described as an example.

The pixel electrode 110 is formed on the entire pixel region of the insulating substrate 101 corresponding to a space spaced apart from the gate wiring 106a and the data wiring 117a. In this case, the pixel electrode 110 is formed of any one selected from a group of transparent materials including indium tin oxide (ITO) and indium zinc oxide (IZO). In the present invention, a case where ITO (Indium Tin Oxide) is used as the transparent conductive material layer pattern 103b will be described.

In addition, the common electrodes 129a and 129b overlap the pixel electrode 110 with the gate insulating layer 111 and the passivation layer 123 interposed therebetween. In this case, the common electrode 129a overlaps the pixel electrode 110 of a large area disposed in the pixel region, and the common electrode 129b overlaps the data wiring 117a. The common electrode 129a may be formed of any one selected from a group of transparent materials including indium tin oxide (ITO) and indium zinc oxide (IZO). In the present invention, a case where ITO (Indium Tin Oxide) is used as the material of the common electrodes 129a and 129b will be described.

The pixel electrode connection pattern 129c electrically connects the pixel electrode 110 and the drain electrode 117d through the pixel electrode contact hole 127a.

Accordingly, the common electrodes 129a and 129b are supplied with reference voltages for driving the liquid crystals, that is, common voltages, to each pixel. The common electrodes 129a and 129b overlap the pixel electrode 110 of the large area with the passivation layer 123 interposed therebetween to form a fringe field.

As shown in FIG. 5, the thin film transistor T is disposed on the gate electrode 106b extending vertically from the gate wiring 106a formed on the insulating substrate 101 and on the gate electrode 106b. The gate insulating layer 111, the active layer 113a, and the ohmic contact layer 115a are formed together with the source electrode 117c and the drain electrode 117d spaced apart from each other by the channel region of the active layer 113a.

A gate pad (not shown) is formed at one end of the gate wiring 106a to extend from the gate wiring 106a to be connected to an external driving circuit unit.

Further, at one end of the data line 117a, a data pad (not shown) extending from the data line 117a and connected to the external driving circuit unit is formed.

Although not shown in the drawing, a lower alignment layer (not shown) is formed on the entire surface of the substrate including the plurality of common electrodes 129a and 129b.

A black matrix (BM) 143 for blocking light from being transmitted to an area excluding a pixel area on the color filter substrate 141 spaced apart from and bonded to the thin film transistor substrate, that is, the insulating substrate 101. Is formed.

In addition, color filter layers 145 of red, green, and blue colors are formed in the pixel region of the color filter substrate 141. In this case, the black matrix 143 is formed on the color filter substrate 141 between the color filter layers 145 of red, green, and blue colors.

Here, when the color filter substrate 141 and the insulating substrate 101 which is the thin film transistor substrate are bonded together, the black matrix 143 is an area excluding a pixel region of the insulating substrate 101, for example, a thin film transistor ( T), the gate wiring 106a and the data wiring 117a are disposed to overlap with each other.

Although not shown in the drawings, an upper alignment layer (not shown) is formed on the color filter layer 145 to arrange the liquid crystals in a predetermined direction.

In this manner, when a data signal is supplied to the pixel electrode 110 through the thin film transistor T, a fringe field is formed between the common electrodes 129a and 129b and the pixel electrode 110 supplied with the common voltage. The liquid crystal molecules arranged in the horizontal direction between the insulating substrate 101 and the color filter substrate 141 are rotated by dielectric anisotropy, so that the light transmittance of the liquid crystal molecules passing through the pixel region varies depending on the degree of rotation. As a result, gray scales are realized.

A method of manufacturing an array substrate for a FPS type liquid crystal display device according to the present invention having the above configuration will be described with reference to FIGS. 6 to 7.

6A to 6R are cross-sectional views illustrating a manufacturing process of an array substrate for a FPS type liquid crystal display device according to the present invention.

7A to 7F are cross-sectional views schematically illustrating a process of removing an ITO tail when forming a gate wiring and a pixel electrode in the method of manufacturing a FPS type liquid crystal display device according to the present invention.

As shown in FIGS. 6A and 7A, a plurality of pixel areas including a switching area are defined on the transparent insulating substrate 101, and the first transparent conductive material layer 103 and the first transparent conductive material layer 103 are formed on the insulating substrate 101. The 1 conductive metal layer 105 is deposited in order by the sputtering method. Here, the first transparent conductive material layer 103 may be formed of any one selected from the group consisting of indium tin oxide (ITO) and indium zinc oxide (IZO). Here, the case where ITO (Indium Tin Oxide) is used as the first transparent conductive material layer 103 will be described as an example.

In addition, the first conductive metal layer 205 may include aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), molybdenum tungsten (MoW), or molybdenum. At least one selected from the group of conductive metals, including titanium (MoTi), copper / mortitanium (Cu / MoTi), is used. Here, the case where copper (Cu) is used as the first conductive metal layer 205 will be described as an example.

Next, a photoresist having high transmittance is coated on the first conductive metal layer 105 to form a first photoresist layer 107.

Subsequently, an exposure process is performed on the first photosensitive film 107 through a first mask process using a first diffraction mask 109 including the light blocking part 109a, the transflective part 109b, and the transmission part 109c. In this case, the first diffraction mask 109 is a mask that can control the transmittance using a diffraction phenomenon of light, and includes a slit mask and a half-ton mask. Here, the case where the slit mask is used as the diffraction mask will be described as an example.

The light blocking portion 109a of the first diffraction mask 109 is positioned above the first photoresist layer 107 corresponding to the gate wiring, the gate electrode, and the gate pad formation region, and is disposed on the first diffraction mask 109. The transflective portion 109b is positioned above the first photoresist layer 107 corresponding to the pixel electrode formation region.

6B and 7B, the exposure process is performed, and then the first photoresist layer 107 is selectively removed through the development process, thereby forming a gate wiring, a gate electrode, and a gate pad forming region. The first pattern portion 107a and the second pattern portion 107b corresponding to the pixel electrode formation region are formed.

At this time, since the first pattern portion 107a does not transmit light, the thickness of the first photoresist layer 107 is maintained as it is. However, the second pattern portion 107b is partially removed, do. That is, the first pattern portion 107b has a thickness smaller than that of the second pattern portion 107a.

6C and 7C, the first transparent conductive material layer 103 and the first conductive layer are etched using the first pattern portion 107a and the second pattern portion 107b of the first photoresist film as an etch mask. The metal layer 105 is selectively etched to form a first metal layer pattern portion (not shown) and a first transparent conductive layer pattern portion (not shown) in the gate wiring forming region, and a second metal layer pattern portion in the gate electrode forming region. 105b and a second transparent conductive layer pattern portion 103b are formed, and a third metal layer pattern portion 105a and a third transparent conductive layer pattern portion 103a are simultaneously formed in the pixel electrode formation region.

At this time, the first transparent conductive material layer 103 and the first conductive metal layer 105 during the first wet etching, the copper layer (Cu) and the first conductive used as the first transparent conductive material layer 103 An etching solution capable of simultaneously etching the ITO layer used as the metal layer 105 is used. In the case of etching the copper layer (Cu) used as the first transparent conductive material layer 103 and the ITO layer used as the first conductive metal layer 105 by using the etching solution, the copper layer (Cu) Since the etching rate of the etching rate and the ITO layer is different, the etching degree of the copper layer (Cu) and the ITO layer is different. That is, the etching rate of the copper layer Cu is about 90 kV / sec, and the etching rate of the ITO layer is about 8 kPa, and the copper layer Cu is etched faster than the ITO layer. In this case, as the etching solution, an etching solution capable of wet etching the first transparent conductive material layer 103 and the second conductive metal layer 105 collectively is used.

Therefore, during the first wet etching of the first transparent conductive material layer 103 and the first conductive metal layer 105 using the etching solution, the first transparent conductive material layer 103 and the first conductive metal layer ( Since the degree of etching 105 is different, the ITO tail (not shown, see "A" in FIG. 7C) of the first transparent conductive material layer 103 is longer than that of the first conductive metal layer 105. do.

Then, as shown in FIGS. 6D and 7D, an ashing process is performed, and the first metal layer pattern portion (not shown) and the first transparent conductive layer pattern portion (not shown) in the gate wiring forming region are formed. A portion of the first pattern portion 107a of the first photosensitive film formed on the second metal layer pattern portion 105b and the second transparent conductive layer pattern portion 103b in the gate electrode formation region is etched to form the pixel electrode. The second pattern portion 107b of the first photosensitive film formed on the third transparent conductive layer pattern portion 103a and the third metal layer pattern portion 105a in the region is completely etched to form the first layer in the pixel electrode formation region. 3 The upper surface of the transparent conductive layer pattern portion 103a is exposed. In this case, since a portion of the first pattern portion 107a of the first photoresist layer is etched, a first transparent conductive layer pattern portion (not shown) in the gate wiring forming region and a second transparency in the gate electrode forming region are formed. The side surface of the full layer pattern part 103b is exposed to the outside. This is because the first transparent conductive material layer 103 is etched slower than the first conductive metal layer 105 during the first wet etching, so that the side portion of the first transparent conductive material layer 103 is etched slowly. Compared to the first conductive metal layer 105, a shape protruding to the outside, that is, an ITO tail (not shown, see “A” in FIG. 7C) is formed.

In addition, although the first pattern portion 107a is etched by a predetermined thickness through the ashing process and overlaps the upper surfaces of the first metal layer pattern portion (not shown) and the second metal layer pattern portion 105b, the first transparency Since the side portions of the entire layer pattern portion (not shown) and the second transparent conductive layer pattern portion 103b do not overlap, the side portions of the first transparent conductive layer pattern portion (not shown) and the second transparent conductive layer pattern portion 103b, That is, the ITO tail (not shown, see “A” in FIG. 7C) is exposed to the outside.

Subsequently, as shown in FIGS. 6E and 7E, the first pattern portion 107a, which has been partially etched by the ashing process, is used as an etching mask, and the exposure is performed using the etching solution used during the first wet etching process. The exposed first transparent conductive material layer pattern portion (not shown) and the second transparent conductive material layer pattern portion together with the third conductive metal layer pattern 105a and the third transparent conductive layer pattern portion 103a thereunder. By collectively etching the side portions of 103b by a secondary wet etching process, gate wirings (not shown, see 106a in FIG. 4) and gate electrodes 106b are formed in the gate wiring forming region and the gate electrode forming region, respectively. The pixel electrode 110 is formed in the pixel electrode formation region. In this case, the second wet etching process is performed until the exposed dummy conductive metal layer pattern 105a is completely etched.

In addition, the gate wiring (not shown) (see 106a of FIG. 4) has a stacked structure of the first wet-etched first transparent conductive material layer pattern portion (not shown) and the first conductive metal layer pattern portion (not shown). The gate electrode 106b has a stacked structure of a second transparent conductive material layer pattern portion 103b and a second conductive metal layer pattern portion 105b.

In addition, the pixel electrode 110 includes a second wet-etched third transparent conductive material layer pattern part 103a.

As shown in FIGS. 6F and 7F, the first transparent conductive material layer pattern part (not shown) and the gate electrode 106b constituting the gate wiring (not shown, see 106a of FIG. 4) are formed. Since the side portions of the second transparent conductive material layer pattern part 103b and the third transparent conductive material layer pattern part 103a constituting the pixel electrode 110 are collectively etched by the second wet etching process, the ITO tail (tail ) Will decrease.

Therefore, the gap between the gate wiring 106a and the pixel electrode 110 is secured by reducing the tails of the sidewalls of the gate wiring 106a and the pixel electrode 110, thereby providing the gate wiring 106a. And short generation between the pixel electrode 110 and the pixel electrode 110 are prevented.

Next, as shown in FIG. 6G, after the remaining first pattern portion 107a is removed, silicon nitride (SiNx) or silicon oxide film (SiO ₂ ) is formed on the entire surface of the substrate including the pixel electrode 110. A gate insulating layer 111 is formed, and an amorphous silicon layer (a-Si: H) 113 and an amorphous silicon layer (n + or p +) 115 containing impurities and a second conductive layer are formed on the gate insulating layer 111. The metal layers 117 are sequentially stacked.

At this time, the amorphous silicon layer (n + or p +) 115 containing the amorphous silicon layer (a-Si: H) 113 and the impurities is deposited by a chemical vapor deposition (CVD) method, 2 conductive metal layer 117 is deposited by a sputtering method.

Although only the chemical vapor deposition method and the sputtering method are described above as the deposition method, other deposition methods may be used if necessary. The second conductive metal layer 117 may be formed of a metal such as aluminum (Al), tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), molybdenum tungsten At least one selected from the group of conductive metals including titanium (MoTi), copper / moly titanium (Cu / MoTi) is used.

Subsequently, as illustrated in FIG. 6H, a photoresist having high transmittance is coated on the second conductive metal layer 117 to form a second photosensitive layer 119.

Next, an exposure process is performed on the second photosensitive film 119 through a second mask process using a second diffraction mask 121 including the light blocking part 121a, the transflective part 121b, and the transmitting part 121c. . In this case, the second diffraction mask 121 is a mask that can control the transmittance using a diffraction phenomenon of light, and includes a slit mask and a half-ton mask.

Here, the case where the slit mask is used as the diffraction mask will be described as an example.

In this case, the light blocking portion 121a of the second diffraction mask 121 is located above the second photoresist layer 119 corresponding to the data pad formation region together with the data wiring, source electrode and drain electrode formation regions. The transflective portion 121b of the second diffraction mask 121 is positioned above the second photosensitive layer 119 corresponding to the channel formation region of the thin film transistor.

Subsequently, as illustrated in FIG. 6I, the second photoresist layer 119 is etched through the exposure process, and then the first pattern portion 119a corresponding to the data wiring, source electrode, and drain electrode formation regions is formed. ) And a second pattern portion 119b corresponding to the channel formation region.

At this time, since the first pattern portion 119a does not transmit light, the thickness of the second photoresist layer 119 is maintained. However, since the second pattern portion 119b transmits a part of the light, do. That is, the second pattern portion 119b is thinner than the first pattern portion 119a.

Next, the second conductive metal layer 117, the amorphous silicon layer 115 including impurities, and the amorphous silicon layer using the first pattern portion 119a and the second pattern portion 119b of the second photoresist layer as an etch mask. The 113 is sequentially etched together with the data line 106a and the data pad (not shown) perpendicularly intersecting with the gate line 106a and on the gate insulating layer 111 corresponding to the gate electrode 105c. The active layer 113a and the ohmic contact layer 115a are formed.

Subsequently, as illustrated in 6j, an ashing process may be performed to form a second pattern portion corresponding to the channel formation region along with a portion of the first pattern portion 119a corresponding to the source electrode and drain electrode formation region. Completely remove 119b). In this case, an upper surface of the second conductive metal layer 117 overlapping the channel region is exposed to the outside.

Next, the exposed portions of the second conductive metal layer 117 are etched using the first pattern portion 119a from which the portions are removed, and the source electrode 117b and the drain electrode 117c are separated from each other. Form. At this time, a portion of the ohmic contact layer 115a on the channel region is exposed to the outside.

Subsequently, as shown in FIG. 6K, the ohmic contact layer 115a exposed between the source electrode 117b and the drain electrode 117c is also etched and spaced apart from each other. At this time, a channel region is formed in the active layer 113a under the etched ohmic contact layer 115a.

Next, as shown in FIG. 6L, the first pattern portion 119a of the second photoresist film is removed, and then an inorganic insulating material or organic insulating material made of silicon nitride (SiNx) or silicon oxide film (SiO ₂ ) is formed on the entire surface of the substrate. A material is deposited to form a passivation layer 123, and then a photoresist having a high transmittance is coated on the passivation layer 123 to form a third photoresist layer 125. An example of using an inorganic insulating material made of silicon nitride (SiNx) or silicon oxide film (SiO ₂ ) as the passivation film 123 will be described.

Subsequently, as illustrated in FIG. 6M, the third photoresist layer 125 is patterned to form a third photoresist layer pattern 125a by performing an exposure and development process by a third mask process using an exposure mask (not shown). do.

Next, as shown in FIG. 6N, the passivation layer 123 and the gate insulating layer 111 below are selectively etched using the third photoresist pattern 125a as a mask to form the drain electrode 117c and the pixel. The pixel electrode contact hole 127a exposing the electrode 103a is formed. Although not shown in the drawing, the gate pad contact hole (not shown) exposing the gate pad (not shown) and the data pad contact exposing the data pad (not shown) are formed when the pixel electrode contact hole 127a is formed. Holes (not shown) are also formed.

Subsequently, as shown in FIG. 6O, the third photoresist layer pattern 125a is removed, and the second transparent conductive material layer 129 is disposed on the passivation layer 123 including the pixel electrode contact hole 127a. It deposits by magnetron sputtering. At this time, as the second transparent conductive material layer 129, any one selected from a transparent material group including indium tin oxide (ITO) and indium zinc oxide (IZO) is used.

Next, a fourth photoresist layer 131 is formed by applying a photoresist having a high transmittance on the second transparent conductive material layer 129.

Subsequently, as illustrated in FIG. 6P, the fourth photoresist layer pattern 131a is selectively patterned by performing an exposure and development process through a fourth mask process using an exposure mask (not shown) to selectively pattern the fourth photoresist layer 131. To form.

Next, as illustrated in FIG. 6Q, the second transparent conductive material layer 129 is selectively etched using the fourth photoresist pattern 131a as an etching mask, and thus the plurality of common electrodes 129a and 129b are spaced apart from each other. And a pixel electrode connection pattern 129c for electrically connecting the pixel electrode 110 and the drain electrode 117c through the pixel electrode contact hole 127a. In this case, when the plurality of common electrodes 129a and 129b and the pixel electrode connection pattern 129c are formed, although not shown in the drawing, the gate pad contact hole (not shown) and the data pad contact hole (not shown) are provided. A gate pad connection pattern (not shown) and a data pad connection pattern (not shown) respectively connected to the gate pad (not shown) and the data pad (not shown) are also formed.

Subsequently, although not shown in the drawing, the fourth photoresist layer pattern 131a is removed, and a lower alignment layer (not shown) is formed on the entire surface of the substrate including the plurality of common electrodes 129a and 129b, thereby forming the F film according to the present invention. The manufacturing process of the array substrate for the FPS type liquid crystal display device is completed.

Next, as shown in FIG. 6R, light is blocked from being transmitted to an area excluding the pixel area on the thin film transistor substrate, that is, the color filter substrate 141 spaced apart from each other and bonded to the insulating substrate 101. To form a black matrix (BM) 143.

Next, a color filter layer 145 of red, green, and blue colors is formed in the pixel region of the color filter substrate 141. At this time, the black matrix 143 is located on the color filter substrate 141 between the red, green, and blue color filter layers 145.

At this time, the black matrix 143 is an area except for the pixel region of the insulating substrate 101 when the color filter substrate 141 and the insulating substrate 101 that is the thin film transistor substrate are bonded together, for example, a thin film transistor. (T), the gate wiring 106a and the data wiring 117a are disposed so as to overlap.

Next, although not shown in the drawing, a process of manufacturing a color filter array substrate is completed by forming an upper alignment layer (not shown) on the color filter layer 145 to arrange liquid crystals in a predetermined direction.

Subsequently, although not shown in the drawing, the liquid crystal layer 151 is formed between the insulating substrate 101 and the color filter substrate 141 to manufacture a FPS type liquid crystal display device according to the present invention.

As described above, in fabricating an array substrate for a FPS type liquid crystal display device according to the present invention, a gate wiring and a pixel electrode are formed using one mask, and an active layer, a source electrode and a drain electrode are formed of one mask. It can be formed by using, the mask cost can be reduced by manufacturing the FPS type liquid crystal display device by four mask process instead of the conventional six mask process, thereby reducing the manufacturing process time and manufacturing cost .

In addition, according to the FPS type liquid crystal display array substrate according to the present invention, the transparent conductive material layer and the conductive metal layer laminated structure to form a gate wiring and a pixel electrode using the photoresist pattern as an etch mask, the transparent conductive material layer In the case of primary wet etching using an etchant for etching the conductive metal layer and the conductive metal layer, the transparent conductive material layer is etched later than the conductive metal layer due to the difference in the etch rate of the transparent conductive material layer and the conductive metal layer. As a result, a side of the transparent conductive material layer, for example, an ITO tail is generated, but after the first wet etching, the photoresist pattern is selectively removed through an ashing process, and the remaining photoresist pattern is etched. The exposed portions of the transparent conductive material layer and the conductive metal layer may be secondarily etched using the etching solution used during the first wet etching. By wet etching, the exposed portions of the metal conductive layer and the portions protruding from the transparent conductive material layer can be collectively etched, thereby reducing the ITO tail.

 In addition, according to the array substrate for the FSF type liquid crystal display device according to the present invention, the transparent conductive material layer and the conductive metal layer are first wet-etched at the same time to form the gate wiring and the pixel electrode at the same time. By simultaneously wet etching the exposed portion of the metal layer with the etching solution used during the first wet etching, the conductive metal layer, for example, copper (Cu) residue can be improved.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments.

Accordingly, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention.

101: insulation substrate 106a: gate wiring
106b: gate electrode 109: first diffraction mask
110: pixel electrode 111: gate insulating film
113a: active layer 115a: ohmic contact layer
117a: data wiring 117b: source electrode
117c drain electrode 121 second diffraction mask 123 passivation film 127a pixel electrode contact hole
129a and 129b common electrode 129c pixel electrode connection pattern
141: color filter substrate 143: black matrix
145: color filter layer 151: liquid crystal layer

Claims (10)

Providing a substrate in which a gate wiring forming region and a pixel electrode forming region are defined;
Sequentially stacking a transparent conductive material layer and a conductive metal layer on the substrate;
Forming a first photoresist pattern having a first thickness and a second photoresist pattern having a second thickness thinner than the first thickness on the conductive metal layer;
First etching the conductive metal layer and the transparent conductive material layer simultaneously using the first and second photoresist pattern as an etch mask to form a first conductive metal layer pattern portion and a first transparent conductive layer pattern portion in the gate wiring forming region, and the pixel Forming a second conductive metal layer pattern portion and a second transparent conductive layer pattern portion in the electrode formation region;
Etching a portion of the first photoresist pattern and all of the second photoresist pattern to expose an upper surface of the second conductive metal layer pattern;
The remaining first photoresist pattern is an etch mask, and second exposed portions of the first conductive metal layer pattern and the first transparent conductive material layer pattern, and the exposed portions of the second conductive metal layer pattern and the second transparent conductive material layer pattern are etched. Thereby forming a gate wiring and a pixel electrode;
The first photoresist layer pattern is removed, and the gate insulating layer and the active layer are formed on the substrate including the gate wiring and the pixel electrode, and the source and drain electrodes are formed on the active layer and spaced apart from each other. Forming a data line;
Forming a pixel electrode contact hole exposing the drain electrode and the pixel electrode on an entire surface of the substrate including the data line; And
And forming a pixel electrode connection pattern on the passivation layer to electrically connect the pixel electrode and the drain electrode through the pixel electrode contact hole together with a plurality of common electrodes overlapping the pixel electrode. Method for manufacturing array substrate for device. The method of claim 1, wherein the first photoresist pattern and the second photoresist pattern are formed by a mask process using a diffraction mask. The method of claim 1, wherein the same etching solution is used in the first etching process and the second etching process. The method of claim 3, wherein the etching solution is an etching solution for simultaneously etching the transparent conductive material layer and the conductive metal layer. The method of claim 1, wherein the transparent conductive material layer and the conductive metal layer are collectively etched during the first etching process and the second etching process. The method of claim 1, wherein the secondary etching process is performed until the second conductive metal layer pattern portion in the pixel electrode formation region is completely removed. The data line of claim 1, further comprising a gate insulating layer and an active layer formed on the substrate including the gate line and the pixel electrode, and a data line vertically intersecting the gate line with source and drain electrodes spaced apart from each other. Forming the method, the array substrate manufacturing method for a liquid crystal display device, characterized in that made through a mask process using a diffraction mask. The material of claim 1, wherein any one selected from the group consisting of indium tin oxide (ITO) and indium zinc oxide (IZO) is used as a material of the transparent conductive material layer, and aluminum (Al) is used as the material of the conductive metal layer. , Tungsten (W), copper (Cu), molybdenum (Mo), chromium (Cr), titanium (Ti), molybdenum tungsten (MoW), molybdenum (MoTi), copper / mortitanium (Cu / MoTi) A method of manufacturing an array substrate for a liquid crystal display device using at least one selected from the group of conductive metals. The method of claim 1, wherein the etching of the exposed portions of the first conductive metal layer pattern and the first transparent conductive material layer pattern and the second conductive metal layer pattern and the second transparent conductive material layer pattern is performed through the secondary etching process. The side surface of the first transparent conductive material layer pattern and the second transparent conductive material layer pattern are also etched together, characterized in that the array substrate manufacturing method for a liquid crystal display device. The liquid crystal display device of claim 1, wherein the gate wiring is formed of the first conductive metal layer pattern and the first transparent conductive material layer pattern, and the pixel electrode is formed of the second transparent conductive material layer pattern. Array substrate manufacturing method.

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