KR20130059580A - Semiconductor package and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A semiconductor package and a method for manufacturing the same are provided to improve the productivity of a substrate by using a double substrate method. CONSTITUTION: A base substrate(10) is selectively removed to form a bump formation region. An insulation part(30) is formed in a region except the bump formation region. A rewiring circuit(40) is formed in the surface of the base substrate including the insulation part. A first solder resist layer(51) patterned on the outer layer of the rewiring circuit is formed. A patterned second solder resist layer(52) covering the insulation part is formed. A semiconductor chip is mounted on the surface of the base substrate in including the rewiring circuit.

Description

Semiconductor package and its manufacturing method {SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME}

The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a routeable semiconductor package and a method of manufacturing the same based on a lead frame.

Recently, as the electronic industry has developed rapidly, various technologies have been developed in the field of electronic devices. In particular, with the trend toward thinner and shorter electronic products, more and more packages are required to form fine pitch patterns and to increase the number of input / output (I / O) terminals.

As a result, semiconductor package technology has produced a multi-pin pin grid array (PGA) or a surface-mounted quad flat package (QFP) from a conventional in-line package (DIP). Since then, it has been changed to Plastic Ball Grid Array (PGA), Tape Ball Grid Array (TBGA), and Flip Chip, which are BGA (Ball Grid Array) type products that can satisfy two types of multi-pinning and high density mounting. In the memory product field, small out-line J-Bend packages (SOJ) and thin small out-line packages (TSOP), which are in the form of small-out-line packages (SOPs) and thin-out-line packages (TSOPs), are mainstream. have.

Such a semiconductor package and a semiconductor package for forming a redistribution circuit pattern on a base substrate of a conductive material among the manufacturing method thereof and a method of manufacturing the same are proposed in Korean Patent Publication No. 10-2011-0021407.

1 is a view briefly showing a conventional semiconductor package and a method of manufacturing the same.

Referring to FIG. 1, referring to the prior art, as shown in FIGS. 1A and 1B, half etching may be performed on one surface of a base substrate 10 of a conductive material such as a prepared lead frame. And (c), a polymer resin of an insulating material is filled in the space formed by half etching. After that, as shown in FIG. 1 (d), the insulating part 30 is formed by grinding and removing the resin so that the conductive material is exposed to the entire surface of the resin-filled surface, and FIG. 1. As shown in (e), the redistribution circuit 40 is formed by performing additional half etching or pattern etching on the other surface on which the conductive material is not half-etched.

The conventional semiconductor package manufacturing method as described above is a problem occurs by going through the half etching process. 2 is a diagram illustrating a problem caused by a conventional semiconductor package and a method of manufacturing the same.

As shown in FIGS. 2A and 2B, when half etching is performed on one surface of the base substrate 10 of the conductive material, when the isotropic etching is performed, the redistribution circuit 40 is implemented. The corners of the portion are formed in a round shape (see a portion indicated by dotted round circles in FIGS. 2 (a) and 2 (b)). When the half etching process is performed as described above, a problem occurs in implementing the redistribution circuit due to the rounding of corners in the depth direction in which the redistribution circuit 40 is formed by isotropic etching during half etching.

That is, as shown in FIG. 2 (a), when the pitch of the circuit is wide at the portion where the redistribution circuit 40 is implemented, no problem occurs in the normal operation of the circuit (FIG. 2 ( (a) as shown by the dotted circle in the dotted line), as shown in FIG. 2 (b), in the case of a fine circuit having a narrow pitch, the portion indicated by the dotted circle in FIG. Likewise, there is a high possibility that a short circuit occurs between circuit wirings in the redistribution circuit 40 due to the rounding phenomenon caused by the isotropic etching of the half etching machine.

In addition, in order to solve such a short circuit problem, when the over etching is more deeply etched, there is a high problem that the line width of a normal fine circuit is reduced or the circuit wiring is open. .

Therefore, when etching, conditions such as exposure time to an etching solution or an etching solution are important, and in particular, when the redistribution circuit is implemented as a fine circuit having a narrow pitch, it is difficult to satisfy the etching conditions in which the circuit operates normally. There is.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package having a reliable circuit reliability and a method for manufacturing the same even when the redistribution circuit has a fine circuit pattern.

As a means for solving the above technical problem, the present invention is a method of manufacturing a semiconductor package having a redistribution circuit on at least one surface, comprising: (a) preparing a conductive base substrate; (b) a first etching step of selectively removing the remaining regions of the base substrate except for the region to be formed as a bump to penetrate the base substrate; (c) filling an area selectively removed by the first etching in the base substrate with an insulating material to form an insulating part; And (d) forming a redistribution circuit on at least one surface of the base substrate including the insulating portion; It provides a method for manufacturing a semiconductor package comprising a.

In addition, the present invention provides a method of manufacturing a semiconductor package having a redistribution circuit on at least one surface, comprising the steps of: (a) attaching a conductive base substrate to both surfaces of the interlayer; (b) a second etching step of selectively removing the remaining regions of the at least one base substrate attached to the interlayer, except for a region to be formed as a bump, to expose the interlayer; (c) forming an insulating part by filling an area of the base substrate selectively removed by the second etching with an insulating material; (d) forming a redistribution circuit on a surface of the base substrate including at least one of the insulating parts, opposite to a surface to which the interlayer is attached; And (e) separating the base substrate and the interlayer; It provides a method for manufacturing a semiconductor package comprising a.

Also, in the present invention, the step (b) may selectively remove the base substrate attached to both surfaces of the interlayer so that the interlayer is exposed to the remaining regions except for the region to be formed as a bump by one process. A semiconductor package manufacturing method is provided.

In the present invention, the step (d) provides a method for manufacturing a semiconductor package, characterized in that to form a redistribution circuit in one process for the base substrate including the insulating portion attached to both sides of the interlayer.

In addition, in the present invention, the redistribution circuit provides a method of manufacturing a semiconductor package, characterized in that formed by a pattern plating method or an etching method.

The present invention also provides a method for removing the insulating material between the step (c) and the step (d) so that the base substrate is exposed to the outside when the insulating material covers the base substrate; It provides a method for manufacturing a semiconductor package comprising a further.

In addition, the present invention comprises the steps of forming a patterned first solder resist layer on the outer layer of the redistribution circuit between the step (d) and the step (e); It provides a method for manufacturing a semiconductor package comprising a further.

In addition, the present invention comprises the steps of performing a third etching in any pattern on the area of the base substrate except the insulating portion on the opposite side of the surface on which the redistribution circuit is formed; It provides a method for manufacturing a semiconductor package comprising a further.

In addition, the third etching in the present invention, the semiconductor package manufacturing method, characterized in that for etching the entire area except the insulating portion so that the insulating portion protrudes.

In addition, the present invention comprises the steps of forming a patterned second solder resist layer covering the insulating portion on the opposite side of the base substrate on which the redistribution circuit is formed; It provides a method for manufacturing a semiconductor package comprising a further.

In addition, the present invention provides a method of manufacturing a semiconductor package having a redistribution circuit on at least one surface, comprising the steps of: (a) attaching a conductive base substrate to both surfaces of the interlayer; (b) half etching a region other than a region to be formed as a bump in at least one of the base substrates attached to the interlayer; (c) filling the region selectively removed by the half etching with an insulating material to form an insulating portion; (d) separating the base substrate including the insulation and the interlayer; And (e) selectively etching the opposite side of the half-etched surface of the base substrate including at least one of the insulating portions so that the insulating portion is exposed to the outside corresponding to the redistribution circuit pattern; It provides a method for manufacturing a semiconductor package comprising a.

In addition, the present invention includes the steps of mounting a semiconductor chip on one surface of the base substrate on which the redistribution circuit is formed; It provides a method for manufacturing a semiconductor package comprising a further.

In addition, the present invention is a bump substrate of the conductive base substrate is selectively removed other than the bump area; An insulating portion of an insulating material filled in the removed region of the bump substrate to penetrate the bump substrate; A redistribution circuit formed on at least one surface of the bump substrate including the insulation portion; And a semiconductor chip mounted on one surface of the bump substrate on which the redistribution circuit is formed. It provides a semiconductor package comprising a.

In addition, the redistribution circuit in the present invention, the die pad to which the semiconductor chip is attached; And a land insulated from the die pad and electrically connected to the semiconductor chip. It provides a semiconductor package comprising a.

In addition, the redistribution circuit in the present invention, the solder pad is electrically connected through the semiconductor chip and the solder ball; It provides a semiconductor package comprising a.

In addition, the present invention is an encapsulant of the insulating material surrounding the mounted semiconductor chip; It provides a semiconductor package comprising a further.

In addition, the present invention is a solder portion etched in an arbitrary pattern on the other side of the bump substrate on the opposite side of the surface on which the redistribution circuit is formed; It provides a semiconductor package comprising a further.

In addition, the solder portion in the present invention provides a semiconductor package, characterized in that the entire surface is made of an etching.

Further, in the present invention, a patterned solder resist layer covering the insulating portion on the opposite side of the surface of the bump substrate on which the redistribution circuit is formed; It provides a semiconductor package comprising a further.

Since the semiconductor package and the method of manufacturing the same according to the present invention are etched through the conductive material, the difficulty of satisfying the difficult etching conditions is eliminated.

In addition, the semiconductor package and the method of manufacturing the same according to the present invention eliminates the problem that the circuit is shorted or opened even if the redistribution circuit is implemented as a fine circuit having a narrow pitch by etching through the conductive material.

In addition, the semiconductor package and its manufacturing method according to the present invention has the effect of improving the productivity of the substrate in terms of the semiconductor package manufacturing process by lowering the semiconductor package by manufacturing a double-substrate (Double Substrate) method, and lowers the manufacturing cost of the semiconductor package.

In addition, the semiconductor package and a method of manufacturing the semiconductor package according to the present invention, in a conductive material having a microcircuit, is etched on a portion of one surface of the base substrate of the conductive material on which solder paste or solder balls are to be seated. By ensuring the mechanical or electrical reliability of the solder when soldering.

1 is a view briefly showing a conventional semiconductor package and a method of manufacturing the same.
2 is a diagram illustrating a problem caused by a conventional semiconductor package and a method of manufacturing the same.
3A is a diagram schematically illustrating a semiconductor package and a method of manufacturing the same according to an embodiment of the present invention.
3B is a view briefly illustrating a flowchart of the method of manufacturing a semiconductor package according to FIG. 3A.
4A is a diagram schematically illustrating a method of manufacturing a semiconductor package capable of simultaneously producing two semiconductor packages according to one embodiment of the present invention.
4B is a view briefly illustrating a flowchart of a method of manufacturing a semiconductor package according to FIG. 4A.
FIG. 5A is a diagram schematically illustrating a semiconductor package and a method of manufacturing the same according to an embodiment of the present disclosure.
5B is a view briefly illustrating a flowchart of the method of manufacturing a semiconductor package according to FIG. 5A.
6A to 6C are views schematically illustrating a semiconductor package and a method of manufacturing the same for reliable soldering according to an embodiment of the present invention in order.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly explain the present invention in the drawings, parts not related to the description are omitted, and similar parts are denoted by similar reference numerals throughout the specification.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1st Example

3A is a view schematically illustrating a semiconductor package and a method of manufacturing the same according to an embodiment of the present invention in order, and FIG. 3B is a view briefly illustrating a flowchart of the method of manufacturing the semiconductor package according to FIG. 3A.

As shown in FIG. 3B, in the method of manufacturing a semiconductor package according to the present exemplary embodiment, a step (S10) of preparing a conductive base substrate 10 is large, except for a region to be formed as a bump on the base substrate 10. First etching step S20 of selectively removing the base substrate 10 to penetrate through it, and filling the region selectively removed by the first etching in the base substrate 10 with an insulating material to form the insulating part 30. And forming a redistribution circuit 40 on at least one surface of the base substrate 10 including the S30 and the insulation 30.

In this case, when the insulating material covers the base substrate 10, the forming of the insulating part 30 further includes removing the insulating material so that the base substrate 10 is exposed to the outside (S31). It may include, and after the step (S40) of forming the redistribution circuit 40, the step of forming a patterned first solder resist layer 51 on the outer layer of the redistribution circuit 40 (S41), the base substrate Performing third etching in a random pattern on a surface opposite to the surface on which the redistribution circuit is formed (S51), and covering the insulating part 30 on the surface opposite to the surface on which the redistribution circuit 40 is formed among the base substrates 10. The method may further include forming a patterned second solder resist layer 52 (S52) and mounting a semiconductor chip on one surface of the base substrate 10 on which the redistribution circuit 40 is formed (S60). .

Hereinafter, each step will be described in detail with reference to the drawings of FIG. 3A.

As shown in FIG. 3A (a), first, a base substrate 10 of a conductive material is prepared (S10). In this case, the conductive base substrate 10 transmits or receives an electrical signal with the semiconductor chip, and supports the semiconductor chip 60 when the semiconductor chip 60 is mounted on at least one surface of the base substrate 10. It is a substrate on a plate. Since the base substrate 10 should basically have excellent electrical conductivity, a gold, silver (Ag), or copper (Cu) material is generally used. However, the base substrate 10 is made of nickel (copper) having excellent electrical conductivity and elongation. An alloy lead frame made of a mixture of Ni), silicon (Si), and phosphorus (P) may be used. The base substrate 10 is not only an electrical conductivity, but also a high thermal conductivity, it is preferable to use a material that can effectively dissipate heat generated from the semiconductor chip.

Thereafter, as shown in FIG. 3A (b), the base substrate 10 is selectively removed so that the base substrate 10 penetrates through the remaining regions except for the region to be formed as a bump by the first etching. (S20). The substrate formed through the etching process will be referred to as a bump substrate 20.

In order to form the bump substrate 20, the base substrate 10 is subjected to a conventional etching method, that is, an exposure and development process so as to correspond to a region where bumps are to be formed in order to apply a resist layer and to pattern the resist layer. After roughening, the base substrate 10 is selectively etched using the patterned resist layer as a mask.

By etching so as to penetrate the base substrate 10, the corners of the portion where the redistribution circuit 40 is to be formed by isotropic etching during conventional half etching are not formed in a rounded round shape. The problem of electrical connection between them is eliminated, and it is not necessary to satisfy the difficult nicking conditions during etching.

Thereafter, as shown in FIG. 3A (d), the region selectively removed by the first etching is filled with an insulating material to form the insulating portion 30 (S30).

The insulating portion 30 is formed by filling the portion removed by etching of the base substrate 10 with an insulating material, thereby preventing the electrical connection between the bumps and the insulating portion 30 is coupled to the bump substrate 20. The bump substrate 20 can support the structure of the bump substrate 20 from mechanical forces such as bending and warping that can be applied from the outside. At this time, the insulating material to form the insulating portion 30 is usually made of a resin of a polymer material (Resin), but not limited to the material that can prevent the electrical connection, but in addition to the insulating properties bump substrate 20 It is preferable to have adhesive strength with) and to have a predetermined rigidity when cured.

In order to fill the insulating material with the bump substrate 20, a method such as screen printing may be used, or heat and / or pressure may be applied to the bump substrate 20 with a plate-like layer made of an insulating material. 30) may be formed.

In the process of forming the insulating portion 30 by filling the insulating material with the bump substrate 20, as shown in FIG. 3A (c), when the reference insulating material covers the surface of the bump substrate 20, the bump substrate ( 20) may further include a step S31 of removing the insulating material to expose to the outside (see FIG. 3A (d)).

That is, the insulating material covering the bump substrate 20 may be removed by mechanical or chemical grinding or polishing by a variety of methods, whereby the conductive material portion except for the insulating portion 30 of the bump substrate 20 may be removed. Exposed to, it may be electrically connected to the semiconductor chip 60 in the future, or to make an electrical connection to the outside of the semiconductor package.

Thereafter, as illustrated in FIG. 3A (g), the redistribution circuit 40 is formed on at least one surface of the bump substrate 20 filled with the insulating portion 30 (S40).

The redistribution circuit 40 is electrically connected between the semiconductor chip 60 and the bumps, and transmits an electrical signal transmitted from the semiconductor chip to the outside through the bump, or transmits an electrical signal transmitted from the outside through the bump to the semiconductor. It serves to transfer to the chip (60).

At this time, when the redistribution circuit 40 is electrically coupled to the semiconductor chip 60 by a wire bonding method, the redistribution circuit 40 is a die pad 41 to which the semiconductor chip 60 is attached. And a land 42 electrically disconnected from the die pad 41 and capable of transmitting or receiving an electrical signal to or from an outside of the semiconductor package through the wire 61 of the semiconductor chip 60. When the redistribution circuit 40 is electrically coupled to the semiconductor chip 60 in a flip chip manner, the redistribution circuit 40 may transmit and receive an electrical signal through the solder ball 62. The solder pad 43 may be included.

The redistribution circuit 40 may be formed by a pattern plating method or an etching method. As an example, a method of forming the redistribution circuit 40 by an etching method is simply illustrated in FIGS. 3A (e) to 3A (g). That is, as shown in FIG. 3A (e), the conductive layer 31 is formed on at least one surface of the bump substrate 20 filled with the insulating portion 30, and as shown in FIG. 3A (f), In order to pattern the formed conductive layer 31 into the redistribution circuit 40, the first resist layer 32 is coated, and the first resist layer patterned through exposure and development processes to the applied first resist layer 32. By using (32) as a mask, as shown in Fig. 3A (g), the conductive layer 31 is subjected to an etching process for selectively removing regions other than the wiring of the redistribution circuit 40. The redistribution circuit 40 is formed.

At this time, the conductive layer 31 shown in Figure 3a (e) may be formed through electroless plating and electrolytic plating, a method of laminating a film on a thin plate of a metal material such as copper foil (Cu Foil) It can form through etc.

As an etching method according to another embodiment other than the method of forming the redistribution circuit 40 by the etching method described above, the conductive layer 31 is formed by plating or lamination, and the first layer is formed on the conductive layer 31. The resist layer 32 is patterned through an exposure and development process, electroplated on the first resist layer 32 to form a patterned plating layer, and then the first resist layer 32 is peeled off and flash-etched. The redistribution circuit 40 may be formed.

As another method other than the etching method among the methods for forming the redistribution circuit 40 as described above, the redistribution circuit 40 may be formed by a pattern plating method. For example, unlike the method of the above etching, the first resist layer 32 is first applied without forming the conductive layer 31, and the first resist layer 32 is patterned through exposure and development. Thereafter, the patterned first resist layer 32 may be electroless plated to form a circuit by peeling the first resist layer 32.

In a pattern plating method according to another embodiment other than the pattern plating method described above, electroless plating is performed on the entire surface of the base substrate 10 including the insulating portion 30, and a first resist layer is formed on the electroless plating layer. After applying (32) and patterning by exposure and development, the patterned first resist layer 32 is subjected to electrolytic plating, and the first resist layer 32 is peeled off and flashed on the entire surface of the substrate surface. By etching, the redistribution circuit 40 can also be formed.

The redistribution circuit 40 may be formed by the etching method or the pattern plating method as described above, but the redistribution circuit 40 may be formed by various methods not illustrated.

Thereafter, as illustrated in FIG. 3A (h), the first solder resist layer 51 may be formed on the redistribution circuit 40.

The patterned first solder resist layer 51 may be formed as a surface treatment process for protecting the redistribution circuit 40 and preventing soldering on unnecessary portions of the substrate.

In this case, the patterned first solder resist layer 51 is a screen for applying solder resist ink on one surface of the bump substrate 20 on which the redistribution circuit 40 is formed using a screen plate. The patterned first solder resist layer 51 may be formed by a screen printing method or by applying a solder resist ink, and then applying a photo method to the applied solder resist by exposure and development. have.

Subsequently, as illustrated in FIG. 6A, a patterned second solder resist 52 covering the insulating part 30 may be formed on the opposite side of the base substrate 10 on which the redistribution circuit 40 is formed. .

The process of forming the second solder resist 52 is the same as described in the above-described process of forming the first solder resist 51, and the process of forming the first solder resist 51 and the second solder resist 52 are performed. The forming process may be changed in order, or may be performed simultaneously by one process. That is, the solder resist layer is screen printed on both surfaces of the base substrate 10 on which the redistribution circuit 40 is formed by one process, or is exposed and developed using photosensitive solder resist ink to expose the first solder resist layer 51. And the second solder resist layer 52 may be simultaneously formed.

Before forming the second solder resist 52 described above, after the redistribution circuit 40 is formed (S40), an insulating part (a part of the base substrate 10 formed on the opposite side of the surface on which the redistribution circuit 40 is formed) is formed. The method may further include performing a third etching (S51) in an arbitrary pattern on the region except for 30).

FIG. 6B is a diagram schematically illustrating a semiconductor package and a method of manufacturing the same for reliable soldering according to an embodiment of the present invention.

As shown in FIG. 6B (a), in the base substrate 10 on which the redistribution circuit 40 is formed, as shown in FIG. 6B (b), on the opposite side to the surface on which the redistribution circuit 40 is formed. A second resist layer 33 for third etching in an arbitrary pattern may be formed in a region other than the insulating portion 30. In this case, the second resist layer 33 may be formed only on the opposite side of the surface on which the redistribution circuit 40 is formed among the base substrate 10, but the second resist layer 33 may be formed on both surfaces of the base substrate 10. It is preferable to form Forming the second resist layer 33 together on the surface on which the redistribution circuit 40 is formed, which is the surface opposite to the surface on which any pattern of the base substrate 10 is to be formed, is the redistribution circuit 40 by the third etching. This is to prevent the damage.

Subsequently, an exposure and development process is performed to form the second resist layer 33 in an arbitrary pattern on the opposite side of the surface on which the redistribution circuit 40 is formed, that is, the surface on which the arbitrary pattern is to be formed. By etching through the patterned second resist layer 33 as a mask, as shown in Fig. 6B (c), the base substrate having grooves in an arbitrary pattern in the region except for the insulating portion 30 ( 10) can be formed.

The base substrate 10 having grooves in an arbitrary pattern is completed as a semiconductor package, and then solder such as solder paste during soldering to make electrical contact with other substrates. In the case of contacting with the base substrate 10, the contact surface area between the base substrate 10 and the solder (not shown) may be increased to enhance adhesion between the base substrate 10 and electrical reliability as well as mechanical reliability between the solder and the base substrate 10. In this case, the semiconductor package is mounted on the surface of the substrate through a pre-flux process such as electroless tin plating, a solder paste coating process, and a heat treatment process without additional surface treatment. can do.

As described above, even after forming an arbitrary pattern on the surface opposite to the surface on which the redistribution circuit 40 is formed in the base substrate 10 by the third etching, the patterned second solder resist layer covering the insulating portion 30 ( 52 may be formed (S52).

As shown in FIG. 6B (d), a second solder resist layer patterned on an opposite side of the base substrate 10 on which the redistribution circuit 40 is formed after the third etching is formed. 52). The detailed description is the same as described above, and protects the surface of the substrate by forming the patterned second solder resist layer 52.

Alternatively, as shown in Fig. 6C (c), the third etching is not an arbitrary pattern, and the third etching is performed on the opposite side of the surface on which the redistribution circuit 40 is formed in the base substrate 10. The entire area may be etched except for the insulating part 30 so that the insulating part 30 protrudes.

As described above, when one surface of the base substrate 10 has a shape in which the insulating portion 30 protrudes, the protruding insulating portion 30 itself acts like a solder resist, so that the surface of the substrate does not need to be coated with a separate solder resist layer. The surface can be protected and soldering can be prevented from unnecessary parts of the substrate.

As described above, as shown in the third etching step S51, the third etching step S51 is performed after the first solder resist layer 51 is formed, as described above, and after the third etching, the second solder is formed. Although the resist layer 52 can be formed, the first solder resist layer 51 is not formed first, but after the redistribution circuit 40 is formed (S40), a third etching is performed and the first solder resist layer is formed. The first solder resist layer 51 may be formed at the same time or the first solder resist layer 51 may be formed at the same time, and the first solder resist layer is formed after the second solder resist layer 52 is formed first. 51 may be formed.

Finally, as shown in FIG. 3A (J) or FIG. 3A (K), a step (S60) of mounting the semiconductor chip 60 on one surface of the base substrate 10 on which the redistribution circuit 40 is formed is performed. It may further include. When the semiconductor chip 60 is mounted on the base substrate 10, a wire bonding type may be mounted as shown in FIG. 3A (j), or as shown in FIG. 3A (k). Flip chip bonding may be implemented.

Briefly, in the case where the wire bonding type is mounted, the semiconductor may be formed by die attaching, wire bonding, and singulation after molding of the encapsulant 70 in order. When the package is completed and the flip chip bonding type is mounted, the semiconductor package is completed through die attaching and singulation after molding the encapsulant 70.

Second Example

4A is a view schematically illustrating a semiconductor package manufacturing method capable of simultaneously producing two semiconductor packages according to an embodiment of the present invention, and FIG. 4B is a simplified flowchart of the semiconductor package manufacturing method according to FIG. 4A. It is shown in the figure.

As shown in FIG. 4B, the method of manufacturing a semiconductor package according to the present embodiment is largely performed by attaching a conductive base substrate 10 to both surfaces of the interlayer 100 (S100), at least attached to the interlayer. A second etching step (S200) for selectively removing the remaining regions except the region to be formed as a bump on one base substrate 10 so that the interlayer 100 is exposed, and selectively by the second etching on the base substrate 10. Forming the insulating part 30 by filling the removed region with an insulating material (S300), the opposite side of the surface to which the interlayer 100 is attached among the base substrates 10 including the at least one insulating part 30. Forming a redistribution circuit 40 at step S400 and separating the bump substrate 20 from the interlayer 100 at step S500.

In this case, in the forming of the insulating part 30 (S300), when the insulating material covers the base substrate 10, the removing of the insulating material so that the base substrate 10 is exposed to the outside (S301) is further performed. It may include, and after forming the redistribution circuit 40 (S400), forming a patterned first solder resist layer 51 on the outer layer of the redistribution circuit 40 (S401), the base substrate Performing third etching in a random pattern on a surface opposite to the surface on which the redistribution circuit is formed (S501), and covering the insulating part 30 on the surface opposite to the surface on which the redistribution circuit 40 is formed among the base substrates 10. The method may further include forming a patterned second solder resist layer 52 (S502) and mounting a semiconductor chip on one surface of the base substrate 10 on which the redistribution circuit 40 is formed (S600). .

In the method of manufacturing the semiconductor package according to the present embodiment, first, as shown in FIG. 4A (a), the conductive base substrate 10 is attached to both surfaces of the interlayer 100 (S100). The base substrate 10 is attached to both sides of the interlayer 100 with the interlayer 100 interposed therebetween to separate the base substrate 10 and the interlayer 100 (S500). By going through the process, the productivity can be doubled and the cost can be lowered in terms of manufacturing cost.

In this case, the interlayer 100 should have adhesiveness capable of attaching the conductive base substrate 10 to at least a surface thereof, but in addition, when the etching is made to penetrate the base substrate 10, the interlayer is formed by etching. Corrosion resistance so that the 100 is not removed, the subsequently processed base substrate 10 is a material that can be easily separated from the interlayer 100, the warpage or warpage of the substrate during a series of manufacturing processes (Warpage In order to minimize), it is preferable that the material has a predetermined stiffness.

Thereafter, as shown in FIG. 4A (b), the interlayer 100 is exposed to the outside of the at least one base substrate 10 attached to the interlayer 100 except for a region to be formed as a bump. Selectively remove (S200).

Etching through the base substrate to expose the interlayer 100 to the outside is the same as described in the previous embodiment, except that in the present embodiment, the base substrate 100 attached to both sides of the interlayer 100 By simultaneously etching), by selectively removing the remaining regions except the regions to be formed as bumps for the two base substrates 10 so as to expose the interlayer 100 by one process, an advantageous effect in terms of productivity and cost reduction Occurs.

Thereafter, as shown in FIG. 4A (d), the insulating portion 30 is formed by filling the region selectively removed by the second etching on the base substrate with an insulating material (S300), but shown in FIG. 4A (c). As described above, when the insulating material covers the surface of the base substrate 10 in the process of filling the base substrate 10 with the base substrate 10 to form the insulating portion 30, the bump substrate 20 is exposed to the outside. The method may further include removing the material (S301).

Detailed description of the process of forming the insulating portion 30 (S300) or removing the insulating material (S301) is the same as described in the previous embodiment, but in this embodiment, two layers attached to both sides of the interlayer 100 are provided. Using a method such as screen printing an insulating material or applying a layer on the plate to the bump substrate 20 by applying a method such as screen printing to an area other than the area where the base substrate 10 is to be formed into a bump by one process. By this, the insulation part 30 can be formed. In addition, the insulation 30 is simultaneously applied by mechanical or chemical polishing or grinding so that the bump substrate 20 is exposed to the outside of the insulating material covering the surfaces of the two base substrates 10 attached to both surfaces of the interlayer 100. It can be formed.

Particularly, in the case of mechanical polishing using a brush, since the base substrate 10 is removed by attaching the base substrate 10 to both surfaces of the interlayer 100 according to the present embodiment, the overall thickness is more than doubled. Increased, it is possible to reduce the problem that the deformation caused by the base substrate 10 is pushed in the grinding or grinding process by the brush.

Thereafter, as shown in FIGS. 4A to 4A, redistribution is performed on a surface opposite to the surface on which the interlayer 100 is attached to the bump substrate 20 filled with the at least one insulating portion 30. A circuit 40 is formed (S400), and then, as shown in FIG. 4A (i), the bump substrate 20 filled with the insulating portion 30 and the interlayer 100 are separated (S500).

In this case, the method may further include forming a first solder resist layer 51 on the outer layer of the redistribution circuit 40 before separating the bump substrate 20 and the interlayer 100 (S401).

For the detailed description of the process of forming the redistribution circuit 40 (S400) and the process of forming the first solder resist layer 51 (S401), the etching method or the pattern plating method may be performed as described in the foregoing embodiment. In this embodiment, the redistribution circuit 40 for the two base substrates 10 is formed in one process with respect to the base substrate 10 attached to both surfaces of the interlayer 100. .

In addition, the step (S401) of forming the patterned first solder resist layer 51 on the outer layer of the redistribution circuit 40 is also the same as described in the previous embodiment, in the present embodiment a third etching (S501), Rather than forming the second solder resist layer 52 (S502), it is preferable to carry out before separating the base substrate 10 from the interlayer 100 in terms of productivity and cost.

As such, by adhering the two base substrates 10 with the interlayer 100 interposed therebetween, the productivity by one process can be increased by about two times.

After separating the base substrate 10 and the interlayer 100 on which the redistribution circuit 40 is formed (S500), the insulating part 30 is provided on the opposite side of the surface on which the redistribution circuit 40 is formed. Patterned second solder covering the insulating portion 30 on the opposite side of the third etching step (S501) and the base circuit board 10 on which the redistribution circuit 40 is formed in an area except for The method may further include forming a resist layer 52 (S502).

At this time, the third etching step (S501) may be etched in any pattern on the region except the insulating portion 30, as described in the previous embodiment, the insulating portion 30 so that the insulating portion 30 protrudes The area except for) may be etched entirely.

Finally, as shown in FIG. 4A (K) or FIG. 4A (L), the step (S600) of mounting the semiconductor chip 60 on one surface of the base substrate 10 on which the redistribution circuit 40 is formed is performed. It may further include. In the mounting of the semiconductor chip 60, the semiconductor chip 60 may be mounted in a wire bonding type as shown in FIG. 4A (k) when the semiconductor chip 60 is mounted on the base substrate 10 as in the previous embodiment. Alternatively, flip chip bonding type mounting may be performed as shown in FIG. 4A (1).

Third Example

FIG. 5A is a view schematically illustrating a semiconductor package and a method of manufacturing the same according to an embodiment of the present invention in order, and FIG. 5B is a view schematically illustrating a flowchart of the method of manufacturing a semiconductor package according to FIG. 5A.

As shown in FIG. 5B, a semiconductor package and a method of manufacturing the same according to an embodiment of the present invention are largely attached to the conductive base substrate 10 on both sides of the interlayer 100 (S110). Half etching (S210) a region other than a region to be formed as a bump in at least one base substrate 10 attached to 100 (S210), wherein the region selectively removed by half etching is formed of an insulating material. Filling the insulating substrate 30 (S310), separating the base substrate 10 including the interlayer 100 and the insulating portion 30 (S410), and the base substrate including the insulating portion 30 ( And selectively etching the surface opposite to the half-etched surface in FIG. 10 so that the insulating portion 30 is exposed to the outside in accordance with the redistribution circuit pattern (S510).

In addition, in the method of manufacturing the semiconductor package according to the present exemplary embodiment, after the insulating material 30 is formed by filling the insulating material with respect to the region of the base substrate 10 selectively removed by half etching, the insulating portion 30 is formed. When the material covers the base substrate 10, the method may further include removing the insulating material so that the base substrate 10 is exposed to the outside (S311), and etching to form the redistribution circuit 40. After (S510), a third etching is performed in an arbitrary pattern on a surface opposite to the surface on which the redistribution circuit 40 is formed in the base substrate 10 (S511) and the patterning agent is patterned on the outer layer of the redistribution circuit 40. The method may further include forming a patterned second solder resist layer 52 covering an insulating material region on a surface opposite to the surface on which the solder resist layer 51 and / or the redistribution circuit 40 is formed (S512). Finally, a redistribution circuit is provided on the outer layer of the redistribution circuit 40. The method may further include mounting a semiconductor chip on one surface of the formed base substrate 10 (S610).

The method of manufacturing a semiconductor package according to the present exemplary embodiment is similar to the method of manufacturing the semiconductor package according to the second embodiment, and the following description will be mainly focused on other differences with reference to FIG. 5A.

After attaching the conductive base substrate 10 to both surfaces of the interlayer 100 (S110), as shown in FIG. 5A (b), in this embodiment, except for the region to be formed as a bump on the base substrate 10. Half etching is performed on the remaining region (S210). That is, there is a difference in performing half etching instead of completely etching the base substrate 10 to completely penetrate and expose the interlayer 100.

Subsequently, in order to form the redistribution circuit 40, the insulating part 30 is formed by filling the region selectively removed by half etching with an insulating material (S310). However, in this case, when the insulating material covers the base substrate 10, the method may further include removing the insulating material so that the base substrate 10 is exposed to the outside (S311).

As such, in order to form the redistribution circuit 40 on the base substrate 10 including the insulating part 30, the redistribution circuit 40 must be separated from the interlayer 100 (S410).

That is, by half-etching the base substrate 10 according to the present exemplary embodiment, the insulating portion 30 is not exposed to the outside on the surface of the base substrate 10 that contacts the interlayer 100. Therefore, in order to form the redistribution circuit 40, the conductive layer 31 may be formed by etching the conductive layer 31 on the half-etched surface where the insulating part 30 is exposed to the outside, or may be formed by pattern plating. Forming a redistribution circuit 40 by etching without forming a conductive layer 31 on one surface of the base substrate 10 that is in contact with the interlayer 100 that is not exposed to the outside. It is preferable at the point which can reduce.

As an example, as shown in FIG. 5A (f), the redistribution circuit is formed by using the first resist layer 32 formed as a mask, and patterning the first resist layer 32 through exposure and development processes as a mask. By removing the region corresponding to 40 by etching, the redistribution circuit 40 is formed. In this case, the resist layer may be formed on the entire surface of the base substrate 10 to protect the base substrate 10 from etching on one surface of the insulating portion 30 exposed to the outside. When the redistribution circuit 40 is formed by etching as described above, it is not necessary to form the conductive layer 31 through plating or lamination unlike in the previous embodiment.

Thereafter, similarly to the previous embodiment, the third etching may be performed in an arbitrary pattern on the opposite side of the surface of the base substrate 10 on which the redistribution circuit 40 is formed (S511). The entire surface of the base substrate 10 may be etched evenly on the opposite side of the surface of the base substrate 10 on which the redistribution circuit 40 is formed, except for the insulating portion 30.

Similar to the process in the previous embodiment, as shown in FIG. 5A (h), the patterned first solder resist layer 51 and / or the second solder resist layer 52 may be formed (S512). In this case, the second patterned on the surface half-etched on the base substrate 10 including the insulating portion 30 before the base substrate 10 including the interlayer 100 and the insulating portion 30 is separated (S410). The solder resist layer 52 may be formed by a screen printing method or a photo method, but after the redistribution circuit 40 is formed, the first solder resist layer 51 and / or the second solder resist layer 52 may be formed. It is preferable to form This is because when the resist layer is formed for etching for forming the redistribution circuit after the solder resist layer is first formed, there is a possibility that a space is formed between the solder resist layer and the resist layer for etching.

In this case, the first solder resist layer 51 and the second solder resist layer 52 may be formed first, and then, a semiconductor chip (1) may be formed on one surface of the base substrate 10 on which the redistribution circuit 40 is formed. The semiconductor package is completed by mounting 60 (S610).

According to the present exemplary embodiment, the manufacturing of two substrates is performed by one process using the interlayer 100, thereby increasing productivity by about two times and reducing costs in terms of manufacturing cost.

Semiconductor package

6A, 6A, and 6A (c) are diagrams showing a semiconductor chip 60 before mounting of the semiconductor substrate manufactured by the semiconductor manufacturing method described above.

As shown in FIG. 6A (b), the semiconductor package manufactured by the semiconductor manufacturing method described above includes a bump substrate 20 and a bump substrate 20 in which remaining regions other than bumps are selectively removed from the conductive base substrate. Redistribution circuit 40 and redistribution formed on at least one surface of bump substrate 20 including insulating portion 30 and insulating portion 30 filled to penetrate bump substrate 20 in the removed region of the substrate The semiconductor chip 60 is mounted on one surface of the bump substrate 20 on which the circuit is formed.

In this way, the insulating part 30 filled in the bump substrate 20 in which the remaining areas except the bumps are selectively removed from the bump substrate 20 is filled to penetrate the bump substrate 20, and thus, of course, the bump substrate 20 The problem of being electrically connected between the wires of the redistribution circuit 40 formed on at least one surface of the N) is solved.

In this case, when the semiconductor chip 60 is connected to the rewiring circuit 40 of the bump substrate 20 by a wire bonding type method, the redistribution circuit may include the semiconductor chip 60 attached thereto. Insulated from the die pad 41 and the die pad 41, and electrically connected to the semiconductor chip 60 may include a land 42 for transmitting an electrical signal to the outside of the semiconductor package, by a flip chip type method In this case, the redistribution circuit may include a solder pad 43 electrically connected to the semiconductor chip through the solder ball 62 to transmit an electrical signal to the outside of the semiconductor package.

After the semiconductor chip 60 is connected to the redistribution circuit 40, the semiconductor chip 60 may further include an encapsulant 70 formed of an insulating material surrounding the semiconductor chip 60 by molding the semiconductor chip 60. At this time, the encapsulant 70 surrounds the semiconductor chip 60, thereby fixing the position of the semiconductor chip 60 and allowing the semiconductor chip 60 to be protected from external shock. .

In addition, as shown in FIG. 6B (d), the semiconductor package is etched in an arbitrary pattern on portions other than the insulating portion 30 on the opposite side of the bump substrate 20 on which the redistribution circuit 40 is formed. The solder part 80 may further include. As such, the semiconductor chip 60 may transmit an electrical signal to the substrate connected to the outside of the semiconductor package through the solder part 80. When etching in a random pattern as described above, solder paste may be applied to the semiconductor chip 60. When the semiconductor package is mounted on a substrate, the surface contact area between the solder and the bump substrate 20 is widened, thereby securing mechanical or electrical reliability.

However, in this case, as shown in FIG. 6C (c), the solder part 80 may be formed by flatly etching the bump substrate 20 except for the insulating part 30 so that the insulating part 30 protrudes. . At this time, it may further include a patterned solder resist layer applied to the insulating portion 30, in this case, a solder ball (not shown) to the solder portion 80 as a passage for the electrical connection to the semiconductor chip 60 and the semiconductor Electrical signals are sent and received between substrates outside the package.

As described above, even when etching is not performed on the opposite side of the bump substrate 20 on which the redistribution circuit 40 is formed, as shown in FIG. 6A (c), the patterning covering the insulating portion 30 is performed. The solder resist layer may be further included. Even in such a case, an electrical signal is transmitted and received between the semiconductor chip 60 and the substrate outside the semiconductor package as a passage for electrically connecting a solder ball (not shown) to the bump substrate 20 except for the insulating part 30.

Preferred embodiments of the present invention described above are disclosed to solve the technical problem, and those skilled in the art to which the present invention pertains (man skilled in the art) various modifications, changes, additions, etc. within the spirit and scope of the present invention. It will be possible to, and such modifications, changes, etc. will be considered to be within the scope of the following claims.

10: base substrate 20: bump substrate
30: insulation 31: conductive layer
32: first resist layer 33: second resist layer
40: redistribution circuit 41: die pad
42: land 43: solder pads
51: first solder resist layer 52: second solder resist layer
60: semiconductor chip 61: wire
62: solder ball 70: encapsulant
80: solder portion 100: interlayer

Claims (19)

In the semiconductor package manufacturing method having a redistribution circuit on at least one side,
(a) preparing a conductive base substrate;
(b) a first etching step of selectively removing the remaining regions of the base substrate except for the region to be formed as a bump to penetrate the base substrate;
(c) filling an area selectively removed by the first etching in the base substrate with an insulating material to form an insulating part; And
(d) forming a redistribution circuit on at least one surface of the base substrate including the insulating portion;
Semiconductor package manufacturing method comprising a. In the semiconductor package manufacturing method having a redistribution circuit on at least one side,
(a) attaching a conductive base substrate on both sides of the interlayer;
(b) a second etching step of selectively removing the remaining regions of the at least one base substrate attached to the interlayer, except for a region to be formed as a bump, to expose the interlayer;
(c) forming an insulating part by filling an area of the base substrate selectively removed by the second etching with an insulating material;
(d) forming a redistribution circuit on a surface of the base substrate including at least one of the insulating parts, opposite to a surface to which the interlayer is attached; And
(e) separating the base substrate and the interlayer;
Semiconductor package manufacturing method comprising a. 3. The method of claim 2,
The step (b)
And removing the base substrate attached to both sides of the interlayer selectively to expose the interlayer to the remaining regions except for the region to be formed as a bump by one process. 3. The method of claim 2,
The step (d)
And forming a redistribution circuit in a single process with respect to the base substrate including the insulating parts attached to both surfaces of the interlayer. 3. The method according to claim 1 or 2,
The redistribution circuit is formed by a pattern plating method or an etching method. 3. The method according to claim 1 or 2,
Between step (c) and step (d),
If the insulating material covers the base substrate, removing the insulating material so that the base substrate is exposed to the outside;
Method for manufacturing a semiconductor package further comprising. 3. The method of claim 2,
Between step (d) and step (e),
Forming a patterned first solder resist layer on an outer layer of the redistribution circuit;
Method for manufacturing a semiconductor package further comprising. 3. The method according to claim 1 or 2,
The semiconductor package manufacturing method,
Performing a third etching of an area of the base substrate on a surface opposite to the surface on which the redistribution circuit is formed except for the insulation portion in an arbitrary pattern;
Method for manufacturing a semiconductor package further comprising. The method of claim 8,
The third etching step,
And etching the entire area except the insulating part so that the insulating part protrudes. 3. The method according to claim 1 or 2,
The semiconductor package manufacturing method,
Forming a patterned second solder resist layer on the opposite side of the base substrate on which the redistribution circuit is formed;
Method for manufacturing a semiconductor package further comprising. In the semiconductor package manufacturing method having a redistribution circuit on at least one side,
(a) attaching a conductive base substrate on both sides of the interlayer;
(b) half etching a region other than a region to be formed as a bump in at least one of the base substrates attached to the interlayer;
(c) filling the region selectively removed by the half etching with an insulating material to form an insulating portion;
(d) separating the base substrate including the insulation and the interlayer; And
(e) selectively etching the opposite side of the half-etched surface of the base substrate including at least one of the insulating portions so that the insulating portion is exposed to the outside corresponding to the redistribution circuit pattern;
Semiconductor package manufacturing method comprising a. The method according to any one of claims 1, 2 and 11,
The semiconductor package manufacturing method,
Mounting a semiconductor chip on one surface of the base substrate on which the redistribution circuit is formed;
Method for manufacturing a semiconductor package further comprising. A bump substrate in which regions of the conductive base substrate except for bumps are selectively removed;
An insulating portion of an insulating material filled in the removed region of the bump substrate to penetrate the bump substrate;
A redistribution circuit formed on at least one surface of the bump substrate including the insulation portion; And
A semiconductor chip mounted on one surface of the bump substrate on which the redistribution circuit is formed;
≪ / RTI > The method of claim 13,
The redistribution circuit,
A die pad to which the semiconductor chip is attached; And
A land insulated from the die pad and electrically connected to the semiconductor chip;
Semiconductor package comprising a. The method of claim 13,
The redistribution circuit,
A solder pad electrically connected to the semiconductor chip through a solder ball;
Semiconductor package comprising a. The method of claim 13,
An encapsulant of an insulating material surrounding the mounted semiconductor chip;
The semiconductor package further comprises. The method of claim 13,
A solder portion etched in an arbitrary pattern on a portion of the bump substrate other than the insulation portion on a surface opposite to the surface on which the redistribution circuit is formed;
The semiconductor package further comprises. The method of claim 17,
The solder portion is a semiconductor package, characterized in that the entire surface is made of etching. The method of claim 13,
A patterned solder resist layer covering the insulation on an opposite side of the bump substrate on which the redistribution circuit is formed;
The semiconductor package further comprises.

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