KR20130044717A - Wafer level led package and method of fabricating the same - Google Patents

Abstract

A wafer level light emitting diode package and a method of manufacturing the same are disclosed. The light emitting diode package manufacturing method includes forming a plurality of semiconductor stack structures on a first substrate, and forming a plurality of semiconductor stack structures on each semiconductor stack structure such that the first conductive pads and the second conductive pads on neighboring semiconductor stack structures are electrically connected to each other. Forming a first conductive pad connected to the first conductive semiconductor layer and a second conductive pad connected to the second conductive semiconductor layer, and forming a plurality of semiconductor stacked structures on the mount substrate having the first and second through holes. And forming first vias and second vias coupled to the first conductive pads and the second conductive pads through the first through holes and the second through holes.

Description

Wafer level light emitting diode package and method of manufacturing the same {wafer level LED package and measurement of FABRICATING THE SAME}

The present invention relates to a light emitting diode package and a method of manufacturing the same, and more particularly, to a wafer level light emitting diode package and a method of manufacturing the same.

Light-emitting diodes can be made light and short, have the advantages of energy saving and long life. Accordingly, the light emitting diode is used as a back light source of various display devices including a mobile phone, and the light emitting diode package in which the light emitting diode is mounted can implement white light having high color rendering property and is applied to general lighting by replacing white light sources such as fluorescent lamps. It is becoming.

Conventionally, a light emitting diode package is usually formed by mounting an individual light emitting diode chip in a package having lead electrodes, connecting the light emitting diode chip and lead electrodes with a bonding wire, and encapsulating the light emitting diode chip with an encapsulant.

The light emitting diode package manufacturing method according to the prior art handles the light emitting diode chips individually, so that the production of the light emitting diode package in large quantities takes a lot of time and cost, resulting in poor productivity. Furthermore, since the bonding wire is formed again after mounting the LED chip, the LED package manufacturing process is complicated. In addition, since the wire bonding process using the capillary requires a space for moving the capillary, there is a limit to miniaturization of the package size, and it is easy to cause a package defect due to poor bonding or disconnection of the wire.

In addition, as the size of the growth substrate for growing the epitaxial layer is increased from 2 inches to 4 inches and 6 inches, there are thousands of light emitting diode chips manufactured in one growth substrate. Therefore, there is a further demand for manufacturing a light emitting diode package in large quantities quickly using such light emitting diode chips. However, the conventional technology is difficult to meet such a demand.

Accordingly, recently, after forming a plurality of semiconductor stacked structures on a growth substrate and before dividing into individual light emitting diode chips, the plurality of semiconductor stacked structures are bonded to a second substrate by using a solder bonding technique, and the second substrate and A technology for manufacturing a wafer level light emitting diode package by dividing a plurality of semiconductor laminate structures into individual light emitting diode chips is being researched. However, when substrate bonding is performed at a relatively high temperature (for example, 200 ° C. or more), such as solder bonding, a bonding failure is likely to occur due to a difference in thermal expansion coefficient between the growth substrate and the second substrate. Bonding defects caused by high temperature bonding processes will be more severe as the growth substrate size increases.

It is an object of the present invention to provide a wafer level light emitting diode package and a method of manufacturing the same, which can be manufactured by combining a plurality of semiconductor laminate structures and a second substrate using a relatively low temperature process.

Another object of the present invention is to provide a wafer level light emitting diode package capable of stably coupling a semiconductor laminate structure and a second substrate, and a method of manufacturing the same.

According to embodiments of the present invention, a wafer level light emitting diode package is provided. The light emitting diode package includes a mount substrate having a first through hole and a second through hole; A semiconductor stacked structure disposed above the mount substrate and having a first conductive semiconductor layer, a second conductive semiconductor layer, and an active region interposed between the first conductive semiconductor layer and the second conductive semiconductor layer; First and second conductive pads disposed between the mount substrate and the semiconductor stacked structure and connected to the first conductive semiconductor layer and the second conductive semiconductor layer, respectively; An insulating layer insulating the first conductive pad from the second conductive semiconductor layer and the active layer of the semiconductor laminate; First and second vias connected to the first conductive pad and the second conductive pad through the first through hole and the second through hole; And a first lead electrode and a second lead electrode positioned below the mount substrate and electrically connected to the first via and the second via, respectively.

The first and second vias couple a mount substrate and semiconductor stack structures through the through holes. The first and second vias may be formed using a relatively low temperature process, such as electroplating.

The semiconductor laminate structure may have a plurality of holes exposing the first conductive semiconductor layer, and the first conductive pad may be connected to the first conductive semiconductor layer exposed to the plurality of holes. .

In addition, a wavelength converter may be positioned on the semiconductor stacked structure. The wavelength converter may have various shapes. For example, the wavelength converter may have a hemispherical shape, but is not limited thereto and may have a flat top surface.

Furthermore, a transparent resin may be interposed on the wavelength converter or between the wavelength converter and the semiconductor laminate.

In addition, the wavelength converter may have a uniform thickness, but is not limited thereto, and may be thicker near a center region than an edge of the semiconductor laminate.

In some embodiments, a provisional adhesive layer may be positioned between the semiconductor laminate structure and the mount substrate. The provisional adhesive layer can reinforce the adhesion between the semiconductor laminate and the mount substrate, and can prevent moisture from penetrating from the outside.

The first conductive pad and the second conductive pad may be located at the same level. That is, the bottom surface of the first conductive pad and the bottom surface of the second conductive pad may be positioned at the same height from the mount substrate.

The light emitting diode package may further include an ohmic contact layer contacting the second conductivity type semiconductor layer. The insulating layer is interposed between the ohmic contact layer and the first conductive pad to insulate the first conductive pad from the ohmic contact layer, so that the second conductive pad is connected to the ohmic contact layer through an opening of the insulating layer. Can be connected.

The growth substrate may be positioned on the semiconductor stack structure, but is not limited thereto. The growth substrate may be removed.

According to other embodiments of the present invention, a method of manufacturing a wafer level light emitting diode package is provided. In this method, a plurality of semiconductor laminates are formed on a first substrate, wherein each semiconductor laminate has a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and the first conductivity type semiconductor layer and the second conductivity type. An active region interposed between the semiconductor layers; A first conductive pad connected to the first conductive semiconductor layer and a second conductive pad connected to the second conductive semiconductor layer are formed on each of the semiconductor stacked structures; The pads and the second conductive pads are electrically connected to each other; Preparing a mount substrate having first through holes and second through holes aligned to correspond to the plurality of semiconductor stacked structures; Disposing the plurality of semiconductor laminate structures on the mount substrate; Forming first vias and second vias coupled to the first conductive pads and the second conductive pads through the first through holes and the second through holes.

The first vias and the second vias may be formed using electroplating.

The method may further include forming a ring pattern on the edge of the first substrate to electrically connect the first conductive pads and the second conductive pads to each other. First and second conductive pads may be electrically connected by the ring pattern to easily perform electroplating.

Meanwhile, the method may further include forming a wavelength converter on the semiconductor stacked structures. The wavelength converter may be formed thicker near the center area than the edge of each semiconductor laminate.

In some embodiments, a provisional adhesive layer may be formed before disposing the plurality of semiconductor laminate structures on the mount substrate. The provisional adhesive layer pre-bonds the semiconductor stack structures to the mount substrate before forming the first vias and the second vias.

The forming of the plurality of semiconductor stacked structures may include forming a plurality of holes exposing the first conductive semiconductor layer by etching the second conductive semiconductor layer and the active layer. The first conductive pads may be connected to the first conductive semiconductor layer through the plurality of holes.

Further, the method may further include forming an ohmic contact layer on the second conductive semiconductor layer and forming an insulating layer covering the semiconductor stacked structures and the ohmic contact layer before forming the first and second conductive pads. It may further include doing.

The first conductive pads and the second conductive pads may be formed on the insulating layer, and the second conductive pads may be connected to the ohmic contact layer through the insulating layer. The first conductive pads are connected to the first conductive semiconductor layer through an insulating layer in the plurality of holes.

According to the present invention, a plurality of semiconductor laminates and mount substrates can be bonded using a relatively low temperature process, and the semiconductor laminates and mount substrates can be firmly bonded. In addition, according to the present invention, electroplating may be easily performed using the ring patterns and the first and second conductive pads formed on the wafer.

1 to 8 are plan views and cross-sectional views illustrating a method of manufacturing a wafer level light emitting diode package according to an embodiment of the present invention.
9 is a cross-sectional view for describing a method of manufacturing a wafer level LED package according to still another embodiment of the present invention.
10 and 11 are cross-sectional views illustrating a method of manufacturing a wafer level light emitting diode package according to another embodiment of the present invention.
12A through 12C are cross-sectional views illustrating various modified examples of the wafer level LED package of FIGS. 10 and 11.
13 is a plan view for explaining a modification of the first conductive pad and the second conductive pad formed on the wafer.
14 is a plan view for explaining a modification of the semiconductor laminate.
15 to 17 are cross-sectional views illustrating a method of manufacturing a wafer level light emitting diode package according to another embodiment of the present invention.
18 to 20 are cross-sectional views illustrating a method of manufacturing a wafer level light emitting diode package according to another embodiment of the present invention.
21 and 22 are cross-sectional views illustrating a method of manufacturing a wafer level light emitting diode package according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Accordingly, the invention is not limited to the embodiments described below and may be embodied in other forms. In the drawings, widths, lengths, thicknesses, and the like of components may be exaggerated for convenience. Like numbers refer to like elements throughout.

1 to 8 are plan views and cross-sectional views illustrating a method of manufacturing a light emitting diode package according to an embodiment of the present invention.

(Wafer 20 ready)

FIG. 1 is an overall plan view of the wafer 20, FIG. 2 is a partial plan view of FIG. 1, and FIG. 3 is a partial cross sectional view taken along the cut line A-A of FIG.

1 to 3, a wafer 20 in which a plurality of semiconductor stack structures 30 are formed on a first substrate 21 is prepared.

The wafer 20 includes a first substrate 21 and a plurality of semiconductor stacked structures 30 arranged on the first substrate, and further includes an ohmic contact layer 31, an insulating layer 33, and a first substrate 21. The first conductive pad 35a, the second conductive pad 35b, and a buffer layer (not shown) may be included. In addition, the wafer may include a ring pattern 35c. The semiconductor stacked structure 30 may include a first conductive semiconductor layer 25, an active region 27, and a second conductive semiconductor layer 29.

The first substrate 21 may be a growth substrate capable of growing a nitride semiconductor layer, such as sapphire, silicon carbide, spinel, or the like.

The semiconductor stacked structure 30 may be manufactured by a conventional light emitting diode chip manufacturing process. That is, epitaxial layers including the first conductive semiconductor layer 25, the active layer 27, and the second conductive semiconductor layer 29 are grown on the first substrate 21, and the epitaxial layers are patterned to form the epitaxial layers. A plurality of semiconductor laminates 30 are formed on the first substrate 21. The second conductive semiconductor layer 29 and the active layer 27 may also be partially removed to expose a portion of the first conductive semiconductor layer 25. For example, as shown in FIGS. 2 and 3, the second conductive semiconductor layer 29 and the active layer 27 are partially removed to form the first conductive semiconductor layer 25 in each semiconductor laminate structure 30. A plurality of holes 30a exposing may be formed.

The active layer 27 and the first and second conductive semiconductor layers 25 and 29 may be formed of a III-N-based compound semiconductor such as (Al, Ga, In) N semiconductor. The first and second conductivity-type semiconductor layers 25 and 29 may be single layers or multiple layers, respectively. For example, the first conductivity type and / or second conductivity type semiconductor layers 25 and 29 may include a contact layer and a cladding layer, and may also include a superlattice layer. In addition, the active layer 27 may have a single quantum well structure or a multiple quantum well structure. For example, the first conductivity type may be n type, and the second conductivity type may be p type, but is not limited thereto and vice versa. The buffer layer mitigates lattice mismatch between the first substrate 21 and the first conductivity type semiconductor layer 25 to reduce the defect density generated in the semiconductor layers 25, 27, and 29.

An ohmic contact layer 31 is formed on the second conductive semiconductor layer 29 of each semiconductor laminate structure 30. The ohmic contact layer 31 may include a reflective layer such as Ag, and may also include a diffusion barrier layer. The ohmic contact layer 31 may be formed after forming the plurality of holes 30a, but may be formed on the second conductivity-type semiconductor layer 29 before forming the plurality of holes 30a. May be patterned to form the holes 30a of the.

The insulating layer 33 covers the semiconductor stack structures 30. The insulating layer 33 covers sidewalls in the plurality of holes 30a and exposes the first conductivity type semiconductor layer 25 at the bottom of the holes 30a. The insulating layer 33 may also cover side surfaces of the semiconductor stacked structures 30. Meanwhile, the insulating layer 33 has openings that expose the ohmic contact layer. The insulating layer 33 may be formed of, for example, silicon oxide or silicon nitride.

On the other hand, each of the first conductive pad 35a and the second conductive pad 35b is formed on the semiconductor laminate structure 30. The first conductive pad 35a is connected to the first conductive semiconductor layer 25, and the second conductive pad 35b is connected to the second conductive semiconductor layer 29. As illustrated, the first conductive pad 35a may be connected to the first conductive semiconductor layer 25 exposed in the plurality of holes 30a and may be connected to the second conductive semiconductor layer 25 by the insulating layer 33. And the active layer 27 and the ohmic contact layer 31. On the other hand, the second conductive pad 35b is connected to the ohmic contact layer 31 through the opening of the insulating layer 33. The first and second pads 35a and 35b may include, for example, Ti, Cu, Ni, Al, Au, or Cr, and may be formed of two or more of these materials.

The first conductive pad 35a and the second conductive pad 35b are spaced apart from each other on each semiconductor stack. However, as illustrated, the first conductive pads 35a on the neighboring semiconductor stacked structures 30 may be connected to each other, and the second conductive pads 35b may be connected to each other.

Meanwhile, while forming the first and second conductive pads 35a and 35b, a ring pattern 35c may be formed at an edge of the first substrate 21. The ring pattern 35c electrically connects the first and second conductive pads 35a and 35b to each other. The ring pattern 35c may be formed of the same material layer as the first and second conductive pads 35a and 35b.

In the present exemplary embodiment, although the plurality of semiconductor stacked structures 30 are illustrated as being separated from each other on the first substrate 21, the present invention is not limited thereto. For example, the first conductive semiconductor layers 25 may be connected to each other. . However, when the plurality of semiconductor laminates 30 are separated from each other, the insulating layer 33 may cover the entire side surface of the semiconductor laminate 30, so that moisture or the like penetrates into the semiconductor laminate from the outside. Can be effectively prevented.

(Mount substrate 51 ready)

4 shows a plan view of the mount substrate 51, and FIG. 5 shows a partial cross-sectional view of the mount substrate 51.

4 and 5, a mount substrate 51 for joining a plurality of semiconductor stacked structures 30 at the wafer level is prepared. The mount substrate 51 may include first through holes 51a and second through holes 51b and may also include a through pattern 51c.

The first through holes 51a and the second through holes 51b are formed on the semiconductor stacked structure 30 to correspond to the first and second conductive pads 35a and 35b. At least one first through hole 51a and at least one second through hole 51b are formed corresponding to each semiconductor stack 30.

The mount substrate 51 may be an insulating substrate or a substrate in which an oxide film or an insulating film is formed on the surface of the conductive substrate. For example, the mount substrate 51 may be an organic substrate such as FR4, or an AlN, alumina substrate, low temperature or high temperature cofired ceramic substrate, Si substrate, SiC substrate, metal substrate, or the like. When the mount substrate 51 is a conductive substrate such as Si or a metal substrate, an oxide film or an insulating film is formed to insulate the surface.

On the other hand, the through pattern 51c exposes the ring pattern 35c on the wafer 20 when the mount substrate 51 and the wafer 20 are aligned so that the external power source can be connected. The through pattern 51c may be formed in a notch shape at the edge of the mount substrate 51 as illustrated, but is not limited thereto. Furthermore, when the overall size of the mount substrate 51 is made smaller than the overall size of the wafer 20, the through pattern 51c can be omitted.

(Combination of Wafer 20 and Mount Substrate 51)

6 to 8 are cross-sectional views illustrating a method of manufacturing a wafer level LED package by aligning the wafer 20 and the mount substrate 51.

Referring to FIG. 6, the provisional adhesive layer 40 may be formed on the first substrate 21 on which the semiconductor stack structures 30 are formed. The temporary adhesive layer 40 may be formed using, for example, spin coat, dispensing, chemical vapor deposition, physical vapor deposition, or screen printing technology, and the first conductive pad 35a and the second conductive pad 35b. It can be patterned to have openings exposing it. The temporary adhesive layer 40 may be formed of a thermosetting resin or a thermoplastic resin, and may be used as an adhesive layer for preliminarily bonding the wafer 20 and the mounting substrate 51.

In addition, a plurality of semiconductor laminate structures 30 on the first substrate 21 are disposed on the mount substrate 50 so as to face the mount substrate 51.

Referring to FIG. 7, the first conductive pad 35a and the second conductive pad 35b are aligned to be positioned on the first through hole 51a and the second through hole 51b, respectively, and the temporary adhesive layer 40 is disposed. ) Pre-bonds the wafer 20 with the mount substrate 51.

Subsequently, the first vias 53a and the second vias 53b are formed in the first and second through holes 51a and 51b of the mount substrate 51 using the electroplating technique. For example, a combination of the mount substrate 51 and the wafer 20 may be plated in a plating bath. In particular, electroplating may be performed by connecting a power supply to the ring patch 35c on the wafer 20. Accordingly, plating is started from the first conductive pad 35a and the second conductive pad 35b exposed through the first and second through holes 51a and 51b, thereby closing the through holes 51a and 51b. And thus, the first vias 53a and the second vias 53b are formed. The first vias 53a and the second vias 53b extend below the bottom surface of the mount substrate 51 to form first and second lead electrodes 55a and 55b.

The first vias 53a and the second vias 53b are formed together through the same process, and thus may be formed of the same material, for example, a solder such as AuSn. The first vias 53a and the second vias 53b join the mount substrate 51 and the first and second conductive pads 35a and 35b to structurally and electrically connect the semiconductor stack 30. It is connected to the mounting board 51.

The plating technique may be performed in a low temperature process of 100 ° C. or less, and thus, a problem of poor bonding due to a difference in thermal expansion coefficient between the first substrate 21 and the mount substrate 51 may be solved.

Referring to FIG. 8, the first and second substrates 21 and 51 may be cut to complete individual LED packages. The first substrate 21 and the mount substrate 51 may be divided by scribing, breaking, sawing, or may be divided using a laser. The light emitting diode package emits light through the first substrate 21. Meanwhile, a wavelength converter (not shown) may be formed first on the first substrate 21 before cutting the first substrate 21. The formation of the wavelength converter will be clarified by the embodiments described below.

9 is a cross-sectional view for describing a method of manufacturing a wafer level LED package according to still another embodiment of the present invention.

Referring to FIG. 9, as described above with reference to FIG. 7, first vias 53a and second vias 53b are formed. Thereafter, the first substrate 21 is removed from the semiconductor laminate 30. Subsequently, the development substrate LED package is completed by cutting the mount substrate 51. In addition, a roughened surface (not shown) may be formed on the exposed first conductive semiconductor layer 25.

10 and 11 are cross-sectional views illustrating a method of manufacturing a wafer level light emitting diode package according to another embodiment of the present invention.

Referring to FIG. 10, after the first substrate 21 is removed as described with reference to FIG. 9, the wavelength converter 60 is formed on the exposed first conductive semiconductor layer 25. The wavelength converter 60 may be formed by coating a phosphor or by coating a resin containing the phosphor. For example, a resin containing phosphors may be applied to the exposed first conductive semiconductor layer 27 surface, and the wavelength converter 60 may be formed to a uniform thickness by using a squeeze. Alternatively, it may be formed by attaching a wavelength converter containing a phosphor, for example, glass.

Referring to FIG. 11, the light emitting diode package is completed by dividing the mount substrate 51.

According to the present embodiment, the wavelength converter 60 in direct contact with the first conductivity type semiconductor layer 27 is formed. However, the wavelength converter 60 according to the present embodiment may also be applied to the manufacture of the LED package of FIG. 8, so that the wavelength converter 60 may be formed on the first substrate 21.

Also, various modifications are possible as shown in FIGS. 12A, 12B and 12C. For example, as shown in FIG. 12A, a transparent resin 61 may be formed on the wavelength converter 60. The transparent resin 61 may protect the wavelength converter 60 from moisture and the like, and may have a convex lens shape such as a hemispherical shape. In addition, as shown in FIG. 12B, the wavelength converter 60a may be formed to have a convex lens shape such as a hemispherical shape. Furthermore. A convex transparent resin 62 is formed first, and a wavelength converter 60b may be formed thereon. The wavelength converter 60b may be thicker in the center region than the outer side of the semiconductor stack 30. Therefore, when the amount of light emitted from the semiconductor laminate structure varies depending on the position, it is possible to achieve uniform color conversion by adjusting the thickness of the wavelength converter 60b.

13 is a plan view for explaining a modification of the first conductive pad and the second conductive pad formed on the wafer.

Referring to FIG. 13, the wafer 20 described with reference to FIGS. 1 and 2 has been described as having the first conductive pad 35a and the second conductive pad 35b separated from each other. In this case, the first conductive pad 35a on one semiconductor stacked structure 30 and the second conductive pad 35b on the adjacent semiconductor stacked structure 30 are connected to each other.

The semiconductor stacked structures 30 are finally divided into individual light emitting diode packages, so that the first conductive pad 35a and the second conductive pad 35b connected to each other are separated from each other in the dividing process.

According to the present embodiment, the first conductive pad 35a and the second conductive pad 35b respectively cover the side surfaces of the semiconductor stacked structure 30, and these conductive pads 35a and 35b are shown in FIG. 3 above. The insulating layer 33 may be insulated from the side surface of the semiconductor stacked structure 30.

14 is a plan view for explaining a modification of the semiconductor laminate.

2 and 3 have a plurality of holes 30a exposing the first conductive semiconductor layer 25. In contrast, in the present embodiment, instead of the plurality of holes 30a, the partial region 30b near the edge of the first conductivity-type semiconductor layer 25 is exposed in a form similar to a horizontal light emitting diode. The first conductive pad 35a is connected to the exposed first conductive semiconductor layer 25 in the partial region 30b and covers the upper portion of the second conductive semiconductor layer 29.

The first conductive pad 35a and the first conductive semiconductor layer 25 may be connected in various forms. In addition, at least a portion of the first conductive pad 35a may be positioned at the same level as the second conductive pad 35b.

15 to 17 are cross-sectional views illustrating a method of manufacturing a wafer level light emitting diode package according to another embodiment of the present invention. In the present embodiment, a method of separately forming the first and second vias 53a and 53b and the lead electrodes 55a and 55b will be described.

Referring to FIG. 15, as described above with reference to FIG. 7, first vias 53a and second vias 53b are formed through a plating process. In this case, the first and second vias 53a and 53b may be formed for a sufficient time, and thus a relatively thick plating layer may be formed on the lower surface of the mount substrate 51.

Referring to FIG. 16, the plating layer formed under the mount substrate 51 is removed. The plating layer may be removed using polishing, lapping, CMP, or the like until the bottom surface of the mount substrate 51 is exposed. While removing the plating layer, a part of the mount substrate 51 may also be removed to thin the mount substrate 51.

Referring to FIG. 17, first lead electrodes 55a and second lead electrodes 55b are formed on the bottom surface of the mount substrate 51. The first lead electrodes 55a are electrically connected to each other by covering the first vias 53a, and the second lead electrodes 55b are electrically connected to each other by covering the second vias 53b. The light emitting diode package may then be divided into individual light emitting diode packages.

According to the present embodiment, when it is difficult to uniformly form the lead electrodes 55a and 55b by the plating process for forming the first and second vias 53a and 53b, the first and second vias ( By separating the plating process of forming 53a and 53b from the process of forming lead electrodes 55a and 55b, the lead electrodes 55a and 55b may be formed flat and uniformly.

18 to 20 are cross-sectional views illustrating a method of manufacturing a wafer level light emitting diode package according to another embodiment of the present invention. Also in this embodiment, a method of separately forming the first and second vias 53a and 53b and the lead electrodes 55a and 55b will be described.

Referring to FIG. 18, as described above with reference to FIG. 7, first vias 53a and second vias 53b are formed through a plating process. In this case, the first and second vias 53a and 53b partially fill the through holes 51a and 51b of the mount substrate 51 without sufficiently filling them.

Referring to FIG. 19, the surface of the mount substrate 51 may be polished, wrapped, CMP, or the like until the first and second vias 53a and 53b in the through holes 51a and 51b are exposed. Remove it partially. While removing the mount substrate 51, some of the first and second vias 53a and 53b may also be removed.

Referring to FIG. 20, first lead electrodes 55a and second lead electrodes 55b are formed on the bottom surface of the mount substrate 51. The first lead electrodes 55a are electrically connected to each other by covering the first vias 53a, and the second lead electrodes 55b are electrically connected to each other by covering the second vias 53b. The light emitting diode package may then be divided into individual light emitting diode packages.

According to the present exemplary embodiment, in the case where it is difficult to uniformly form the lead electrodes 55a and 55b by the plating process for forming the first and second vias 53a and 53b, the plating process and the lead electrodes 55a are performed. The process of forming the 55b may be separated to form the lead electrodes 55a and 55b flat and uniformly.

21 and 22 are cross-sectional views illustrating a method of manufacturing a wafer level light emitting diode package according to another embodiment of the present invention.

Referring to FIG. 21, in the above-described embodiments, the provisional adhesive layer 40 is used to temporarily attach the wafer 20 and the mount substrate 51. However, in this embodiment, the provisional adhesive layer 40 is omitted. The first conductive pad 35a and the second conductive pad 35b are brought into close contact with the surface of the mount substrate 51, and the wafer 20 and the mount substrate 51 are held by clamping means such as a jig (not shown). Fix the position. Thereafter, the first via 53a and the second via 53b are formed through the plating process, and then the mount substrate 51 is cut to complete the individual LED package shown in FIG. 22. do.

According to the present exemplary embodiment, the mount substrate 51 and the first and second conductive pads 35a and 35b are in close contact with each other, and the first and second vias 53a and 53b are connected to the mount substrate 51 and the first. And a package for coupling the second conductive pads 35a and 35b.

While various embodiments have been described above, it should be understood that the matters described and limited to the specific embodiments may be applied to other embodiments without changing the spirit of the present invention. In addition, the present invention is not limited to the above-described embodiments, and various modifications and changes may be made without departing from the spirit of the present invention.

Claims (21)

A mount substrate having a first through hole and a second through hole;
A semiconductor stacked structure disposed above the mount substrate and having a first conductive semiconductor layer, a second conductive semiconductor layer, and an active region interposed between the first conductive semiconductor layer and the second conductive semiconductor layer;
First and second conductive pads disposed between the mount substrate and the semiconductor stacked structure and connected to the first conductive semiconductor layer and the second conductive semiconductor layer, respectively;
An insulating layer insulating the first conductive pad from the second conductive semiconductor layer and the active layer of the semiconductor laminate;
First and second vias connected to the first conductive pad and the second conductive pad through the first through hole and the second through hole; And
And a first lead electrode and a second lead electrode disposed under the mount substrate and electrically connected to the first via and the second via, respectively. The method according to claim 1,
The semiconductor laminate has a plurality of holes exposing the first conductivity type semiconductor layer,
And the first conductive pad is connected to the first conductive semiconductor layer exposed to the plurality of holes. The method according to claim 1,
A wafer level light emitting diode package further comprising a wavelength converter positioned on the semiconductor stacked structure. The method according to claim 3,
The wavelength converter has a hemispherical shape wafer level light emitting diode package. The method according to claim 3,
The wafer level light emitting diode package further comprises a transparent resin interposed between the wavelength converter and the semiconductor laminate. The method according to claim 5,
And the wavelength converter is thicker near the center region than the edge of the semiconductor stack. The method according to claim 1,
And a provisional adhesive layer disposed between the semiconductor laminate structure and the mount substrate. The method according to claim 1,
The first conductive pad and the second conductive pad are at the same level, the wafer level light emitting diode package. The method according to claim 8,
An ohmic contact layer contacting the second conductivity type semiconductor layer,
The insulating layer is interposed between the ohmic contact layer and the first conductive pad to insulate the first conductive pad from the ohmic contact layer,
And the second conductive pad is connected to the ohmic contact layer through an opening of the insulating layer. The method according to claim 1,
A wafer level light emitting diode package further comprising a growth substrate positioned on the semiconductor stacked structure. A plurality of semiconductor stacked structures are formed on a first substrate, wherein each semiconductor stacked structure is formed between a first conductive semiconductor layer, a second conductive semiconductor layer, and the first conductive semiconductor layer and the second conductive semiconductor layer. Including an intervening active region,
A first conductive pad connected to the first conductive semiconductor layer and a second conductive pad connected to the second conductive semiconductor layer are formed on each of the semiconductor stacked structures; The pads and the second conductive pads are electrically connected to each other,
Preparing a mount substrate having first through holes and second through holes aligned to correspond to the plurality of semiconductor stacked structures,
Disposing the plurality of semiconductor laminate structures on the mount substrate,
And forming first vias and second vias coupled to the first conductive pads and the second conductive pads through the first through holes and the second through holes. The method of claim 11,
And the first vias and the second vias are formed using electroplating. The method of claim 11,
And forming a ring pattern on the edge of the first substrate to electrically connect the first conductive pads and the second conductive pads to each other. The method according to claim 13,
The ring pattern is formed with the first and second conductive patterns. The method of claim 11,
And removing the first substrate after forming the first and second via holes. The method of claim 11,
And forming a wavelength converter on the semiconductor stacked structures. 18. The method of claim 16,
And the wavelength converter is thicker near the center region than the edge of each semiconductor laminate. The method of claim 11,
And forming the temporary adhesive layer before disposing the plurality of semiconductor laminate structures on the mount substrate. The method of claim 11,
Forming the plurality of semiconductor laminate structures,
Etching the second conductive semiconductor layer and the active layer to form a plurality of holes exposing the first conductive semiconductor layer;
The first conductive pads are connected to the first conductive semiconductor layer through the plurality of holes. The method of claim 19,
Before forming the first and second conductive pads,
Forming an ohmic contact layer on the second conductivity type semiconductor layer,
And forming an insulating layer covering the semiconductor stacked structures and the ohmic contact layer. The method of claim 20,
The first conductive pads and the second conductive pads are formed on the insulating layer,
The second conductive pads are connected to the ohmic contact layer through the insulating layer.

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