KR20120074913A - Method of fabricating array substrate for bistable chiral splay nematic mode liquid crystal display device - Google Patents

Abstract

PURPOSE: A method for manufacturing an array panel for a BSCN(Bistable Chiral Splay Nematic) mode liquid crystal display device is provided to simplify processes by a mask process six or seven times. CONSTITUTION: Gate and data lines(130) and a thin film transistor are formed. A first passivation layer(140) is formed on the thin film transistor. A first electrode(155) is formed on the first passivation layer. A second passivation layer(145) is formed on a frontal side of a substrate on the first electrode. Second and third electrodes(165,168) are formed on the second passivation layer. The second and third electrodes penetrate each pixel area.

Description

Method of fabricating array substrate for bistable chiral splay nematic mode liquid crystal display device

The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing an array substrate for a bistable chiral splay nematic (BCSN) liquid crystal display device capable of switching between a memory mode and a dynamic mode.

Recently, as the information society has developed rapidly, the necessity of a display device having excellent characteristics such as thinning, light weight, and low power consumption has emerged. Accordingly, development of flat panel displays has been actively conducted. In particular, liquid crystal displays are excellent in resolution, color display, image quality, and the like, and are being actively applied to monitors of notebook computers and desktop computers.

In general, a liquid crystal display device arranges two substrates on which electrodes are formed so that the surfaces on which the two electrodes are formed face each other, injects a liquid crystal material between the two substrates, and applies a voltage to the two electrodes to generate an electric field. By moving the liquid crystal molecules, the image is expressed by the transmittance of light that varies accordingly.

In more detail, the structure thereof will be described with reference to FIG. 1, which is an exploded perspective view of a general liquid crystal display. As shown, the liquid crystal display includes an array substrate 10 and a color filter with a liquid crystal layer 30 therebetween. The substrate 20 has a configuration in which the substrates are face-to-face bonded to each other. The array substrate 10 of the lower part of the plurality of gate wirings 14 is vertically and horizontally arranged on the upper surface of the transparent substrate 12 to define a plurality of pixel regions P. And a data line 16, and a thin film transistor T is provided at an intersection point of the two lines 14 and 16 so as to be connected one-to-one with the pixel electrode 18 provided in each pixel region P. FIG.

In addition, the upper color filter substrate 20 facing the array substrate 10 is a rear surface of the transparent substrate 22 and non-display of the gate wiring 14, the data wiring 16, and the thin film transistor Tr. A grid-like black matrix 25 is formed around the pixel region P so as to cover the region, and red (R) and green are sequentially arranged in order to correspond to the pixel region (P) in the grid. A color filter layer 26 including (G) and blue (B) color filter patterns 26a, 26b, and 26c is formed, and is transparent over the entire surface of the black matrix 25 and the color filter layer 26. The common electrode 28 is provided.

Although not shown in the drawings, each of the two substrates 10 and 20 is sealed with a sealant or the like along the edge to prevent leakage of the liquid crystal layer 30 interposed therebetween. 10 and 20 are interposed between the upper and lower alignment layers that provide reliability in the molecular alignment direction of the liquid crystal at the boundary between the liquid crystal layer 30 and the polarization axes perpendicular to each other on the outer surfaces of the substrates 10 and 20. Each of the first and second polarizing plates is provided.

In addition, a back-light is provided on the outer surface of the array substrate 10 to supply light, so that the on / off signal of the thin film transistor Tr is supplied to the gate wiring 14. When the image signal of the data wiring 16 is transferred to the pixel electrode 18 of the selected pixel region P by being sequentially scanned and applied, the liquid crystal molecules are driven by the vertical electric field therebetween, and thus the transmittance of light We can display various images by change

In such a liquid crystal display device, liquid crystals that are frequently used are of the nematic type, smectic type, and cholesteric type. Among the liquid crystals described above, the arrangement of the liquid crystals may be disturbed. In this case, nematic liquid crystals having the property of scattering the light most are used the most.

The electro-optic effect of liquid crystals refers to the phenomenon in which the optical properties of a liquid crystal cell change, resulting in electrical optical modulation, which is caused by the change of liquid crystal molecules from one array state to another by application of an electric field. .

In the liquid crystal display device applying the nematic liquid crystal, the molecular arrangement is continuously changed when the electric field is applied to the nematic liquid crystal, and thus, the TN mode and the in-plane switching mode are most commonly used. ) Type is mainly used.

In the TN mode type, the panel is configured to have an angle of 90 degrees on each of the transparent electrodes oriented so that the major axis of the liquid crystal molecules are parallel to the electrode surface, and the nematic liquid crystal is interposed therebetween from the one electrode. It has an array state twisted 90 degrees continuously in the longitudinal axis direction of the molecule toward the electrode surface of, and uses such a liquid crystal structure.

In the in-plane switching mode, the common electrode and the pixel electrode are arranged on the same substrate, and the viewing angle characteristic is improved compared to the TN mode by rotating the liquid crystal molecules by the transverse electric field.

Meanwhile, recently, various types of display devices have been introduced to satisfy rapidly changing consumer demands. In particular, various products are being introduced for light weight, thinness, and energy efficiency due to the advancement and portability of information usage environment. These products are intended to include various functions such as watching video and e-book.

In line with this trend, dual mode is available, allowing both dynamic mode for video viewing and memory mode to minimize power consumption and act as e-book or e-paper. There is a need for a liquid crystal display device. In order to cope with this, reflective chistle splay nematic (BCSN) mode liquid crystal displays have been developed.

In such a BCSN (Bistable Chiral Splay Nematic) liquid crystal display, the memory mode that operates with the minimum power consumption utilizes bistable stability on the splay and π-twist phases, and is optimized for dynamic viewing of video and the like. Mode uses switching between a low bend phase and a high bend phase.

On the other hand, the BCSN (bistable chiral splay nematic) liquid crystal display device for driving such a driving is increasing the number of mask processes for patterning compared to manufacturing a conventional transmissive liquid crystal display device.

That is, in the case of the array substrate of the conventional BCSN (Bistable chiral splay nematic) liquid crystal display device, the gate electrode / semiconductor layer and the source and drain electrode / emboss structure first protective layer / reflective plate / planarization layer / second protective layer / plate A total of nine mask processes are required to form the second and third electrodes for implementing the first electrode / third protective layer / lateral electric field.

A mask process means a photolithography process, and after forming a material layer for patterning on a substrate, forming a photoresist layer having photosensitive characteristics thereon, and using an exposure mask having a light transmitting region and a blocking region. A series of complex unit processes, such as exposure, development of the exposed photoresist layer, etching of the material layer using the developed photoresist pattern, stripping of the photoresist pattern, and the like.

In order to process a single mask process, a unit process equipment for each unit process and a material for each unit process are required, and each process process time through each unit process equipment is required.

Therefore, the array substrate for the BCSN (Bistable Chiral Splay Nematic) liquid crystal display device manufactured through such a complicated process needs to reduce the mask process in order to reduce the manufacturing cost and improve productivity.

Accordingly, in order to solve the above-mentioned problems, the present invention provides a bistable chiral splay nematic (BCSN) mode liquid crystal display which can reduce the number of mask processes, simplify the manufacturing process, reduce the manufacturing time, and improve productivity. It is an object of the present invention to provide a method for producing an array substrate for use.

In order to achieve the above object, a method of manufacturing an array substrate for a bistable chiral splay nematic (BCSN) mode liquid crystal display device according to the present invention includes a display area having a plurality of pixel areas and a substrate having a non-display area defined outside thereof. Forming a gate and data wiring crossing the display area on the display area to define the pixel area, and forming a thin film transistor connected to the gate and data wire in the pixel area; Forming a first protective layer having a first contact hole in the display area over the thin film transistor and exposing a drain electrode of the thin film transistor and having a flat surface as an organic insulating material; Forming a plate-shaped first electrode in contact with the drain electrode of the thin film transistor through the first contact hole in the pixel area over the first passivation layer and serving as a reflector; Forming a second protective layer over the first electrode over the first electrode; Forming second and third electrodes penetrating each pixel region and spaced apart from each other in parallel with each other over the second passivation layer.

Forming a third protective layer of an inorganic insulating material on the entire surface of the substrate over the thin film transistor before forming the first protective layer; Before forming the first electrode, a fourth passivation layer is formed on the entire surface of the substrate over the first passivation layer using an inorganic insulating material, and the fourth passivation layer and the third passivation layer are patterned to form the fourth passivation layer. Exposing the drain electrode of the thin film transistor.

In addition, the first electrode may be formed of aluminum (Al) or aluminum alloy (AlNd), which is a metal material having excellent reflectance.

The forming of the gate and the data line and the thin film transistor may include forming the gate line extending in one direction at a boundary of each pixel region, and forming the gate electrode connected to the gate line in each pixel region. Steps; Forming a gate insulating film as an inorganic insulating material over the gate wiring and the gate electrode; Forming a data line on the gate insulating layer to cross the gate line to define the pixel area, a semiconductor layer formed thereon to correspond to the gate electrode, and a source electrode connected to the data line above the semiconductor layer; Forming the drain electrode spaced apart therefrom.

In this case, the forming of the gate wiring may include forming a common wiring having a shape passing through each pixel region in the display area and a gate pad electrode connected to one end of the gate wiring in the non-display area. The forming of the data line may include forming a gate pad electrode connected to one end of the data line in the non-display area.

The forming of the second passivation layer may include patterning the second passivation layer, the first passivation layer, and the gate insulating layer to form a gate pad contact hole and the data pad electrode exposing the gate pad electrode. The data pad contact hole to be exposed is formed.

The forming of the second and third electrodes may include an auxiliary gate pad electrode contacting the gate pad electrode through the gate pad contact hole, and auxiliary data contacting the data pad electrode through the data pad contact hole. Forming a pad electrode.

The common wiring may be configured such that the drain electrode overlaps the common wiring and its ends so that the common wiring, the gate insulating layer, and the drain electrode overlap each other to form a storage capacitor.

The forming of the second and third electrodes may include forming a first auxiliary line connecting the end of the second electrode and a second auxiliary line connecting the end of the second electrode to the non-display area. Steps.

As described above, an array substrate for a bistable chiral splay nematic (BCSN) mode liquid crystal display according to an exemplary embodiment of the present invention is manufactured by a total of seven or six mask processes, and thus, compared with a conventional manufacturing method of performing nine mask processes. Since the mask process may be omitted twice or three times, the process is simplified and thereby the productivity per unit time is improved.

1 is an exploded perspective view of a general liquid crystal display device.
2A to 2F are plan views illustrating manufacturing steps of an array substrate for a BCSN mode liquid crystal display according to an exemplary embodiment of the present invention.
3A to 3H are cross-sectional views illustrating manufacturing steps of an array substrate for a BCSN mode liquid crystal display according to an exemplary embodiment of the present invention.

Hereinafter, a method of manufacturing an array substrate for a BCSN mode liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2F are plan views illustrating manufacturing steps of an array substrate for a BCSN mode liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 3A to 3H illustrate an array substrate for a BCSN mode liquid crystal display according to an exemplary embodiment of the present invention. As a step-by-step process cross-sectional view, one pixel area, a gate, and a data pad part are shown. In this case, for convenience of description, an area in which the thin film transistor Tr as the switching element is formed in each pixel area P is defined as a switching area TrA and an area in which the storage capacitor StgC is formed as a storage area StgA. do.

First, as shown in FIGS. 2A and 3A, a metal material such as aluminum (Al), aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), or the like may be formed on a transparent insulating substrate 101. One or more materials of molybdenum alloy (MoTi) and chromium (Cr) are deposited on the front surface to form a first metal layer (not shown).

Thereafter, the first metal layer (not shown) is coated with a photoresist, exposure using a photo mask, development of the exposed photoresist, etching of the first metal layer (not shown), and a strip of photoresist. By patterning by performing a mask process including a unit process of, a gate wiring 103 having a single layer or multilayer structure and extending in a first direction is formed, and at the same time, the gate wiring 103 is formed in the switching region TrA. And a gate electrode 108 connected to the gate electrode 108.

In addition, a common wiring 106 extending in parallel with the gate wiring 103 is formed. In this case, the common wiring 106 penetrates through the storage area StgA, and the portion corresponding to the storage area StgA forms a width larger than that of other areas to form the first storage electrode 109.

In addition, a gate pad electrode 109 connected to the gate line 103 and having a single layer or a multilayer structure is formed in the gate pad part GPA.

Next, as shown in FIGS. 2B and 3B, an inorganic insulating layer is formed on the gate wiring 103, the gate electrode 108, the common wiring 106, and the first storage electrode 109 and the gate pad electrode 109. A material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited to form a gate insulating film 115 over the substrate 101.

Subsequently, a pure amorphous silicon layer (not shown) and an impurity amorphous silicon layer (not shown) are formed on the gate insulating layer 115, and a metal material such as aluminum (Al) is formed on the impurity amorphous silicon layer (not shown). , Depositing one or more materials of aluminum alloy (AlNd), copper (Cu), copper alloy, molybdenum (Mo), molybdenum alloy (MoTi) and chromium (Cr) to form a second metal layer (not shown) do.

Thereafter, a photoresist layer (not shown) is formed on the second metal layer (not shown), and the first photoresist pattern (not shown) having the first thickness and the first thickness are formed by performing halftone exposure or diffraction exposure and developing the photoresist layer. A second photoresist pattern (not shown) having a second thickness thinner than one thickness is formed.

In this case, the first photoresist pattern (not shown) may include the source and drain electrodes (133 and 136 of FIG. 2H), the data wiring (130 of FIG. 3F), the second storage electrode (137 of FIG. 2H), and the data pad electrode. 2H is formed to correspond to a portion to be formed, and the second photoresist pattern (not shown) is formed to correspond to a spaced area between the source and drain electrodes 133 and 136 of FIG. 2H.

Subsequently, the gate insulating layer may be removed by etching and removing the second metal layer (not shown) and impurities and lower pure silicon layers (not shown) exposed to the outside of the first and second photoresist patterns (not shown). A data line 130 is formed on the 115 to cross the gate line 103 and extend in a second direction to define a plurality of pixel regions P. Referring to FIG.

At the same time, a source drain pattern (not shown) connected to the data line 130 and an impurity amorphous silicon pattern (not shown) and pure amorphous silicon sequentially stacked below the data region 130 in the switching region TrA and the storage region StgA. The active layer 120a is formed.

In addition, a data pad electrode 131 connected to the data line 130 is formed in the data pad part GPA.

In this case, the first pattern 121a of pure amorphous silicon and the impurity amorphous silicon may be formed on the lower portion of the data line 130 and the data pad electrode 131 based on the gate insulating layer 115 based on the progress of the manufacturing process. A dummy pattern 121 formed of two patterns 121b is formed.

Next, ashing is performed to remove the second photoresist pattern (not shown) having the second thickness.

Subsequently, the source and drain electrodes 133 spaced apart from each other in the switching region TrA by removing the second photoresist pattern (not shown) by etching and removing a central portion of the source drain pattern (not shown) newly exposed. 136 and a second storage electrode 137 connected to the drain electrode 136 are formed in the storage region StgA.

Subsequently, the impurity amorphous silicon pattern (not shown) exposed between the source and drain electrodes 133 and 136 is continuously removed by dry etching, thereby spaced apart from each other under the source and drain electrodes 133 and 136. An ohmic contact layer 120b exposing the active layer 120a is formed. In this case, the active layer 120a and the ohmic contact layer 120b form the semiconductor layer 120.

In this process, the gate electrode 108, the gate insulating layer 115, the semiconductor layer 120, and the source and drain electrodes 133 and 136 spaced apart from each other are sequentially stacked in the switching region TrA. (Tr).

In addition, the drain electrode 136 extends in the storage region StgA to form a second storage electrode 137, and the first storage electrode 109, the gate insulating layer 115, and the second storage overlap each other. The electrode 137 forms a storage capacitor.

Thereafter, a strip is formed to form a first photoresist pattern remaining on the source and drain electrodes 133 and 136, the second storage electrode 137, the data line 130, and the data pad electrode 131. Not shown).

Next, as illustrated in FIGS. 2C and 3C, an inorganic insulating material, for example, silicon oxide, is formed on the entire surface of the thin film transistor Tr, the data line 130, the storage capacitor StgC, and the data pad electrode 131. The first protective layer 140 is formed on the entire surface of the substrate by depositing (SiO ₂ ) or silicon nitride (SiNx).

Next, as shown in FIGS. 2C and 3D, the gate is formed by applying and patterning an organic insulating material, such as benzocyclobutene (BCB) or photoacryl, on the first protective layer 140. In the non-display area including the pad part GPA and the data pad part DPA, a second protective layer 145 is formed to have a flat surface corresponding to the display area.

In this case, when the second protective layer 145 is patterned, the first protective layer 140 made of an inorganic insulating material is removed to correspond to a central portion of the second storage electrode 131 connected to the drain electrode in each pixel area. The first contact hole 146 exposing the gap is formed.

Next, as shown in FIGS. 2D and 3E, an inorganic insulating material, for example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx), is deposited on the second protective layer 145 to form an entire surface of the substrate 101. The third storage layer 148 is formed, and the second storage electrode is formed in each pixel region P by patterning the first protective layer 140 disposed below and corresponding to the first contact hole 146. A drain contact hole 149 exposing 137 is formed.

In this case, the drain contact hole 149 penetrates through the first contact hole 146 exposing the first protective layer 140 provided in the second protective layer 145.

Since the first passivation layer 140 and the third passivation layer 148 are made of an inorganic insulating material and can be continuously removed through dry etching, the first passivation layer 140 may be separately formed on the second storage electrode 131. ) Does not form a contact hole to expose.

Next, as shown in FIGS. 2E and 3F, a third metal layer (not shown) is deposited on the third protective layer 148 by depositing aluminum (Al) or aluminum alloy (AlNd) as an example of a metal material having excellent first reflectance. The second storage electrode 137 is connected to the drain electrode 136 of the thin film transistor Tr through the drain contact hole 149 in each pixel region P by patterning the mask process. The first electrode 155 in the form of a plate in contact with the electrode is formed.

In this case, the first electrode 155 is a metal having excellent reflectance, and the edge of the first electrode 155 overlaps the gate and the data lines 103 and 130 to correspond to each pixel area P on the front of the display area. At the same time, it serves as an electrode.

On the other hand, in the embodiment of the present invention is shown as an example that the first, second, third protective layer (140, 145, 148) is formed, as a modification, the first and third protective layer made of an inorganic insulating material 140 and 148 may be omitted. In this case, since the third protective layer 148 requiring patterning is omitted, one time mask process can be reduced compared to the exemplary embodiment of the present invention.

Since the first protective layer 140 made of an inorganic insulating material is in contact with the active layer 120a, the characteristics of channel contamination and thin film transistor (Tr) that may occur when the organic insulating material is in contact with the active layer 120a. The third protective layer 148 is formed to prevent degradation, and the third protective layer 148 made of an inorganic insulating material is formed of an organic material and the first electrode 155 made of a metal material to solve the problem of weakening of the bonding strength between the organic insulating material and the metal material. It is formed between the second protective layer 145 made of an insulating material.

Next, as shown in FIGS. 2F and 3G, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the front surface of the first electrode 155 serving as a reflector. The fourth passivation layer 160 is formed on the entire surface of the substrate 101.

Subsequently, the gate pad electrode GPA is formed by patterning the fourth passivation layer 160, the third and first passivation layers 148 and 140 and the gate insulating layer 115 disposed thereunder. A gate pad contact hole 162 exposing the 110 is formed, and at the same time, a data pad contact hole 164 exposing the data pad electrode 131 is formed in the data pad part DPA.

In the modified example, since the first and third protective layers 140 and 148 are omitted, only the fourth protective layer 160 and the gate insulating layer 115 are patterned to form the gate pad in the gate pad part GPA. The gate pad contact hole 162 exposing the electrode 110 may be formed, and at the same time, the data pad contact hole 164 exposing the data pad electrode 131 may be formed in the data pad part DPA.

Next, as shown in FIGS. 2F and 3H, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is deposited over the fourth protective layer 160 on the entire surface of the substrate. To form a transparent conductive material layer (not shown).

Subsequently, the transparent conductive material layer (not shown) is patterned by performing a mask process so as to penetrate each pixel region P parallel to the gate wiring 103 in the display area. Second and third electrodes 165 and 168 are formed.

At the same time, in the gate pad part GPA, an auxiliary gate pad electrode 172 is formed in contact with the gate pad electrode 110 through the gate pad contact hole 162, and is formed in the data pad part DPA. In this case, the auxiliary data pad electrode 174 is formed to contact the data pad electrode 131 through the data pad contact hole 164.

Although not shown in the drawing, a second auxiliary line (not shown) connecting the end of the second electrode 165 is formed in the non-display area, and at the same time, the second auxiliary line connecting the end of the third electrode 168. By forming a wiring (not shown), an array substrate for a bistable chiral splay nematic (BCSN) mode liquid crystal display device according to an embodiment of the present invention is completed.

In this case, although the pair of second and third electrodes 165 and 168 formed to penetrate the pixel region P is formed in each pixel region P, the pixel region P may be an example. The second and third electrodes 165 and 168 may be formed in plural pairs such as two pairs, three pairs, and the like in a form of spaced apart from each other at regular intervals.

In the case of manufacturing the array substrate 101 for the bistable chiral splay nematic (BCSN) mode liquid crystal display device as described above, the gate wiring 103 and the electrode 108 / data wiring 130 and the source and drain electrodes (133, 136) / first electrode 155 serving as a third protective layer 148 / reflector having a second protective layer 145 / drain contact hole 149 formed corresponding to the display area with an organic insulating material Conventional bistable chiral splay nematic by performing a total of seven mask processes to form the fourth passivation layer 160 / second and third electrodes 165 and 168 with the pad contact holes 162 and 164. ) It has the effect of reducing the mask process twice compared to the manufacturing method of the array substrate for a mode liquid crystal display device, and in the case of the modification of omitting the first and third protective layers (140, 148), a total of six mask processes are conventionally performed. In comparison, the mask process is reduced three times.

101: (array for BCSN liquid crystal display device) substrate
108: gate electrode 109: first storyr electrode
110: gate pad electrode 115: gate insulating film
120: semiconductor layer 120a: active layer
120b: ohmic contact layer 121: dummy pattern
121a and 121b: first and second patterns 130: data wiring
131: data pad electrode 133: source electrode
136: drain electrode 137: second storage electrode
140: first protective layer 145: second protective layer
146: first contact hole 148: third protective layer
149: drain contact hole 155: first electrode
160: fourth protective layer 162: gate pad contact hole
164: data pad contact hole 165: second electrode
168: third electrode 172: auxiliary gate pad electrode
174: auxiliary data pad electrode DPA: data pad portion
GPA: Data pad portion P: Pixel area
StgA: Storage Area StgC: Storage Capacitor
Tr: Thin Film Transistor TrA: Switching Area

Claims (9)

A gate and data line defining the pixel area by crossing the display area on a substrate having a plurality of pixel areas and a non-display area defined outside thereof, and connected to the gate and data wires in the pixel area; Forming a thin film transistor;
Forming a first protective layer having a first contact hole in the display area over the thin film transistor and exposing a drain electrode of the thin film transistor and having a flat surface as an organic insulating material;
Forming a plate-shaped first electrode in contact with the drain electrode of the thin film transistor through the first contact hole in the pixel area over the first passivation layer and serving as a reflector;
Forming a second protective layer over the first electrode over the first electrode;
Forming second and third electrodes penetrating through the pixel areas and spaced apart from each other in parallel to the second passivation layer;
Method of manufacturing an array substrate for a bistable chiral splay nematic (BCSN) mode liquid crystal display comprising a.
The method according to claim 1 or 2,
Forming a third protective layer of an inorganic insulating material on the entire surface of the substrate over the thin film transistor before forming the first protective layer;
Before forming the first electrode, a fourth passivation layer is formed on the entire surface of the substrate over the first passivation layer using an inorganic insulating material, and the fourth passivation layer and the third passivation layer are patterned to form the fourth passivation layer. Exposing the drain electrode of the thin film transistor
Method of manufacturing an array substrate for a bistable chiral splay nematic (BCSN) mode liquid crystal display comprising a.
The method according to claim 1 or 2,
The first electrode is a method of manufacturing an array substrate for a bistable chiral splay nematic (BCSN) mode liquid crystal display device characterized in that the first electrode is formed of aluminum (Al) or aluminum alloy (AlNd) which is a metal material with excellent reflectance.
The method according to claim 1 or 2,
Forming the gate and data lines and the thin film transistor,
Forming the gate wiring extending in one direction at a boundary of each pixel region, and forming the gate electrode connected to the gate wiring in each pixel region;
Forming a gate insulating film as an inorganic insulating material over the gate wiring and the gate electrode;
Forming a data line on the gate insulating layer to cross the gate line to define the pixel area, a semiconductor layer formed thereon to correspond to the gate electrode, and a source electrode connected to the data line above the semiconductor layer; Forming the drain electrode spaced apart from the gap
Method of manufacturing an array substrate for a bistable chiral splay nematic (BCSN) mode liquid crystal display comprising a.
The method of claim 4, wherein
The forming of the gate wiring may include forming a common wiring having a shape passing through each pixel region in the display area, and forming a gate pad electrode connected to one end of the gate wiring in the non-display area.
The forming of the data line may include forming a gate pad electrode connected to one end of the data line in the non-display area, wherein the array substrate for a bistable chiral splay nematic (BCSN) mode liquid crystal display device is formed.
The method of claim 5, wherein
The forming of the second passivation layer may include patterning the second passivation layer, the first passivation layer, and the gate insulating layer to expose the gate pad contact hole and the data pad electrode exposing the gate pad electrode. A method of manufacturing an array substrate for a bistable chiral splay nematic (BCSN) mode liquid crystal display device characterized by forming a data pad contact hole.
The method according to claim 6,
The forming of the second and third electrodes may include an auxiliary gate pad electrode contacting the gate pad electrode through the gate pad contact hole, and an auxiliary data pad electrode contacting the data pad electrode through the data pad contact hole. Method of manufacturing an array substrate for a bistable chiral splay nematic (BCSN) mode liquid crystal display device comprising the step of forming a.
The method of claim 5, wherein
The common wiring may include a bistable chiral splay nematic (BCSN) mode liquid crystal display, in which the drain electrode is formed such that the common electrode and the end thereof overlap each other so that the common wiring, the gate insulating layer, and the drain electrode overlap each other to form a storage capacitor. Method of manufacturing an array substrate for an apparatus.
The method according to claim 1 or 2,
The forming of the second and third electrodes may include forming a first auxiliary line connecting the end of the second electrode and a second auxiliary line connecting the end of the second electrode to the non-display area. A method of manufacturing an array substrate for a bistable chiral splay nematic (BCSN) mode liquid crystal display comprising a liquid crystal display.

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