KR20120065607A - Semiconductor light emitting device and manufacturing method of the same - Google Patents

Abstract

PURPOSE: A semiconductor light emitting device and a manufacturing method thereof are provided to prevent the deterioration of crystallinity of the semiconductor layer by interposing a buffer unit between a substrate and a p type nitride semiconductor layer. CONSTITUTION: A p-type nitride semiconductor layer(102) is formed on a substrate(101). An active layer(103) is formed on the p-type nitride semiconductor layer. An n type zinc oxide semiconductor layer(104) is formed on the active layer. A first electrode(105) is formed on the lower side of the substrate. A second electrode(106) is formed on the upper side of the n type zinc oxide semiconductor layer.

Description

Semiconductor light emitting device and manufacturing method of the same

The present invention relates to a semiconductor light emitting device and a method for manufacturing the semiconductor light emitting device.

A light emitting diode (LED), which is a kind of semiconductor light emitting device, is a semiconductor device capable of generating light of various colors based on recombination of electrons and holes at junctions of p and n type semiconductors when current is applied thereto. Such semiconductor light emitting devices have a number of advantages, such as long lifespan, low power supply, excellent initial driving characteristics, high vibration resistance, etc., compared to filament based light emitting devices. In particular, in recent years, group III nitride semiconductors capable of emitting light in a blue series short wavelength region have been in the spotlight.

The light emitting device using the group III nitride semiconductor is obtained by growing a light emitting structure having an n-type and p-type nitride semiconductor layer and an active layer formed therebetween on the substrate, in this case, a sapphire substrate as a substrate for growth of the nitride semiconductor This is commonly used. The sapphire substrate has a hexagonal laminar structure that is relatively easy to grow a nitride thin film, and has the advantage of being stable at high temperatures.

However, sapphire (α-Al ₂ O ₃₎ For the substrate, the hardness is high, processability is inferior. In addition, a sapphire substrate is relatively expensive, and in the case of a practically used substrate, since the area is relatively small, there is a limit in manufacturing a large number of devices at one time. Specifically, in order to replace an existing light source such as a fluorescent lamp, the efficiency related to the manufacturing cost needs to be greatly improved. For this purpose, a large diameter of the substrate may be considered. Sapphire substrates commonly used at present are relatively small in size (mainly 2 " and 3 "), so there is a problem in that mass production is low. In order to solve this problem, a method of replacing a sapphire substrate with another wafer having a low cost and large diameter such as a silicon (Si) substrate has been studied.

An object of the present invention is to provide a semiconductor light emitting device having excellent workability and improved crystal quality and light extraction efficiency by using a substrate suitable for obtaining a large number of devices at a large area at a time.

Another object of the present invention is to provide a method for efficiently manufacturing a semiconductor light emitting device having the above structure.

In order to solve the above problems, an aspect of the present invention,

Provided is a semiconductor light emitting device comprising a substrate, a p-type nitride semiconductor layer formed on the substrate, an active layer formed on the p-type nitride semiconductor layer, and an n-type zinc oxide semiconductor layer formed on the active layer.

In one embodiment of the present invention, irregularities may be formed on the side of the substrate.

In one embodiment of the present invention, the substrate may have electrical conductivity.

In one embodiment of the present invention, the substrate may be a silicon (Si) substrate.

In an embodiment of the present disclosure, the semiconductor device may further include an ohmic contact portion formed between the substrate and the p-type nitride semiconductor layer.

In this case, the ohmic contact part may include a highly doped n-type nitride semiconductor layer.

In addition, the ohmic contact unit may include at least one of InN, InGaN, and InGaN / GaN.

In an embodiment of the present invention, the semiconductor device may further include a buffer unit formed in at least a portion of the region between the substrate and the first conductive semiconductor layer.

In this case, the buffer unit may include a nucleation layer formed on the substrate and a stress compensation layer formed on the nucleation layer and having a larger lattice constant than the nucleation layer.

In this case, the nucleation layer is made of an Al-containing nitride semiconductor, and the stress compensation layer may be made of a nitride semiconductor having a lower Al content or no Al than the nucleation layer.

In addition, the nucleation layer may include a first nitride semiconductor layer formed on the substrate and a second nitride semiconductor layer made of a material having a lattice constant greater than that of the first nitride semiconductor layer and having a smaller lattice constant than the stress compensation layer. In this case, the first nitride semiconductor layer is made of AlN, the second nitride semiconductor layer is made of Al _x Ga _(1-x) N (0 <x <1), the stress compensation layer is GaN Can be made.

The second nitride semiconductor layer may have a higher Al content than a region close to the stress compensation layer in a region close to the first nitride semiconductor layer.

In addition, the stress compensation layer may be made of undoped GaN.

In addition, the buffer unit may further include a porous mask layer disposed between the nucleation layer and the stress compensation layer.

In contrast, the stress compensation layer is divided into upper and lower layers in a thickness direction, and the buffer unit may further include a porous mask layer disposed between the upper and lower layers.

In this case, the porous mask layer may be made of silicon nitride.

In addition, the buffer part may further include an intermediate layer made of a material different from the stress compensation layer on the stress compensation layer, in this case, the stress compensation layer is made of GaN, the intermediate layer is Al _x Ga _{(1- x)} N (0 <x≤1).

In addition, the buffer part is formed on the intermediate layer, and may further include an additional nitride layer made of a material different from the intermediate layer, in this case, the additional nitride layer may be made of GaN.

In one embodiment of the present invention, the semiconductor substrate may further include a reflector formed in at least a portion of the region between the substrate and the first conductivity-type semiconductor layer.

In this case, the reflector may have a DBR structure.

On the other hand, another aspect of the present invention,

Growing a p-type nitride semiconductor layer on a substrate, growing an active layer on the p-type nitride semiconductor layer, and growing an n-type zinc oxide semiconductor layer on the active layer. To provide.

In an embodiment of the present disclosure, the method may further include forming an ohmic contact portion on the substrate before growing the p-type nitride semiconductor layer.

In an embodiment of the present disclosure, the method may further include forming a buffer unit on the substrate before growing the p-type nitride semiconductor layer.

In an embodiment of the present disclosure, the method may further include forming a reflector on the substrate before growing the p-type nitride semiconductor layer.

In an embodiment of the present disclosure, growing the n-type zinc oxide semiconductor layer may be performed at a lower temperature than growing the p-type nitride semiconductor layer.

In an embodiment of the present disclosure, the growing of the n-type zinc oxide semiconductor layer may be performed at a temperature of 900 ° C. or less.

According to an embodiment of the present invention, a semiconductor light emitting device having improved processability and improved crystal quality and light extraction efficiency may be obtained using a substrate that is excellent in workability and suitable for obtaining a large number of devices at a large area at one time.

In addition, according to another embodiment of the present invention, it is possible to obtain a method for efficiently manufacturing a semiconductor light emitting device having the above structure.

1 is a cross-sectional view schematically showing a semiconductor light emitting device according to an embodiment of the present invention.
FIG. 2 is a schematic perspective view illustrating a semiconductor light emitting device of FIG. 1 mounted on a module substrate. FIG.
3 is a schematic cross-sectional view of a semiconductor light emitting device according to an embodiment modified from the embodiment of FIG. 1.
4 is a schematic cross-sectional view of a semiconductor light emitting device according to another embodiment of the present invention.
5 is a schematic cross-sectional view of a semiconductor light emitting device according to still another embodiment of the present invention.
6 is a schematic cross-sectional view of a semiconductor light emitting device according to still another embodiment of the present invention.
7 to 9 are schematic cross-sectional views illustrating processes for manufacturing a semiconductor light emitting device according to one embodiment of the present invention.
10 is a configuration diagram schematically showing an example of use of a semiconductor light emitting device proposed in the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

However, embodiments of the present invention may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. Further, the embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art. Accordingly, the shapes and sizes of the elements in the drawings may be exaggerated for clarity of description, and the elements denoted by the same reference numerals in the drawings are the same elements.

1 is a cross-sectional view schematically showing a semiconductor light emitting device according to an embodiment of the present invention. Referring to FIG. 1, the semiconductor light emitting device 100 according to the present embodiment includes a substrate 101, a p-type nitride semiconductor layer 102, an active layer 103, and an n-type zinc oxide (ZnO) semiconductor layer 104. It includes a structure. In this case, the first and second electrodes 105 and 106 may be provided on the bottom surface of the substrate 101 and the top surface of the n-type zinc oxide semiconductor layer 104 in order to apply an external electric signal. However, in this specification, terms such as 'top', 'bottom', and 'side' are based on the drawings and may actually vary depending on the direction in which the device is disposed.

The substrate 101 may be provided as a substrate for growing a semiconductor, and a substrate made of an electrically insulating and conductive material such as Si, sapphire, SiC, MgAl ₂ O ₄ , MgO, LiAlO ₂ , LiGaO ₂ , GaN, or the like may be used. As shown in FIG. 1, an electrically conductive substrate should be used to form the electrode 105 on the bottom surface of the substrate 101. If the electrically insulating substrate is used, the electrode 105 may need to be disposed at another position. will be. In particular, in this embodiment, a substrate 101 made of Si, that is, a silicon semiconductor is used. In this case, n-type or p-type doping may be performed on the silicon substrate 101 to have a high level of electrical conductivity. The silicon semiconductor used as the substrate 101 in this embodiment can be provided as a large area substrate, which can provide an advantage in mass production of the device. In addition, in the case of the silicon semiconductor substrate 101, it is also an advantage that the processability and heat dissipation performance are relatively excellent. However, when the silicon semiconductor is used as a substrate, since the lattice constant difference between the material such as nitride semiconductor and the like grown thereon is relatively large, the crystallinity of the grown semiconductor layer may be poor, as will be described later. This problem can be minimized by employing an appropriate buffer section.

The p-type nitride semiconductor layer 102 is made of, for example, a material having a composition of Al _x In _y Ga _(1-xy) N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). Dopants such as Mg and Zn are doped. In the case of a general light emitting diode structure, the n-type semiconductor layer is preferentially grown on the growth substrate, but in this embodiment, the p-type nitride semiconductor layer 102 is grown on the substrate 101, and the active layer 103 and The n-type zinc oxide semiconductor layer 104 is grown. By employing a device having the p-type nitride semiconductor layer 102 disposed thereunder, the hole barrier may be lowered during operation of the device, and thus the hole injection efficiency may be improved. The active layer 103 disposed between the p-type nitride semiconductor layer 102 and the n-type zinc oxide semiconductor layer 104 emits light having a predetermined energy by recombination of electrons and holes, and generates a quantum well layer and a quantum barrier. In the case of a multi-quantum well (MQW) structure in which layers are alternately stacked with each other, for example, a nitride semiconductor, a GaN / InGaN structure may be used. An n-type zinc oxide semiconductor layer 104 is disposed on the active layer 103 to form a junction structure of dissimilar materials. In this embodiment, the n-type zinc oxide semiconductor layer 104 is used because the growth temperature (about 900 ° C. or less) is relatively low, so that thermal damage of the active layer 103 disposed under the growth process can be minimized. In addition, in the case of the zinc oxide semiconductor, the refractive index is about 2.0, which is lower than that of GaN, which is about 2.4, so that the n-type zinc oxide semiconductor layer 104 may be disposed on the light emitting structure to improve light extraction efficiency.

Meanwhile, the semiconductor light emitting device 100 having the same structure as the present embodiment may be mounted on a module substrate and used as a light emitting device. FIG. 2 is a schematic perspective view illustrating a semiconductor light emitting device of FIG. 1 mounted on a module substrate. FIG. As shown in FIG. 2, the module substrate 107 includes first and second terminal patterns 108, 109. The first electrode 105 of the device is connected to the first terminal pattern 109 and may be coupled to each other by a bonding layer (not shown) such as a eutectic metal or a conductive polymer. In addition, the second electrode 106 may be connected to the second terminal pattern 109 formed on the upper surface of the module substrate 107 through the conductive wire (W).

3 is a schematic cross-sectional view of a semiconductor light emitting device according to an embodiment modified from the embodiment of FIG. 1. Referring to FIG. 3, in the case of the semiconductor light emitting device 100 ′ according to the present embodiment, irregularities are formed on at least one surface (side surface in the present embodiment) of the substrate 101 ′, and other components are different from those of the foregoing embodiment. same. Since the substrate 101` made of a silicon semiconductor has superior heat dissipation performance as compared to other substrates such as sapphire, the device using the same can be expected to improve heat dissipation and emission characteristics, and in particular, the substrate as in the present embodiment. By forming irregularities at 101 ', heat dissipation performance may be further improved. In this case, the unevenness of the substrate 101 ′ may be easily formed by a process such as CMP, RIE, etc. using the excellent processability of silicon. On the other hand, the unevenness of the substrate 101 'proposed in the present modification may be employed in the embodiments described below.

4 is a schematic cross-sectional view of a semiconductor light emitting device according to another embodiment of the present invention. Referring to FIG. 4, the semiconductor light emitting device 200 according to the present embodiment includes a substrate 201, a p-type nitride semiconductor layer 202, an active layer 203, an n-type zinc oxide semiconductor layer 204, and a first electrode. 205 and the second electrode 206, unlike the previous embodiment, an ohmic contact portion C is interposed between the substrate 201 and the p-type nitride semiconductor layer 202. The ohmic contact portion C may improve the electrical properties by forming an ohmic contact with the p-type nitride semiconductor layer 202 and the substrate 201, and may be a highly doped n-type semiconductor layer or an InGaN, InN, or InGaN / GaN structure. And the like. This structure can form a tunneling junction (tunneling junction) can increase the injection efficiency of the carrier. In this case, the amount of doping in the highly doped n-type semiconductor layer may be more than about 10 ¹⁹ / cm 3 as a larger amount than the conventional n-type semiconductor layer. On the other hand, the ohmic contact portion (C) proposed in the present modification may be employed in the embodiments described below.

5 is a schematic cross-sectional view of a semiconductor light emitting device according to another embodiment of the present invention. Referring to FIG. 5, the semiconductor light emitting device 300 according to the present embodiment includes a substrate 301, a p-type nitride semiconductor layer 302, an active layer 303, an n-type zinc oxide semiconductor layer 304, and a first electrode. 305 and the second electrode 306, and unlike the previous embodiment, the buffer portion B is interposed between the substrate 301 and the p-type nitride semiconductor layer 302. The buffer part B may alleviate the tensile stress generated when depositing a material having a lattice constant smaller than that of the silicon semiconductor, such as a nitride semiconductor, on the silicon substrate 301, and further, the semiconductor layer grown thereon. It may be composed of a plurality of semiconductor layers to reduce crystal defects. Therefore, by employing the buffer portion B, it is possible to minimize the deterioration of crystallinity of the semiconductor layer grown while using the silicon substrate 301. The detailed configuration and function of the buffer portion B are illustrated in FIGS. 7 and 8. This will be described in connection with. On the other hand, the buffer unit (B) proposed in the present modification may be employed in the embodiments described below.

6 is a schematic cross-sectional view of a semiconductor light emitting device according to still another embodiment of the present invention. Referring to FIG. 6, the semiconductor light emitting device 400 according to the present embodiment includes a substrate 401, a p-type nitride semiconductor layer 402, an active layer 403, an n-type zinc oxide semiconductor layer 404, and a first electrode. 405 and a second electrode 406, and unlike the previous embodiment, a reflecting portion R is interposed between the substrate 401 and the p-type nitride semiconductor layer 402. The reflector R may emit light emitted from the active layer 403 toward the substrate 401, and light absorption by the silicon semiconductor having a relatively low reflectance may be reduced by the reflector R. For example, in the case of a nitride semiconductor light emitting device of blue light, blue photon energy (˜2.7 eV) generated in the active layer 303 may be emitted in all directions. Here, since the photons directed to the silicon substrate 301 are all absorbed by the silicon substrate 301 (the energy band gap of Si: 1.1 eV), a considerable amount (about 50%) of the photons may be lost, resulting in a decrease in light efficiency. There is a problem. Therefore, as in the present embodiment, the light absorption by the silicon substrate 3010 can be minimized by employing the reflector R. FIG.

The reflector R may be any material as long as the material has high light reflectivity. For example, as illustrated in FIG. 6, the reflector R may have a DBR structure in which dielectric layers R1 and R2 having different refractive indices are alternately stacked. Can be used. In addition, an ODR structure in which a reflective layer and a low refractive layer is stacked may be used. In this case, the DBR structure may be implemented by combining materials such as SiO ₂ , TiO ₂ , TiO ₂ , SiC, or AlGaN / GaN, InGaN / In. On the other hand, the reflection unit (R) proposed in the present modification may be employed in the embodiments described below.

Hereinafter, a method of manufacturing a semiconductor light emitting device having the above-described structure will be described, and the structure (including both the ohmic contact portion and the buffer portion) shown in FIGS. 4 and 5 will be referred to, but in a similar manner in other embodiments. It may be prepared by applying. 7 to 9 are schematic cross-sectional views illustrating processes for manufacturing a semiconductor light emitting device according to one embodiment of the present invention.

First, as shown in FIG. 7, the buffer portion B is formed on the substrate 101, and the buffer portion B is formed from the top surface of the substrate 101 by the nucleation layer 501, the mask layer 502, A stress compensation layer 503, an intermediate layer 504, and an additional nitride semiconductor layer 505. As described above, the buffer unit B may have a multilayer structure to minimize crystal defects of the semiconductor layer grown thereon, and to reduce the stress applied to the semiconductor layer to lower the possibility of crack generation.

Referring to each component of the buffer unit B, first, the nucleation layer 501 may be made of an Al-containing nitride semiconductor, and may be grown under low temperature conditions on the upper surface of the substrate 101 made of a dissimilar material such as a silicon semiconductor. Can be. As a more specific example, the nucleation layer 501 may be divided into two layers, in which case, the first nitride semiconductor layer made of AlN and Al _x Ga _(1-x) N (0 <x <1) It may include a second nitride semiconductor layer. The second nitride semiconductor layer may be employed to mitigate the lattice constant difference between AlN (first nitride semiconductor layer) and GaN (stress compensation layer) when the stress compensation layer 503 grown thereon is made of GaN. To this end, the second nitride semiconductor layer may have a structure in which an Al content is higher than a region close to the stress compensation layer 503 in a region close to the first nitride semiconductor layer. In addition, since the lattice constant of the second nitride semiconductor layer made of Al _x Ga _(1-x) N (0 <x <1) is larger than that of the first nitride semiconductor layer made of AlN, it is extended by the second nitride semiconductor layer. Compressive stress may be generated to relieve stress.

When the nucleation layer 501 having the above-described structure is grown, the nucleation layer 501 is subjected to elongation stress due to the lattice constant difference with the silicon substrate 101, which is because the nitride semiconductor is a silicon semiconductor, for example, This is because the lattice constant is smaller than the (111) plane. The semiconductor layer grown in the state where the extension stress is applied is bent in the cooling step after growth, and there is a problem that defects such as cracks occur in the semiconductor layer due to such bending, and according to the present embodiment, Layers were formed on nucleation layer 501. Specifically, the stress compensation layer 503 formed on the nucleation layer 502 is made of a material having a lattice constant larger than that of the nucleation layer 502, and thus, may generate a compressive stress that compensates for the stretching stress. have. When the nucleation layer 502 is made of Al-containing nitride semiconductor, the stress compensation layer 503 may be made of a nitride layer having a lower Al content than GaN or the nucleation layer 502. In addition, the stress compensation layer 503 may be undoped or doped with impurities. However, when the stress compensation layer 503 is made of an undoped semiconductor, the compressive stress generation effect may be further increased.

On the other hand, as shown in FIG. 7, the porous mask layer 502 may be formed on the nucleation layer 501 before the stress compensation layer 503 is grown. The porous mask layer 502 may be made of silicon nitride (SiN _x ) having a plurality of open regions, and may be formed to have a plurality of open regions exposing the nucleation layer 501 by applying appropriate growth conditions, for example. have. Defects such as dislocations in the nucleation layer 501 are blocked by the porous mask layer 502, and the stress compensation layer 503 may induce lateral growth through the open region, thereby constituting an element. The crystallinity of the semiconductor layers can be improved.

In this case, the formation order of the porous mask layer 502 may vary depending on the embodiment. That is, as shown in FIG. 8, the porous mask layer 502 may be disposed between the stress compensation layers 503 and 503 ′. In this case, the stress compensation layer is divided into an upper layer 503 and a lower layer 503 ′. Specifically, after the growth of the lower layer 503 ′, the porous mask layer 502 is formed, and then the upper layer 503 is regrown. Can be obtained. In such a structure, the stress compensation layer 503 ′ may be formed directly on the nucleation layer 501, which may be more advantageous in terms of compressive stress generation effect.

The intermediate layer 504 is formed on the stress compensation layer 503 and is made of a material different from that of the stress compensation layer 503 to form a heterogeneous interface with the stress compensation layer 503. Specifically, when the stress compensation layer 503 is made of GaN, the intermediate layer 504 may be made of Al _x Ga _(1-x) N (0 <x≤1), and the stress compensation layer 503 and the intermediate layer ( Since propagation of dislocations may be blocked at the heterogeneous interface of 504, an improvement in crystallinity may be expected by the intermediate layer 504. However, the intermediate layer 504 will not necessarily be necessary elements in this embodiment, and may be excluded in some cases. Next, the additional nitride semiconductor layer 505 may be formed of the same material as that of the stress compensation layer 503, for example, GaN, and may be employed as a multi-layer structure of GaN / n-GaN. In addition, since the additional nitride semiconductor layer 505 is formed of a material different from that of the intermediate layer 504, similar to the foregoing description, dislocations may be blocked.

In this way, when the nitride semiconductors are grown on the silicon substrate 101, which is advantageous for mass production, by employing the buffer sections B and B` having the above-described structure, cracks are reduced and high quality with improved crystallinity. The light emitting diode structure can be obtained. Referring to FIG. 8, a multilayer buffer structure employable in the present invention will be described in detail by another approach. An AlN / AlGaN nucleation layer 501 is grown on the silicon substrate 101, and is continuously undoped GaN. To grow the compensation layers 503 and 503` and the additional nitride semiconductor layer 505 which is n-type GaN, and to reduce the dislocation density inside the stress compensation layers 503 and 503` and the additional nitride semiconductor layer 505, respectively. It may be understood that the SiN _x porous mask layer 502 and the AlGaN intermediate layer 504 are further interposed. In a specific example, an AlN / AlGaN nuclear growth layer (about 2 μm or less) is grown, and an undoped GaN layer (about 2 μm or less) and an n-type GaN layer (3 to 4 μm) are grown in succession. When additionally using the SiN _x layer and the AlGaN interlayer at the submicro level inside the layer, the crystallinity of GaN in the light emitting structure grown based on the multilayer buffer structure was (300) for FWHM, <300 arcsec, ( 102) In the case of FWHM, <400 arcsec or less. In addition, no crack is formed on the wafer, and bowing due to thermal stress can be maintained at a low level of <20 μm.

On the other hand, after the buffer portion B is formed, an ohmic contact portion C having a structure such as a highly doped n-type semiconductor layer or In, for example, InGaN, InN, or InGaN / GaN, is formed. As shown in FIG. 9, a light emitting structure, that is, a p-type nitride semiconductor layer 102, an active layer 103, and an n-type zinc oxide semiconductor layer 104 is formed by a process such as MOCVD, HVPE, or the like. In this case, since the n-type zinc oxide semiconductor layer 104 may be grown at about 900 ° C. or less, which corresponds to a relatively low temperature, damage to the active layer 103 may be minimized during the growth process. Thereafter, the first and second electrodes may be formed on the bottom surface of the substrate 101 and the n-type zinc oxide semiconductor layer 104, respectively, to implement a device.

On the other hand, the semiconductor light emitting device having the above structure can be applied in various fields. 10 is a configuration diagram schematically showing an example of use of a semiconductor light emitting device proposed in the present invention. Referring to FIG. 10, the dimming device 600 includes a light emitting module 601, a structure 604 on which the light emitting module 601 is disposed, and a power supply unit 603, and the light emitting module 601 includes the present invention. One or more semiconductor light emitting devices 602 obtained in the manner proposed by the present invention may be disposed. In this case, the semiconductor light emitting device 602 may be mounted on the module 601 or may be provided in a package form. The power supply unit 603 may include an interface 605 for receiving power and a power control unit 606 for controlling the power supplied to the light emitting module 601. In this case, the interface 605 may include a fuse that blocks overcurrent and an electromagnetic shielding filter that shields an electromagnetic interference signal.

When the AC power is input to the power source, the power control unit 606 may include a rectifying unit for converting AC into DC and a constant voltage control unit for converting to a voltage suitable for the light emitting module 601. If the power source itself is a direct current source (for example, a battery) having a voltage suitable for the light emitting module 601, the rectifying unit or the constant voltage control unit may be omitted. In addition, when the light emitting module 601 itself employs an element such as an AC-LED, AC power may be directly supplied to the light emitting module 601, and in this case, the rectifier or the constant voltage controller may be omitted. In addition, the power control unit may control the color temperature and the like to enable the illumination of the human emotion. In addition, the power supply unit 603 may include a feedback circuit device for performing a comparison between the light emission amount of the light emitting element 602 and a predetermined light amount, and a memory device in which information such as desired luminance and color rendering properties are stored.

The dimming device 600 may be used as a backlight unit used in a display device such as a liquid crystal display device including an image panel, an indoor lighting device such as a lamp, a flat panel light, or an outdoor lighting device such as a street lamp, a signboard, a sign, and the like. It can be used in various transportation lighting devices, such as automobiles, ships, aircrafts, and the like. Furthermore, it may be widely used in home appliances such as TVs and refrigerators, and medical devices.

The present invention is not limited by the above-described embodiments and the accompanying drawings, but is intended to be limited only by the appended claims. It will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. something to do.

101: substrate 102: p-type nitride semiconductor layer
103: active layer 104: n-type zinc oxide semiconductor layer
105: first electrode 106: second electrode
107: module substrate 108, 109: first and second terminal pattern
C: ohmic contact section B: buffer section
R: reflector R1, R2: dielectric layer
501: nucleation layer 502: porous mask
503: stress compensation layer 504: intermediate layer
505: additional nitride semiconductor layer

Claims (29)

Board;
A p-type nitride semiconductor layer formed on the substrate;
An active layer formed on the p-type nitride semiconductor layer; And
An n-type zinc oxide semiconductor layer formed on the active layer;
Semiconductor light emitting device comprising a.
The method of claim 1,
The semiconductor light emitting device, characterized in that the irregularities formed on the side of the substrate.
The method of claim 1,
The substrate is a semiconductor light emitting device, characterized in that it has electrical conductivity.
The method of claim 1,
The substrate is a semiconductor light emitting device, characterized in that the silicon (Si) substrate.
The method of claim 1,
And an ohmic contact portion formed between the substrate and the p-type nitride semiconductor layer.
The method of claim 5,
And the ohmic contact portion comprises a highly doped n-type nitride semiconductor layer.
The method of claim 5,
The ohmic contact unit includes at least one structure of InN, InGaN, and InGaN / GaN.
The method of claim 1,
And a buffer unit formed in at least a portion of the substrate and the first conductive semiconductor layer.
The method of claim 8,
And the buffer unit comprises a nucleation layer formed on the substrate and a stress compensation layer formed on the nucleation layer and having a lattice constant greater than that of the nucleation layer.
10. The method of claim 9,
And the nucleation layer is formed of an Al-containing nitride semiconductor, and the stress compensation layer is formed of a nitride semiconductor having a lower Al content or no Al than the nucleation layer.
10. The method of claim 9,
The nucleation layer includes a first nitride semiconductor layer formed on the substrate and a second nitride semiconductor layer made of a material having a lattice constant greater than that of the first nitride semiconductor layer and smaller than the stress compensation layer. A semiconductor light emitting device.
The method of claim 11,
The first nitride semiconductor layer is made of AlN, the second nitride semiconductor layer is made of Al _x Ga _(1-x) N (0 <x <1), characterized in that the stress compensation layer is made of GaN A semiconductor light emitting device.
The method of claim 12,
And wherein the second nitride semiconductor layer has a higher Al content than a region close to the stress compensation layer in a region close to the first nitride semiconductor layer.
The method of claim 12,
The stress compensation layer is a semiconductor light emitting device, characterized in that made of undoped GaN.
15. The method according to any one of claims 9 to 14,
The buffer unit further comprises a porous mask layer disposed between the nucleation layer and the stress compensation layer.
15. The method according to any one of claims 9 to 14,
The stress compensation layer is divided into upper and lower layers in the thickness direction,
The buffer unit semiconductor light emitting device characterized in that it further included a porous mask layer disposed between the top and bottom tiers.
16. The method of claim 15,
The porous mask layer is a semiconductor light emitting device, characterized in that made of silicon nitride.
10. The method of claim 9,
And the buffer part further comprises an intermediate layer formed of a material different from the stress compensation layer on the stress compensation layer.
19. The method of claim 18,
The stress compensation layer is made of GaN, the intermediate layer is a semiconductor light emitting device, characterized in that consisting of Al _x Ga _(1-x) N (0 <x _{≤ 1} ).
19. The method of claim 18,
The buffer unit is formed on the intermediate layer, the semiconductor light emitting device further comprises an additional nitride layer made of a material different from the intermediate layer.
21. The method of claim 20,
The additional nitride layer is a semiconductor light emitting device, characterized in that made of GaN.
The method of claim 1,
And a reflecting portion formed in at least a portion of the substrate and the p-type nitride semiconductor layer.
The method of claim 22,
The reflector has a DBR structure, characterized in that the semiconductor light emitting device.
Growing a p-type nitride semiconductor layer on the substrate;
Growing an active layer on the p-type nitride semiconductor layer; And
Growing an n-type zinc oxide semiconductor layer on the active layer;
Gt; a &lt; / RTI &gt; semiconductor light emitting device.
25. The method of claim 24,
And forming an ohmic contact portion on the substrate before growing the p-type nitride semiconductor layer.
25. The method of claim 24,
And forming a buffer unit on the substrate before growing the p-type nitride semiconductor layer.
25. The method of claim 24,
And forming a reflector on the substrate before growing the p-type nitride semiconductor layer.
25. The method of claim 24,
Growing the n-type zinc oxide semiconductor layer is performed at a lower temperature than growing the p-type nitride semiconductor layer.
25. The method of claim 24,
Growing the n-type zinc oxide semiconductor layer is carried out at a temperature of 900 ℃ or less.

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