Nothing Special   »   [go: up one dir, main page]

KR20120055153A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

Info

Publication number
KR20120055153A
KR20120055153A KR1020100116694A KR20100116694A KR20120055153A KR 20120055153 A KR20120055153 A KR 20120055153A KR 1020100116694 A KR1020100116694 A KR 1020100116694A KR 20100116694 A KR20100116694 A KR 20100116694A KR 20120055153 A KR20120055153 A KR 20120055153A
Authority
KR
South Korea
Prior art keywords
hard mask
mask pattern
film
forming
semiconductor device
Prior art date
Application number
KR1020100116694A
Other languages
Korean (ko)
Inventor
이시영
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020100116694A priority Critical patent/KR20120055153A/en
Publication of KR20120055153A publication Critical patent/KR20120055153A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A semiconductor device manufacturing method is provided to prevent degradation of a profile using a sacrificial film which buries an open region while burying a hard mask pattern. CONSTITUTION: An insulating film is formed in on a substrate. A hard mask pattern(37) is formed on the insulating layer. An open region is formed by etching the insulating film using the hard mask pattern as an etch barrier. A sacrificial film(39) for burying the inner part of the open region is formed . The hard mask pattern is removed by performing a blanket etch process. The sacrificial film is removed.

Description

반도체 장치 제조방법{METHOD FOR FABRICATING SEMICONDUCTOR DEVICE} Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

본 발명은 반도체 장치의 제조 기술에 관한 것으로, 특히 딥콘택(Deep Contact)을 갖는 오픈영역을 구비한 반도체 장치의 제조방법에 관한 것이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing technique of a semiconductor device, and more particularly, to a manufacturing method of a semiconductor device having an open area having deep contacts.

최근, 반도체 장치 예컨대, 디램(DRAM)이 고집적화됨에 따라 대부분의 미세패턴을 위한 포토레지스트 형성공정이 ArF 레지스트를 이용하는 공정으로 전환되고 있으며, 식각공정에서도 2um 이상의 딥콘택(Deep Contact) 형성기술이 요구되고 있다. 이하, 대표적인 딥콘택 형성공정인 스토리지노드홀(storage node hole) 형성공정을 일례로 종래기술에 대하여 설명한다. Recently, as semiconductor devices, for example, DRAMs, have been highly integrated, photoresist forming processes for most fine patterns have been converted to ArF resist processes, and deep contact formation techniques of 2 μm or more are required in the etching process. It is becoming. Hereinafter, the prior art will be described as an example of a storage node hole forming process, which is a typical deep contact forming process.

도 1a 내지 도 1c는 종래기술에 따른 반도체 장치의 제조방법을 도시한 공정단면도이다. 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도 1a에 도시된 바와 같이, 스토리지노드콘택플러그(12)가 형성된 기판(11) 상에 식각정지막(13), 분리절연막(14) 및 하드마스크패턴(15)을 순차적으로 형성한다. 여기서, 반도체 장치의 집적도가 증가함에 따라 하드마스크패턴(15)은 고집적화된 반도체 장치가 요구하는 선폭(또는 직경)을 제공하기 위해 더블패터닝(DPT LLE 또는 DPT LELE) 또는 스페이서패터닝(Pillar SPT)등의 방법을 사용하여 형성함과 동시에 충분한 식각마진을 제공하기 위하여 폴리실리콘막으로 형성한다.As illustrated in FIG. 1A, the etch stop layer 13, the isolation insulating layer 14, and the hard mask pattern 15 are sequentially formed on the substrate 11 on which the storage node contact plug 12 is formed. Here, as the degree of integration of the semiconductor device increases, the hard mask pattern 15 may be double-patterned (DPT LLE or DPT LELE) or spacer patterned (Pillar SPT) to provide the line width (or diameter) required by the highly integrated semiconductor device. It is formed using a method of polysilicon film to provide a sufficient etching margin at the same time.

도 1b에 도시된 바와 같이, 하드마스크패턴(15)을 식각장벽으로 분리절연막(14) 및 식각정지막(13)을 순차적으로 식각하여 스토리지노드콘택플러그(12)를 노출시키는 스토리지노드홀(16)을 형성한다. As shown in FIG. 1B, the storage insulating layer 16 exposes the storage node contact plug 12 by sequentially etching the isolation insulating layer 14 and the etch stop layer 13 using the hard mask pattern 15 as an etch barrier. ).

도 1c에 도시된 바와 같이, 하드마스크패턴(15)을 제거한다. 구체적으로, 폴리실리콘막으로 이루어진 하드마스크패턴(15)은 전면식각공정을 통해 제거한다. As shown in FIG. 1C, the hard mask pattern 15 is removed. Specifically, the hard mask pattern 15 made of a polysilicon film is removed through a front etching process.

하지만, 종래기술에서는 하드마스크패턴(15)을 폴리실리콘막으로 형성하기 때문에 하드마스크패턴(15)을 제거하기 위하여 식각공정 예컨대, 전면식각공정을 진행해야만 한다. 이로 인하여, 하드마스크패턴(15)을 제거하는 과정에서 스토리지노드홀(16)의 프로파일(Profile)이 열화되는 문제점이 발생한다. However, in the related art, since the hard mask pattern 15 is formed of a polysilicon film, an etching process, for example, an entire surface etching process must be performed to remove the hard mask pattern 15. As a result, a problem arises in that the profile of the storage node hole 16 is degraded in the process of removing the hard mask pattern 15.

또한, 종래기술에서 스토리지노드콘택플러그(12)를 폴리실리콘막으로 형성한 경우에는 하드마스크패턴(15)을 제거하는 과정에서 스토리지노드콘택플러그(12)가 손상(또는 손실)되는 문제점이 발생한다.
In addition, in the prior art, when the storage node contact plug 12 is formed of a polysilicon layer, the storage node contact plug 12 may be damaged (or lost) in the process of removing the hard mask pattern 15. .

본 발명은 상기한 종래기술의 문제점을 해결하기 위하여 제안된 것으로, 하드마스크패턴을 제거하는 과정에서 기형성된 오픈영역의 프로파일이 열화되는 것을 방지할 수 있는 반도체 장치 제조방법을 제공하는데 그 목적이 있다. SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method of manufacturing a semiconductor device which can prevent the deterioration of a profile of an open area that is formed in the process of removing a hard mask pattern. .

상기 목적을 달성하기 위한 일 측면에 따른 본 발명은 기판상에 절연막을 형성하는 단계; 상기 절연막 상에 하드마스크패턴을 형성하는 단계; 상기 하드마스크패턴을 식각장벽으로 상기 절연막을 식각하여 오픈영역을 형성하는 단계; 상기 오픈영역의 내부를 매립하는 희생막을 형성하는 단계; 전면식각공정을 실시하여 상기 하드마스크패턴을 제거하는 단계; 및 상기 희생막을 제거하는 단계를 포함하는 반도체 장치 제조방법을 제공한다.
According to an aspect of the present invention, there is provided a method of forming an insulating film on a substrate; Forming a hard mask pattern on the insulating layer; Forming an open region by etching the insulating layer using the hard mask pattern as an etch barrier; Forming a sacrificial layer filling the inside of the open region; Performing a front surface etching process to remove the hard mask pattern; And removing the sacrificial layer.

상술한 과제 해결 수단을 바탕으로 하는 본 발명은, 전면식각공정을 실시하여 하드마스크패턴을 제거하는 과정에서 오픈영역을 매립하는 희생막으로 인해 오픈영역의 프로파일이 열화되는 것을 방지할 수 있는 효과가 있다.
The present invention based on the above-described problem solving means, the effect of preventing the degradation of the profile of the open area due to the sacrificial film to fill the open area in the process of removing the hard mask pattern by performing a front-side etching process have.

도 1a 내지 도 1c는 종래기술에 따른 반도체 장치의 제조방법을 도시한 공정단면도.
도 2a 내지 도 2e는 본 발명의 일실시예에 따른 반도체 장치 제조방법을 도시한 공정단면도. 1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.
2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

이하 본 발명이 속하는 기술분야에서 통상의 지식을 가진자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부도면을 참조하여 설명하기로 한다. 후술할 본 발명은 딥콘택(Deep Contact)을 구비한 반도체 장치를 제조함에 있어서, 폴리실리콘막으로 이루어진 하드마스크패턴을 제거하는 과정에서 기형성된 오픈영역의 프로파일이 열화되는 것을 방지할 수 있는 반도체 장치 제조방법을 제공한다. 이를 위해, 본 발명은 하드마스크패턴을 제거하기 이전에 기형성된 오픈영역 내부를 희생막으로 매립한 이후에 하드마스크패턴을 제거하는 것을 기술사상으로 한다. 이하, 본 발명의 일실시예에서는 대표적인 딥콘택인 스토리지노드홀 형성공정에 본 발명의 기술사상을 적용한 경우를 예시하여 설명한다.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. The present invention to be described later, in manufacturing a semiconductor device having a deep contact (Deep Contact), a semiconductor device capable of preventing the deterioration of the profile of the pre-formed open region in the process of removing the hard mask pattern made of a polysilicon film It provides a manufacturing method. To this end, the present invention has a technical concept of removing the hard mask pattern after filling the inside of the pre-formed open area with a sacrificial layer before removing the hard mask pattern. Hereinafter, one embodiment of the present invention will be described by illustrating the case where the technical idea of the present invention is applied to a storage node hole forming process, which is a representative deep contact.

도 2a 내지 도 2e는 본 발명의 일실시예에 따른 반도체 장치 제조방법을 도시한 공정단면도이다. 2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 2a에 도시된 바와 같이, 소정의 구조물 예컨대, 스토리지노드콘택플러그(32)가 형성된 기판(31)을 준비한다. 이때, 스토리지노드콘택플러그(32)는 폴리실리콘막으로 포함할 수 있다. As shown in FIG. 2A, a substrate 31 having a predetermined structure, for example, a storage node contact plug 32 is prepared. In this case, the storage node contact plug 32 may include a polysilicon layer.

다음으로, 기판(31) 상에 식각정지막(33) 및 분리절연막(36)을 순차적으로 형성한다. 식각정지막(33)은 분리절연막(36)과 식각선택비를 갖는 물질로 형성할 수 있으며, 분리절연막(36)은 후속 공정을 통해 형성될 스토리지노드홀이 요구하는 높이를 안정적으로 제공하기 위해 제1절연막(34)과 제2절연막(35)이 적층된 적층막으로 형성할 수 있다. 일례로, 식각정지막(33)은 실리콘질화막(Si3N4)으로 형성할 수 있고, 분리절연막(36)은 산화막 예컨대, 제1절연막(34)은 PSG(Phosphorus Silicate Glass)로 형성할 수 있고, 제2절연막(35)은 PETEOS(Plasma Enhanced Tetra Ethyle Ortho Silicate)로 형성할 수 있다. Next, the etch stop film 33 and the isolation insulating film 36 are sequentially formed on the substrate 31. The etch stop layer 33 may be formed of a material having an etch selectivity with the isolation insulating layer 36, and the isolation insulating layer 36 may be stably provided to provide a height required by the storage node hole to be formed through a subsequent process. The first insulating film 34 and the second insulating film 35 may be formed as a stacked film. For example, the etch stop layer 33 may be formed of silicon nitride (Si 3 N 4 ), and the isolation insulating layer 36 may be formed of an oxide layer, for example, the first insulating layer 34 may be formed of Phosphorus Silicate Glass (PSG). The second insulating layer 35 may be formed of Plasma Enhanced Tetra Ethyle Ortho Silicate (PETOS).

다음으로, 분리절연막(36) 상에 하드마스크패턴(37)을 형성한다. 이때, 반도체 장치의 집적도가 증가함에 따라 하드마스크패턴(37)은 고집적화된 반도체 장치가 요구하는 선폭(또는 직경)을 제공하기 위해 더블패터닝(DPT LLE 또는 DPT LELE, 'L'은 리소그라피공정, 'E'는 식각공정) 또는 스페이서패터닝(Pillar SPT)등의 방법을 사용하여 형성함과 동시에 분리절연막(36)을 식각하는 동안 충분한 식각마진을 제공하기 위하여 폴리실리콘막(Poly-Si)으로 형성한다. 참고로, 폴리실리콘막은 일반적으로 하드마스크로 많이 사용되는 비정질탄소막(Amorphous Carbon Layer, ACL)보다 우수한 식각마진을 제공한다. Next, a hard mask pattern 37 is formed on the isolation insulating film 36. At this time, as the degree of integration of the semiconductor device increases, the hard mask pattern 37 may provide double patterning (DPT LLE or DPT LELE, 'L' is a lithography process, to provide the line width (or diameter) required by the highly integrated semiconductor device. E 'is formed using a method such as an etching process or spacer patterning (Pillar SPT) and at the same time is formed of a polysilicon film (Poly-Si) to provide a sufficient etching margin during the etching of the isolation insulating film 36 . For reference, the polysilicon film provides an etching margin superior to that of an amorphous carbon layer (ACL), which is generally used as a hard mask.

도 2b에 도시된 바와 같이, 하드마스크패턴(37)을 식각장벽(etch barrier)으로 분리절연막(36) 및 식각정지막(33)을 순차적으로 식각하여 스토리지노드콘택플러그(32)를 노출시키는 오픈영역 즉, 스토리지노드홀(38)을 형성한다. As illustrated in FIG. 2B, the isolation mask 36 and the etch stop layer 33 are sequentially etched using the hard mask pattern 37 as an etch barrier to expose the storage node contact plug 32. The region, that is, the storage node hole 38 is formed.

도 2c에 도시된 바와 같이, 스토리지노드홀(38)을 매립하도록 기판(31) 전면에 희생막(39)을 형성한 후에 평탄화공정을 실시하여 적어도 하드마스크패턴(37)의 상부면을 노출시킨다. 이때, 평탄화공정은 화학적기계적연마법 또는 에치백으로 실시할 수 있다. As shown in FIG. 2C, after the sacrificial layer 39 is formed on the entire surface of the substrate 31 to fill the storage node hole 38, a planarization process is performed to expose at least an upper surface of the hard mask pattern 37. . In this case, the planarization process may be performed by chemical mechanical polishing or etch back.

희생막(39)은 고종횡비(high aspect ratio)를 갖는 스토리지노드홀(38)을 안정적으로 매립하기 위해 유동성절연막으로 형성하는 것이 바람직하다. 일례로, 희생막(39)은 스핀온절연막(Spin On Dielectric, SOD) 또는 스핀온카본막(Spin On Carbon, SOC)으로 형성할 수 있다. 참고로, 유동성절연막으로 이루어진 희생막(39)은 스핀코팅법을 이용하여 기판(31) 전면에 절연물질을 도포한 다음, 도포된 절연물질을 경화시키는 일련의 공정과정을 통해 형성할 수 있다. The sacrificial layer 39 is preferably formed of a flowable insulating layer in order to reliably fill the storage node hole 38 having a high aspect ratio. For example, the sacrificial layer 39 may be formed of a spin on dielectric (SOD) or spin on carbon (SOC) layer. For reference, the sacrificial film 39 formed of a flowable insulating film may be formed through a series of processes in which an insulating material is coated on the entire surface of the substrate 31 by using a spin coating method, and then the applied insulating material is cured.

희생막(39)은 하드마스크패턴(37) 및 분리절연막(36)과 식각선택비를 갖는 물질로 형성하는 것이 바람직하다. 일례로, 하드마스크패턴(37)을 폴리실리콘막으로 형성하고, 분리절연막(36)을 산화막으로 형성한 경우에 희생막(39)은 스핀온카본막으로 형성할 수 있다. The sacrificial layer 39 may be formed of a material having an etching selectivity with the hard mask pattern 37 and the isolation insulating layer 36. For example, when the hard mask pattern 37 is formed of a polysilicon film, and the isolation insulating film 36 is formed of an oxide film, the sacrificial film 39 may be formed of a spin-on carbon film.

도 2d에 도시된 바와 같이, 전면식각공정 예컨대, 에치백을 실시하여 하드마스크패턴(37)을 제거한다. 이때, 폴리실리콘막으로 이루어진 하드마스크패턴(37)을 전면식각공정으로 제거하는 이유는 일반적으로 하드마스크로 많이 사용되는 비정질탄소막과 같이 스트립공정을 통해 제거할 수 없기 때문이다. As shown in FIG. 2D, the hard mask pattern 37 is removed by performing an etch back, for example, an entire surface etching process. In this case, the reason why the hard mask pattern 37 made of the polysilicon film is removed by the front etching process is that it cannot be removed through the strip process like the amorphous carbon film which is generally used as a hard mask.

전면식각공정을 통해 하드마스크패턴(37) 제거공정시 희생막(39)으로 인해 스토리지노드홀(38)의 프로파일이 열화되는 것을 방지할 수 있다. 아울러, 스토리지노드콘택플러그(32)가 손상(또는 손실)되는 것도 방지할 수 있다. It is possible to prevent the profile of the storage node hole 38 from being deteriorated by the sacrificial layer 39 during the hard mask pattern 37 removing process through the front surface etching process. In addition, the storage node contact plug 32 may be prevented from being damaged (or lost).

도 2e에 도시된 바와 같이, 희생막(39)을 제거한다. 희생막(39)은 건식 또는 습식으로 제거할 수 있으며, 희생막(39)을 구성하는 물질에 따라 제거방법을 선택할 수 있다. 일례로, 희생막(39)을 스핀온절연막으로 형성한 경우에는 BOE(Buffered Oxide Etchant) 또는 불산용액(HF)을 이용한 습식공정으로 제거할 수 있고, 스핀온카본막으로 형성한 경우에는 산소플라즈마(O2 plasma)를 이용한 건식공정으로 제거할 수 있다. As shown in FIG. 2E, the sacrificial layer 39 is removed. The sacrificial film 39 may be removed in a dry or wet manner, and a removal method may be selected according to a material forming the sacrificial film 39. For example, when the sacrificial layer 39 is formed as a spin-on insulating layer, the sacrificial layer 39 may be removed by a wet process using BOE (Buffered Oxide Etchant) or hydrofluoric acid solution (HF). Can be removed by a dry process using (O 2 plasma).

상술한 본 발명의 일실시예에 따르면, 전면식각공정을 통해 하드마스크패턴(37)을 제거하는 과정에서 스토리지노드홀(38)을 매립하는 희생막(39)으로 인해 스토리지노드홀(38) 프로파일의 열화되는 것을 방지할 수 있다. 아울러, 희생막(39)으로 인해 스토리지노드콘택플러그(32)가 손상되는 것을 방지할 수 있다.
According to an embodiment of the present invention, the storage node hole 38 profile due to the sacrificial layer 39 filling the storage node hole 38 in the process of removing the hard mask pattern 37 through the front surface etching process. Can be prevented from deteriorating. In addition, the sacrificial layer 39 may prevent the storage node contact plug 32 from being damaged.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기 실시예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술분야의 통상의 전문가라면 본 발명의 기술사상의 범위내의 다양한 실시예가 가능함을 이해할 수 있을 것이다.
The technical idea of the present invention has been specifically described according to the above preferred embodiments, but it should be noted that the above embodiments are intended to be illustrative and not restrictive. In addition, it will be understood by those of ordinary skill in the art that various embodiments within the scope of the technical idea of the present invention are possible.

31 : 기판 32 : 스토리지노드콘택플러그
33 : 식각정지막 34 : 제1절연막
35 : 제2절연막 36 : 분리절연막
37 : 하드마스크패턴 38 : 스토리지노드홀
39 : 희생막 31: substrate 32: storage node contact plug
33: etching stop film 34: first insulating film
35: second insulating film 36: separation insulating film
37: hard mask pattern 38: storage node holes
39: sacrifice

Claims (10)

기판상에 절연막을 형성하는 단계;
상기 절연막 상에 하드마스크패턴을 형성하는 단계;
상기 하드마스크패턴을 식각장벽으로 상기 절연막을 식각하여 오픈영역을 형성하는 단계;
상기 오픈영역의 내부를 매립하는 희생막을 형성하는 단계;
전면식각공정을 실시하여 상기 하드마스크패턴을 제거하는 단계; 및
상기 희생막을 제거하는 단계
를 포함하는 반도체 장치 제조방법.
Forming an insulating film on the substrate;
Forming a hard mask pattern on the insulating layer;
Forming an open region by etching the insulating layer using the hard mask pattern as an etch barrier;
Forming a sacrificial layer filling the inside of the open region;
Performing a front surface etching process to remove the hard mask pattern; And
Removing the sacrificial layer
≪ / RTI >
제1항에 있어서,
상기 기판에 형성된 도전막을 더 포함하고,
상기 오픈영역은 상기 도전막을 노출시키도록 형성하는 반도체 장치 제조방법.
The method of claim 1,
Further comprising a conductive film formed on the substrate,
And the open region is formed to expose the conductive film.
제2항에 있어서,
상기 도전막은 상기 하드마스크패턴과 동일한 물질로 이루어진 반도체 장치 제조방법.
The method of claim 2,
The conductive film is a method of manufacturing a semiconductor device made of the same material as the hard mask pattern.
제1항에 있어서,
상기 하드마스크패턴은 폴리실리콘막을 포함하는 반도체 장치 제조방법.
The method of claim 1,
The hard mask pattern includes a polysilicon layer.
제1항에 있어서,
상기 하드마스크패턴을 제거하는 단계는,
에치백을 사용하여 실시하는 반도체 장치 제조방법.
The method of claim 1,
Removing the hard mask pattern,
A semiconductor device manufacturing method performed using an etch back.
제1항에 있어서,
상기 희생막을 형성하는 단계는,
상기 오픈영역을 매립하도록 상기 기판 전면에 희생막을 형성하는 단계; 및
평탄화공정을 실시하여 상기 하드마스크패턴을 노출시키는 단계
를 포함하는 반도체 장치 제조방법.
The method of claim 1,
Forming the sacrificial layer,
Forming a sacrificial layer on the entire surface of the substrate to fill the open region; And
Exposing the hard mask pattern by performing a planarization process
≪ / RTI >
제6항에 있어서,
상기 평탄화공정은 화학적기계적연마법 또는 에치백을 사용하여 실시하는 반도체 장치 제조방법.
The method of claim 6,
And the planarization step is performed using chemical mechanical polishing or etch back.
제1항에 있어서,
상기 희생막은 유동성절연막을 포함하는 반도체 장치 제조방법.
The method of claim 1,
The sacrificial film includes a flowable insulating film.
제1항에 있어서,
상기 희생막은 상기 절연막 및 상기 하드마스크패턴과 식각선택비를 갖는 물질로 형성하는 반도체 장치 제조방법.
The method of claim 1,
The sacrificial layer may be formed of a material having an etch selectivity with respect to the insulating layer and the hard mask pattern.
제1항에 있어서,
상기 희생막은 스핀온절연막 또는 스핀온카본막을 포함하는 반도체 장치 제조방법. The method of claim 1,
The sacrificial film includes a spin-on insulating film or a spin-on carbon film.
KR1020100116694A 2010-11-23 2010-11-23 Method for fabricating semiconductor device KR20120055153A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100116694A KR20120055153A (en) 2010-11-23 2010-11-23 Method for fabricating semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100116694A KR20120055153A (en) 2010-11-23 2010-11-23 Method for fabricating semiconductor device

Publications (1)

Publication Number Publication Date
KR20120055153A true KR20120055153A (en) 2012-05-31

Family

ID=46270775

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100116694A KR20120055153A (en) 2010-11-23 2010-11-23 Method for fabricating semiconductor device

Country Status (1)

Country Link
KR (1) KR20120055153A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015047255A1 (en) 2013-09-25 2015-04-02 Intel Corporation Sacrificial material for stripping masking layers

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015047255A1 (en) 2013-09-25 2015-04-02 Intel Corporation Sacrificial material for stripping masking layers
KR20160058751A (en) * 2013-09-25 2016-05-25 인텔 코포레이션 Sacrificial material for stripping masking layers
EP3061123A4 (en) * 2013-09-25 2017-05-31 Intel Corporation Sacrificial material for stripping masking layers
US9916988B2 (en) 2013-09-25 2018-03-13 Intel Corporation Sacrificial material for stripping masking layers

Similar Documents

Publication Publication Date Title
TW200537609A (en) Method for fabricating semiconductor device with recessed channel region
KR20120004212A (en) Method for fabricating capacitor
US6660599B2 (en) Semiconductor device having trench isolation layer and method for manufacturing the same
US20080160759A1 (en) Method for fabricating landing plug contact in semiconductor device
KR20100092241A (en) Method of manufacturing semiconductor device
KR101096230B1 (en) Method for fabricating capacitor in semiconductor device
KR20120055153A (en) Method for fabricating semiconductor device
JP2012134454A (en) Method for fabricating semiconductor device
KR100895374B1 (en) Method for manufacturing semiconductor device
KR20060131144A (en) Method for forming contact plug in semiconductor device
KR100607651B1 (en) Method for manufacturing capacitor
KR100670652B1 (en) Method of forming contact plug for semiconductor device
KR20120003692A (en) Method for manufacturing semiconductor device with buried gate
KR100772077B1 (en) A method for forming contact hole of semiconductor device
KR100567872B1 (en) Method for forming isolation layer in a semiconductor manufacturing device
KR20080029565A (en) Method for forming contact plug in semiconductor device
KR100359165B1 (en) Method for forming capacitor of semiconductor device
KR100529379B1 (en) Method for manufacturing capacitor in secmiconductor device
KR101145386B1 (en) Method for fabricating buried gate in semiconductor device
KR100819674B1 (en) Method for forming semiconductor devices
KR100413043B1 (en) Gate electrode formation method of semiconductor device
KR100857853B1 (en) Semiconductor device in capacitor and method for fabricating the same
KR100785862B1 (en) Method for forming gate electrode and sidewall spacer using damascene
KR20000044948A (en) Method for manufacturing trench of semiconductor device
JP2008263017A (en) Manufacturing method of semiconductor device

Legal Events

Date Code Title Description
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid