KR20120053824A

KR20120053824A - Power semiconductor device and manufacturing method thereof

Info

Publication number: KR20120053824A
Application number: KR1020100115139A
Authority: KR
Inventors: 이승철
Original assignee: (주) 트리노테크놀로지
Priority date: 2010-11-18
Filing date: 2010-11-18
Publication date: 2012-05-29

Abstract

PURPOSE: A power semiconductor device and a manufacturing method thereof are provided to improve forward direction operating properties by forming effective current flow through concentration difference which is increased when diffusing a hole carrier. CONSTITUTION: A semiconductor device has an anode region including a metal electrode. A metal electrode(80) is selectively touched with a first conductivity type ion region so that a conductive region and a non-conductive region are alternated. The metal electrode is finitely formed in the conductive region only. An insulating layer which is selectively etched is formed between the first conductivity type ion region and the metal electrode. The conductive region is formed by connected the first conductivity type ion region with the metal electrode in a region in which the insulating layer is eliminated.

Description

Power semiconductor device and manufacturing method thereof

The present invention relates to a power semiconductor device having a structure in which a metal electrode is selectively brought into contact with a collector region or an anode region, and a manufacturing method thereof.

Power semiconductor devices are an important element in the application of power electronic circuits, and power semiconductor devices are developed to meet the diverse needs of various industries (eg high insulation voltage, low conduction loss, low switching loss, high reliability, etc.). It is becoming. For example, power semiconductor devices including insulated gate bipolar transistors (IGBTs), power metal-oxide-semiconductor field effect transistors (power MOSFETs), and various types of thyristors continue to develop in response to such demands.

The bipolar operation of the power semiconductor device (i.e., the operation of flowing current due to the injection of a hole carrier generated in the P-type region P-bonded) guarantees a high current transfer capability and thus the power semiconductor. Various devices are used in the field where high voltage and high current are required.

The forward operation characteristic according to the bipolar operation of the power semiconductor device is determined by how easily the hole carrier injection from the P-type region to the N-type region occurs. Therefore, increasing the injection rate of the hole carrier is an important factor for improving the forward characteristics. That is, when the IGBT has a higher hole carrier injection ratio in the collector P-type region and in the case of a diode, the P-type region of the anode, superior device characteristics can be obtained.

Recently, due to the limitation of development technology, the ion implantation rate of the P-type collector region has become an important issue.

Early IGBTs were fabricated with a PT (Punch-through) type structure using wafers with N-type epitaxial growth on a P-type substrate, but recently, NPT (Non-punch) for cost reduction and device performance improvement. It is manufactured in the structure of -through) or FS (Field stop) type.

For reference, unlike the initial PT type IGBT, the NPT type IGBT and the FS type IGBT process the wafer thinly, and then implant P-type ions into the back of the substrate and heat-treat them to form a P-type collector region. Form an area.

The formation of the P-type collector region by ion implantation contributed to the improvement of device characteristics by controlling the injection amount of the hole carriers. In general, the formation of the P-type collector region occurs after the front side process and the wafer grinding process.

However, since the metal for emitter electrode already exists in the front surface during the heat treatment process for activating the implanted ions, the heat treatment temperature should be proceeded at about 400 ~ 450 ° C., which is lower than the melting point of the metal existing on the front surface. As a result, it is not possible to obtain a sufficient temperature to activate the implanted ions, resulting in only a very small amount (less than about 1%) of impurities being activated.

Therefore, there is a limit to increasing the concentration of the P-type collector region in a limited amount of implantable ions, thereby limiting the collector's ion implantation ability, and thus the power used in applications requiring a lower operating voltage. There is a difficulty in manufacturing a semiconductor device.

The above-described background technology is technical information that the inventor holds for the derivation of the present invention or acquired in the process of deriving the present invention, and can not necessarily be a known technology disclosed to the general public prior to the filing of the present invention.

An object of the present invention is to provide a power semiconductor device having improved forward operating characteristics to have a lower operating voltage and a method of manufacturing the same.

The present invention also provides a power semiconductor device having a higher hole carrier injection rate in a collector region in the case of an IGBT and an anode region in the case of a diode and a method of manufacturing the same.

Other objects of the present invention will be readily understood through the following description.

According to an aspect of the present invention, a semiconductor device having an anode region formed to contact a first conductivity type ion region and a metal electrode, the semiconductor device comprising: the first conductivity type ion region; And the metal electrode formed to selectively contact the first conductivity-type ion region such that a conductive region and a non-conductive region are alternately provided.

The metal electrode may be limitedly formed only in the conductive region.

Alternatively, by forming an insulating film selectively etched between the first conductive ion region and the metal electrode, the first conductive ion region and the metal electrode are connected in the region where the insulating film is removed to form the conductive region. Can be formed.

Alternatively, by forming a damage region layer in which ohmic contact is not formed in a part of the first conductivity type ion region, the contacted first conductivity type ion region and the metal electrode are other than the damage region layer. Only the conductive region may be formed.

The semiconductor device may be at least one of a vertical insulated gate bipolar transistor (vertical IGBT) and a horizontal insulated gate bipolar transistor (lateral IGBT), and the anode region may be a collector region.

The semiconductor device may be at least one of a diode and a thyristor.

The semiconductor device may be at least one of a vertical bipolar transistor and a horizontal bipolar transistor, and the anode region may be an emitter region.

The metal electrode and the first conductivity type ion region may be in contact with each other to have an arbitrary contact ratio within a range of more than 0% and 80% or less of the entire length of the first conductivity type ion region.

The first conductivity type ion region may be a P type ion region or an N type ion region.

According to another aspect of the present invention, a method of manufacturing a semiconductor device having an anode region formed so that the first conductivity type ion region and the metal electrode is in contact, comprising: forming the first conductivity type ion region; And forming the metal electrode in selective contact with the first conductivity type ion region such that a conductive region and a non-conductive region are alternated.

The metal electrode may be limitedly formed only in the conductive region.

The forming of the metal electrode may include forming an insulating layer to be in contact with the first conductivity type ion region; Selectively etching the insulating film to form the conductive region; And depositing the metal electrode on the exposed surface of the first conductive type ion region and the insulating layer such that the conductive region is formed only through the first conductive type ion region exposed by the etching of the insulating layer. .

The forming of the metal electrode may include forming a damaged region layer on which a ohmic contact is not made on a portion of the first conductivity type ion region; And depositing the metal electrode on the exposed surface of the first conductivity type ion region and the damage region layer, wherein the contacted first conductivity type ion region and the metal electrode are other than the damage region layer. Only the conductive region can be formed.

The semiconductor device may be at least one of a diode and a thyristor.

Other aspects, features, and advantages will become apparent from the following drawings, claims, and detailed description of the invention.

According to an embodiment of the present invention, a power semiconductor device having improved forward operating characteristics to have a lower operating voltage may be provided.

In addition, in the case of the IGBT, in the collector region, and in the case of the diode, the hole carrier injection rate may be higher.

1 shows an embodiment of an insulated gate bipolar transistor (IGBT) according to the prior art.
2 illustrates an embodiment of an insulated gate bipolar transistor (IGBT) in accordance with one embodiment of the present invention.
3A to 3C are graphs comparing hole carrier distribution between an insulated gate bipolar transistor according to the prior art and an insulated gate bipolar transistor according to an embodiment of the present invention.
4A and 4B are graphs comparing the on-state voltage Vcesat of the IGBT according to the contact ratio between the collector metal electrode and the collector region.
5 to 8B are diagrams each showing an embodiment of a power semiconductor device according to other embodiments of the present invention.
9A to 9C are flowcharts illustrating a method of manufacturing a power semiconductor device according to embodiments of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention is capable of various modifications and various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. It is to be understood, however, that the invention is not to be limited to the specific embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

If an element such as a layer, region or substrate is described as being on or "onto" another element, the element may be directly above or directly above another element and There may be intermediate or intervening elements. On the other hand, if one element is mentioned as being "directly on" or extending "directly onto" another element, no other intermediate elements are present. In addition, when one element is described as being "connected" or "coupled" to another element, the element may be directly connected to or directly coupled to another element, or an intermediate intervening element may be present. have. On the other hand, when one element is described as being "directly connected" or "directly coupled" to another element, no other intermediate element exists.

"Below" or "above" or "upper" or "lower" or "horizontal" or "lateral" or "vertical" Relative terms such as "vertical" may be used herein to describe a relationship of one element, layer or region to another element, layer or region, as shown in the figures. It is to be understood that these terms are intended to encompass other directions of the device in addition to the orientation depicted in the figures.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, hereinafter, the following description will be mainly focused on the insulated gate bipolar transistor (IGBT) and the case of the diode (Diode) will be briefly described. Of course. In addition, the following description will be mainly focused on an insulated gate bipolar transistor (IGBT) having a planar gate structure, but the technical concept of the present invention may be similarly applied or extended to an insulated gate bipolar transistor having a trench gate structure. It can be natural.

In addition, hereinafter, the description will focus on the P-type collector region or the P-type region of the anode, but the same technical concept may be applied to the case where the P-type ion region is an IGBT or a diode device replaced with an N-type ion region. Of course it can.

1 is a diagram illustrating an embodiment of an insulated gate bipolar transistor (IGBT) according to the prior art.

Referring to FIG. 1, the P type well 35 is formed on the N type drift region 30 by a P type ion implantation and diffusion process. In the P type well 35, an emitter region 40 having an N conductivity type is formed to be exposed to the upper surface of the semiconductor substrate. The emitter region 40 may be formed by selectively implanting and diffusing conductive N-type ions opposite to the P-type well 35 in a region of the upper surface of the P-type well 35. Here, the emitter region 40 may be formed to have a higher impurity concentration than the N-type drift region 30.

The gate electrode 50 is disposed so as to be electrically insulated from and opposed to the N-type drift region 30, the P-type well 35, and the emitter region 40 positioned below. The gate insulating layer 55 is formed under the gate electrode 50 so that the gate electrode 50 is electrically insulated from the emitter region 40 and the like. In addition, an interlayer insulating film is formed to cover the top and side surfaces of the gate electrode 50 so that the gate electrode 50 is electrically insulated from the emitter metal electrode 70.

An emitter metal electrode 70 is then formed over the interlayer insulating film, and the emitter metal electrode 70 is electrically connected to the emitter region 40 and the P-type well 35 at the bottom.

In addition, an N-conductive field stop layer 20 and a P-type collector region 10 are formed below the N-type drift region 30, respectively. The field stop layer 20 suppresses the depletion layer from extending into the P-type collector region 10. The collector metal electrode 80 is formed under the P-type collector region 10.

In general, NPT (Non-punch-through) type or FS (Field stop) type IGBT, after completing the upper MOS (Metal Oxide Semiconductor) structure, thin wafer is processed and P-type collector region through ion implantation and heat treatment process Next, metal is deposited on the rear surface to form an electrode.

In this case, as shown in FIG. 1, the collector region on the rear surface is formed through an ion implantation process and a metal deposition process without a special pattern.

Since the process of forming the P-type collector region on the back side has to be performed in a situation where a metal electrode (for example, an emitter metal electrode) is present on the front side in the process sequence, the application temperature of the heat treatment process is inevitably limited. That is, a heat treatment process for activating P-type implanted ions at a temperature of about 400 to 450 ° C., which is a temperature at which a metal electrode (for example, an aluminum electrode) existing on the front surface does not melt, is performed.

However, at such a temperature, the implanted P-type ions cannot be sufficiently activated to form a high concentration P-type collector region, and thus there is a limit in that a power semiconductor device having a low operating voltage cannot be manufactured.

2 is a diagram illustrating an embodiment of an insulated gate bipolar transistor (IGBT) according to an embodiment of the present invention, and FIGS. 3A to 3C are diagrams illustrating an insulated gate bipolar transistor according to the prior art and an insulator according to an embodiment of the present invention. 4A and 4B are comparisons of the on-state voltage Vcesat of the IGBT according to the contact ratio between the collector metal electrode and the collector region. It is a graph.

Since the structure of the IGBT shown in FIG. 2 is similar to that of the IGBT described above with reference to FIG. 1, the description of the same matters is omitted.

Referring to FIG. 2, an N conductivity type field stop layer 20 and a P type collector region 10 are formed below the N type drift region 30, respectively. A collector metal electrode 80 is formed under the P-type collector region 10 by depositing a metal electrode to expose a portion of the P-type collector region 10. That is, the P-type collector region 10 and the collector metal electrode 80 are selectively contacted (that is, the collector metal electrode 80 contacts only a part of the P-type collector region 10), which is described above with reference to FIG. 1. It is different from the contact form of the P-type collector region 10 and the collector metal electrode 80 described with reference.

Such a structure may be formed by, for example, a lift-off process or a partial etching process after depositing a metal electrode as a whole.

As such, when the P-type collector region 10 and the collector metal electrode 80 are selectively contacted, in the IGBT of the general structure described with reference to FIG. 1, current flows uniformly through the electrode bonded to the rear surface. In the IGBT according to the present embodiment, the current bottleneck occurs because the current flows only through a part of the region where the electrode is formed.

Therefore, as shown in (b) of FIG. 3A, the density of the hole carriers increases around the region in which the electrode is present, and the relatively high hole carrier concentration is maintained in the P-type collector region 10 to increase during diffusion of the hole carriers. This difference in concentration allows for more efficient current flow. This effect can solve the problem of an increase in the forward operating voltage due to the low concentration of the P-type collector region 10, it is possible to implement a lower operating voltage.

3A to 3C are graphs comparing the hole carrier distribution between the insulated gate bipolar transistor according to the prior art and the insulated gate bipolar transistor according to the embodiment of the present invention. For reference, (a) of FIG. 3a shows a hole carrier distribution in the P-type collector region 10 of the IGBT according to the prior art shown in FIG. 1, and (b) is of the present embodiment shown in FIG. The hole carrier distribution in the P-type collector region 10 of IGBT 1 is shown. In addition, simulation results of the hole carrier distribution of the cross section taken along line AA ′ of FIG. 3A to confirm the hole carrier density difference in each situation are shown in FIG. 3B, and it is cut along line BB ′ of FIG. 3A. Simulation results for the hole carrier distribution of the cross section are shown in FIG. 3C. 3B and 3C, reference numeral 210 denotes a hole carrier distribution of the IGBT according to the prior art, and reference numeral 220 denotes a hole carrier distribution of the IGBT according to the present embodiment.

As shown in FIG. 3B, it can be seen that the density of the high hole carrier is formed at the portion while the current is concentrated and flows from the portion where the electrode is not present to the edge portion of the electrode.

For this reason, referring to FIG. 3C where the distribution of hole carriers in the vertical direction in the N-type drift region 30 is shown, the concentration of the hole carriers in the P-type collector region 10 is higher than that of the IGBT according to the prior art. You can see that it is quite high.

This means that the smaller the contact area between the collector metal electrode 80 and the P-type collector region 10, the higher the density of the hole carriers is in some regions of the P-type collector region 10. That is, it means that it can be easily injected into the N-type drift region 30, by using it can lower the operating voltage of the power semiconductor device.

4A and 4B show a comparison graph of the on-state voltage Vcesat of the IGBT according to the contact ratio between the collector metal electrode 80 and the collector region 10.

As shown in FIG. 4A, the contact ratio is a ratio between the length (or area) of the P-type collector region 10 and the length (or area) of the collector metal electrode 80 selectively contacting the P-type collector region 10. It can be calculated as As shown in FIG. 4B, the smaller the contact ratio is, the more effectively the magnitude of the operating voltage is confirmed. The smaller the size of the metal electrode junction is, the higher the injection rate of the hole carrier is, which improves its characteristics. However, the contact ratio should be selected in consideration of the limitations of the patterning technique and the absolute amount of current flow in the semiconductor chip, and considering the simulation results shown in FIG. have.

As described above, the improvement of the forward characteristic by selectively contacting the collector metal electrode 80 and the collector region 10 varies depending on the concentration and depth of the P-type collector region 10, but is the same in all cases. Applicants have already confirmed through the simulation and the like that the properties appear in the direction of improvement. This can simply solve the shortcomings of the low operating voltage due to the low hole injection effect that has been pointed out as a problem in the conventional IGBT.

5 to 8B are diagrams each showing an embodiment of a power semiconductor device according to other embodiments of the present invention.

FIG. 5 illustrates an IGBT in which the P-type collector region 10 and the collector metal electrode 80 are selectively contacted by the selectively etched insulating layer 410.

That is, before forming the collector metal electrode 80, the insulating film 410 is deposited under the P-type collector region 10, and the portion where the electrode is to be formed is selectively etched, and then the collector metal electrode 80 is formed on the entire back surface. By deposition, an insulated gate bipolar transistor (IGBT) in which the P-type collector region 10 and the collector metal electrode 80 are selectively contacted can be manufactured.

6 shows an IGBT in which the P-type collector region 10 and the collector metal electrode 80 are selectively contacted by forming a damaged layer 510 in a portion of the P-type collector region 10. .

That is, the ohmic portion of the P-type collector region 10 may be damaged by ion implanting particles that do not act as carriers to create a current flow in a region where an electrode is not formed, or by damaging the region by plasma treatment. contact) to form a damaged area layer 510 that is not bonded.

Subsequently, when the collector metal electrode 80 is formed below the P-type collector region 10, current flows only to a region other than the damage region layer 510, which is similar to the operation form of the IGBT described with reference to FIG. 2. Will be the same.

As such, the structure for selectively contacting the P-type collector region 10 and the collector metal electrode 80 may be commonly applied to the horizontal IGBT device as well as the vertical IGBT device described above.

That is, the collector metal electrode 80 of the horizontal IGBT according to the prior art shown in FIG. 7A is fragmented as shown in FIG. 7B so that the P-type collector region 10 and the collector metal electrode 80 are selectively contacted. In this case, the forward characteristic may be improved by increasing the amount (density) of the hole carriers in the area of the same P-type collector region 10.

As a method of forming an IGBT in which the P-type collector region 10 and the collector metal electrode 80 are selectively contacted, only a structure corresponding to FIG. 2 is illustrated in FIG. 7B. Naturally, the structure described with reference to 6 can be applied without limitation to the horizontal IGBT.

Likewise, the technical idea of the present invention can be equally applied to a manufacturing process of a diode device.

8A is a diagram illustrating a structure of a diode device according to the prior art, and FIG. 8B is a diagram illustrating a structure of a diode device to which the technical spirit of the present invention is applied.

As shown in FIG. 8A, in the diode device according to the related art, an anode metal electrode is formed on the P-type well region in an active region, so that the P-type well region and the anode metal electrode are in contact area. In total contact with.

However, as shown in FIG. 8B, in the diode device to which the technical idea of the present invention is applied, an insulating film is formed on the P-type well region, and a portion of the P-type well is selectively exposed by a partial etching process. An anode metal electrode is deposited on top so that the P-type well and the anode metal electrode are only partially in contact with the region where the insulating film is removed. In this way, the same effects as described above can be obtained in the diode device as well.

Although only the structure corresponding to FIG. 5 is illustrated in FIG. 8B as a method of forming a diode device in which the P-type region and the anode metal electrode are selectively contacted, the structure described above with reference to FIGS. 2 and 6 will be omitted. Of course, it can be applied without limitation to the manufacturing process of the diode device.

In addition, although not shown, it is a matter of course that the technical concept of the present invention may be equally applied to the emitter region of the vertical and / or horizontal bipolar transistors.

9A to 9C are flowcharts illustrating a method of manufacturing a power semiconductor device according to embodiments of the present invention.

Since the structure of the power semiconductor device according to each embodiment has been described in detail above, the following briefly describes only a method of manufacturing an anode region of the power semiconductor device.

Referring to FIG. 9A, a P-type ion region is formed in step 910 to function as an anode of a power semiconductor device.

Subsequently, the metal electrode is deposited only in a region designated as the conductive region in the anode region to selectively contact the P-type ion region and the metal electrode in step 920.

Referring to FIG. 9B, which shows another embodiment, a P-type ion region is formed in step 930 to function as an anode of a power semiconductor device.

In operation 935, an insulating layer 410 is formed on the surface of the P-type ion region. In operation 940, selective etching for partitioning the conductive region and the non-conductive region is performed on the formed insulating layer 410.

Subsequently, in step 940, a metal electrode is deposited on the exposed surfaces of the P-type ion region and the insulating layer 410 such that the insulating layer 410 is removed to directly contact the P-type ion region only in the region partitioned into the conductive region.

Referring to FIG. 9C, which shows another embodiment, a P-type ion region is formed in step 960 to function as an anode of a power semiconductor device.

In step 965, a damaged region layer 510 is formed in which some ohmic contacts are not formed. The damage region layer 510 may be formed by ion implanting particles that do not act as carriers to create a current flow in a region where an electrode is not formed in the P-type ion region, or by damaging the region through plasma treatment.

In step 970 a metal electrode is deposited on the exposed surfaces of the P-type ion region and damage region layer 510. As a result, the conductive region may be formed only in a region other than the damaged region layer 510 in contact with the P-type ion region and the metal electrode.

Although the above has been described with reference to embodiments of the present invention, those skilled in the art may variously modify the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. And can be changed.

10: P-type collector area 20: Field stop layer
30 N-type drift region 35 P-type well
40 emitter region 50 gate electrode
55 gate insulating film 70 emitter metal electrode
80 collector metal electrode 410 insulating film
510: damaged area layer

Claims

In a semiconductor device having an anode region formed to contact the first conductivity type ion region and the metal electrode,
The first conductivity type ion region; And
And the metal electrode formed to selectively contact the first conductivity type ion region such that a conductive region and a non-conductive region are alternated.

The method of claim 1,
The metal electrode is limited to only the conductive region, characterized in that the semiconductor device.

The method of claim 1,
By forming an insulating film selectively etched between the first conductive ion region and the metal electrode, the conductive region is formed by connecting the first conductive ion region and the metal electrode in a region where the insulating film is removed. A semiconductor device, characterized in that.

The method of claim 1,
By forming a damage region layer in which a ohmic contact is not made in a part of the first conductivity type ion region, the contacted first conductivity type ion region and the metal electrode are formed only in a region other than the damage region layer. A semiconductor device, characterized in that the conductive region is formed.

The method of claim 1,
The semiconductor device is one or more of a vertical insulated gate bipolar transistor (vertical IGBT) and a horizontal insulated gate bipolar transistor (lateral IGBT), wherein the anode region is a collector (collector) region.

The method of claim 1,
And the semiconductor device is one or more of a diode and a thyristor.

The method of claim 1,
The semiconductor device is at least one of a vertical bipolar transistor (vertical bipolar transistor) and a horizontal bipolar transistor (lateral bipolar transistor), characterized in that the anode region is an emitter (emitter) region.

The method of claim 1,
Wherein the metal electrode and the first conductivity type ion region are in contact with each other to have an arbitrary contact ratio within a range of more than 0% and 80% or less of the total length of the first conductivity type ion region. .

The method of claim 1,
And the first conductivity type ion region is a p-type ion region or an n-type ion region.

In the manufacturing method of a semiconductor device having an anode region formed so that the first conductivity type ion region and the metal electrode contact;
Forming the first conductivity type ion region; And
Forming the metal electrode in selective contact with the first conductivity type ion region such that a conductive region and a non-conductive region are alternated.

The method of claim 10,
The metal electrode is a method of manufacturing a semiconductor device, characterized in that formed in the conductive region limited.

The method of claim 10,
Forming the metal electrode,
Forming an insulating layer to be in contact with the first conductivity type ion region;
Selectively etching the insulating film to form the conductive region; And
Depositing the metal electrode on an exposed surface of the first conductive type ion region and the insulating layer so that the conductive region is formed only through the first conductive type ion region exposed by the etching of the insulating layer. Manufacturing method.

The method of claim 10,
Forming the metal electrode,
Forming a damaged region layer on which a ohmic contact is not made on a portion of the first conductivity type ion region; And
Depositing the metal electrode on an exposed surface of the first conductivity type ion region and the damage region layer,
And the first conductive ion region and the metal electrode in contact form the conductive region only in a region other than the damaged region layer.

The method of claim 10,
The semiconductor device is at least one of a vertical insulated gate bipolar transistor (vertical IGBT) and a horizontal insulated gate bipolar transistor (lateral IGBT), the anode region is a method of manufacturing a semiconductor device, characterized in that the collector (collector) region.

The method of claim 10,
The semiconductor device is a method of manufacturing a semiconductor device, characterized in that at least one of a diode and a thyristor.

The method of claim 10,
And the semiconductor device is at least one of a vertical bipolar transistor and a horizontal bipolar transistor, and wherein the anode area is an emitter area.

The method of claim 10,
Wherein the metal electrode and the first conductivity type ion region are in contact with each other to have an arbitrary contact ratio within a range of more than 0% and 80% or less of the total length of the first conductivity type ion region. Method of preparation.

The method of claim 10,
And the first conductivity type ion region is a p-type ion region or an n-type ion region.