KR20110138968A - Image sensor row decoder - Google Patents

Abstract

PURPOSE: An image sensor row decoder is provided to discharge a photo-charge which is accumulated to the pixel of an image sensor which is not sampled in a sub sampling. CONSTITUTION: A first logical combination unit(510) generates a middle reset gate signal by responding to an address signal and a rest signal. By responding to the address and the transmission signal, a second logical combination unit(520) generates a middle transmission gate signal. By responding to the address signal and a selection signal, a third logical combination unit(530) generates a selection gate signal. By responding to a global reset signal and the middle reset gate signal, a fourth logical combination unit(540) generates a reset gate signal. By responding to the global reset signal and the middle gate signal, a fifth logical combination unit(550) generates a transmission gate signal.

Description

Image Sensor Row Decoder {IMAGE SENSOR ROW DECODER}

The present invention relates to an image sensor row decoder, and more particularly, to an image sensor row decoder that emits photocharge of pixels during subsampling and global reset.

In general, an image sensor is an apparatus for capturing an image by using a property of a semiconductor that responds to light. The image sensor includes a pixel array having transistors and image sensing elements, such as a plurality of photodiodes, and receives light from an object to generate an electrical image signal. In particular, an image sensor manufactured using CMOS technology is called a CMOS sensor.

1 is a block diagram of a general CMOS sensor 100. Referring to this, the CMOS image sensor 100 includes a pixel array 110 for converting light energy into electrical energy, a correlated double sampling (CDS) / column decoder for removing fixed pattern noise of a pixel and decoding an address in a column direction. 120, a PGA / ADC (Analog to Digital Converter) 130 for adjusting the intensity of the analog video signal and converting the analog video signal into a digital video signal, a row decoder 140 for decoding the address in the row direction, and a row address And a row driver 150 for driving the rows of the pixel array in response to, and a controller 160 for controlling all the circuits. In the pixel array 110, pixel sensors as illustrated in FIG. 2 are arranged, and predetermined pixels in the pixel array 110 are addressed by the row decoder 140 and the column decoder 120. The PGA / ADC 130 samples the pixel data under the control of the controller 160.

2 is a block diagram of a unit pixel of a general image sensor. As shown in FIG. 2, the unit pixel 200 includes one photodiode 210 and four transistors Tx, Rx, Dx, and Sx. The four transistors emit a transfer transistor Tx for transferring the photocharge generated in the photodiode 210 to the sensing node A, and charges stored in the sensing node A for the next signal detection. Sample and hold to interface between the reset transistor Rx for reading the reference voltage level and the PGA / ADC 130 of FIG. 1 receiving the output signal from the pixel without distorting the signal generated at the pixel. and a drive transistor Dx connected to a source follower for driving and hold, and a selection transistor Sx for addressing the voltage of the pixel in units of rows. The remaining transistor LD is a load transistor driven by a bias voltage Pixel Bias.

A driving operation of the unit pixel will be described with reference to FIG. 2 as follows. First, the reset transistor Rx and the transfer transistor Tx are turned on, and then the reset transistor Rx and the transfer transistor Tx are turned off, and the selection transistor Sx is turned on to reset the reference voltage. Read. Thereafter, in order to read the photocharge generated in the photodiode 210 and transmit the photocharge to the sensing node A, the transfer transistor Tx is turned on to read the signal level. The difference between the reference voltage level and the signal level thus read becomes the output signal of the pixel corresponding to the input light for a predetermined time.

3 shows a circuit diagram of a typical row decoder. Reset gate signals RS _i , RS _{i +1} , ... of each row, transmission gate signals TF _i , TF _{i +1} , ..., select gate signals SL _i , SL _{i +1,.} ... are made of a combination of row address signals A _i , A _{i +1} , ..., a reset signal Rx, a transmission signal Tx, and a selection signal Sel. That is, when a signal for selecting a corresponding row address is applied, the transfer gate signals TF _i , TF _{i +1} , ... of the corresponding row, the reset gate signals RS _i , RS _{i +1} , ..., and The select gate signals SL _i , SL _{i +1} , ... are output. This structure can reset and read PDs sequentially, but it is not possible to reset all rows of PDs simultaneously to support the Electro Mechanical Shutter feature.

In addition, the blooming of the sub-sampling function used to increase the frame rate and reduce the output image size cannot be eliminated. For example, as shown in FIG. 4, the PD which is not accessed in the sub-sampling mode does not emit photocharges accumulated in the PD because the reset gate signal and the selection gate signal are turned off, thereby causing a blooming phenomenon. The controller can effectively control the address, transfer gate, reset gate, and select gate to release photocharges to prevent blooming, but this can affect analog CDS circuitry resulting in image degradation and access during subsampling. There is a problem in that the photocharges accumulated in the PD cannot be completely discharged because the photocharges of the PDs that do not have to be discharged within a predetermined time, and also the low address signals, Since the transmission signal and the reset signal must be additionally controlled, the control unit becomes complicated.

Embodiments of the present invention provide a row decoder for discharging photocharges during subsampling.

According to an aspect of the present invention, a first logic combining portion generates an intermediate reset gate signal in response to an address signal and a reset signal, and a second logic combining portion generates an intermediate transfer gate signal in response to an address signal and a transmission signal. A third logic combination unit for generating a selection gate signal in response to an address signal and a selection signal, and a reset gate signal in response to a global reset signal and an intermediate reset gate signal for resetting a corresponding pixel irrespective of the address signal; An image sensor row decoder includes a fourth logic combination unit generating a second logic combination unit and a fifth logic combination unit generating a transmission gate signal in response to a global reset signal and an intermediate transfer gate signal.

In one embodiment, when the unit array is not selected by the address signal, a global reset signal for resetting the corresponding pixel may be supplied.

According to another aspect of the present invention, a row decoder for addressing a plurality of pixels arranged in rows and columns in an image sensor is provided, wherein the unit array of row decoders generates an intermediate reset gate signal in response to an address signal and a reset signal. A first logic combining unit configured to generate an intermediate transfer gate signal in response to the address signal and the transmission signal, a third logic combining unit generating the selection gate signal in response to the address signal and the selection signal; A fourth logic combination unit configured to generate a reset gate signal in response to a global reset signal and an intermediate reset gate signal for resetting a corresponding pixel of the plurality of pixels irrespective of the address signal, the global reset signal and the Fifth logic to generate a transfer gate signal in response to an intermediate transfer gate signal It includes a combination.

In one embodiment, when the unit array is not selected by the address signal, a global reset signal for resetting the corresponding pixel among the plurality of pixels may be supplied.

In one embodiment, the first predetermined number of unit arrays form a group, the second predetermined number of groups form an entire array of row decoders, and the global reset signal corresponds to a first number of respective units corresponding to the unit arrays. It can be made of a signal.

In one embodiment, in a subsampling mode that samples a portion of the plurality of pixels, the global reset signal may supply a logic value at which the pixels that are not subsampled are reset to the unit array corresponding to the pixels that are not subsampled.

In one embodiment, in the global reset mode for resetting all of the plurality of pixels, the global reset signal may sequentially supply a logic value for resetting the corresponding pixel to each of the preset second number of unit arrays.

According to an exemplary embodiment of the present invention, the blooming of photocharges accumulated in pixels of an image sensor that is not sampled at the time of subsampling may be discharged to remove the blooming phenomenon, thereby improving image quality.

In addition, according to an embodiment of the present invention, the IR drop phenomenon can be prevented by reducing the number of switches that are simultaneously switched at the time of global reset.

1 is a block diagram of a general image sensor.
2 is a block diagram of a unit pixel of a general image sensor.
3 shows a circuit diagram of a typical row decoder.
4 is an operation timing diagram of a general row decoder.
5 is a circuit diagram of a unit array of an image sensor row decoder according to an embodiment of the present invention.
6 is a circuit diagram illustrating a unit array group of an image sensor row decoder according to an embodiment of the present invention.
7 is an operation timing diagram during subsampling for each group of row decoders according to an embodiment of the present invention.

Hereinafter, an image sensor row decoder according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

5 is a circuit diagram illustrating a unit array 500 of a CMOS image sensor row decoder according to an embodiment of the present invention. The unit array 500 of the row decoder includes first to fifth logic combination units 510, 520, 530, 540, and 550. In the embodiment shown in FIG. 5, the first to third logic combinations 510, 520, and 530 are shown as end gate circuits, and the fourth and fifth logic combinations 540 and 500 are as oar gate circuits. Although shown, the present invention is not limited to this, and may be made of other logic combinations.

The first logic combiner 510 generates an intermediate gate signal in response to the address signal A and the reset signal Rx. The second logic combiner 520 generates an intermediate transfer gate signal in response to the address signal A and the transmission signal Tx. The third logic combiner 530 generates the selection gate signal SL in response to the address signal A and the selection signal Sel. The fourth logic combination unit 540 generates a reset gate RS signal in response to the global reset signal GR and the intermediate reset gate signal. The fifth logic combination unit 550 generates the transfer gate signal TF in response to the global reset signal GR and the intermediate transfer gate signal. The reset gate signal RS, the transfer gate signal TF, and the selection gate signal SL are supplied to the unit pixel 200 of FIG. 2.

Referring to the operation of the row decoder, the first logic combination unit 510 receives the address signal A and the reset signal Rx and generates a logical product of these two signals as an intermediate reset gate signal. The intermediate reset gate signal is input to the fourth logic combination unit 540 together with the global reset signal GR, and the fourth logic combination unit 540 outputs the logic sum of the two input signals as the reset gate signal RS. . Therefore, when the corresponding address is selected by the address signal A and the reset signal Rx is input, or when the reset is selected by the global reset signal GR, the fourth logic combination unit 540 performs the H logic. The value is output and supplied to the corresponding unit pixel (eg, the unit pixel 200 of FIG. 2).

In addition, the second logic combiner 520 receives the address signal A and the transmission signal Tx and generates a logical product of the two signals as an intermediate transmission gate signal. The intermediate transfer gate signal is input to the fifth logic combiner 550 together with the global reset signal GR, and the fifth logic combiner 550 outputs the logical sum of the two input signals as the transfer gate signal TF. . Therefore, when the corresponding address is selected by the address signal A and the transmission signal Tx is input or when the transmission is selected by the global reset signal GR, the fifth logic combination unit 550 performs the H logic. The value is output and supplied to the corresponding unit pixel.

Meanwhile, the third logic combiner 530 receives the address signal A and the select signal Sel, generates a logical product of the two signals as the select gate signal, and supplies the resultant signal to the unit pixel 200 of FIG. 2.

As such, when the corresponding pixel is sampled, the unit pixel 500 is selected by the address signal A, and the corresponding pixel is sampled by the reset signal, the transmission signal, and the selection signal. The reset gate signal RS, the transfer gate signal TF, and the selection gate signal SL are transmitted to the corresponding pixel.

In addition, when the pixel corresponding to the unit array 500 is not sampled, the global reset signal GR for supplying photocharge without being sampled is supplied, and the reset gate is supplied by the global reset signal GR. The signal TF and the transfer gate signal TF have an H logic value so as to appropriately discharge the photocharge accumulated in the photodiode. For the pixels that are not sampled, since the selection signal Sel has an L logic value, the selection gate signal SL has an L logic value, so that a sampling operation does not occur.

6 is a circuit diagram illustrating a unit array group of a CMOS image sensor row decoder according to an embodiment of the present invention. Although the unit array group of the row decoder illustrated in FIG. 6 is illustrated as including eight unit arrays, the present invention is not limited thereto and any predetermined first number of unit arrays may form the unit array group of the row decoder. have. The predetermined first number of unit arrays may form a group as shown in FIG. 5 to perform sampling or photocharge emission on corresponding pixels by the reset signal, the transmission signal, the selection signal, and the global reset signal. .

In addition, the row decoder includes a second number of groups as shown in FIG. 6 to form an entire array of row decoders. For example, in the case of VGA (640 × 480), if a group includes eight unit arrays, a total of 60 groups are formed in the row decoder. In this case, the same reset signal, transmission signal, selection signal and global reset signal are supplied to 60 groups. Accordingly, the unit array corresponding to each group may be operated simultaneously by one global reset signal. In other words, all of the corresponding unit arrays in different groups may perform the same operation.

Meanwhile, the operation mode in the image sensor may include a sub-sampling mode for sampling only a portion of the plurality of pixels and a global reset mode for resetting all pixels of the image sensor.

The sub-sampling mode may be, for example, a mode in which only some pixels of the image sensor are sampled and displayed on the LCD screen for live view in a device such as a mobile phone or a digital camera having an image sensor. In the subsampling mode, the global reset signal supplies the unit array corresponding to the pixels that are not subsampled with a logic value at which the subsampled pixels are reset, thereby instructing photocharge emission for the pixels that are not subsampled. The reset gate signal, the transfer gate signal, and the selection gate signal are provided. The pixel operates according to the reset gate signal, the transfer gate signal, and the selection gate signal to emit photocharge of the photodiode. Thus, by causing photocharge to be emitted from the photodiode of the pixel that is not sampled in the sampling mode, the blooming phenomenon can be removed from the sampled image.

The global reset mode is a mode that emits all photocharges by resetting all the pixels as needed. In the global reset mode, in the unit array group of the row decoder, a global reset signal is provided so that the pixel corresponding to each unit array is sequentially reset without being sampled, so that the pixels corresponding to the unit array group are sequentially Can be reset.

In the global reset mode, if multiple pixels are all reset at the same time, too many switches may be switched at the same time, causing IR drops. However, the number of switches simultaneously switched can be reduced by resetting a plurality of pixels sequentially. For example, on the other hand, in the global reset mode, the number of switches simultaneously switched can be reduced by controlling the global reset signal to be 8'h01 =>8'h03=>8'h07=>8h'0f. It can effectively prevent the IR drop phenomenon.

7 illustrates an operation timing diagram during subsampling for each group of row decoders according to an embodiment of the present invention. As shown, the global reset signal is 8'b11001100, and the reset gate signal, the transfer gate signal, and the selection gate signal intended to emit photocharges are transmitted to the corresponding pixel for the pixel that is not sampled in the sub-sampling mode. Able to know.

It is intended that the present invention not be limited by the above-described embodiments and the accompanying drawings, but only by the appended claims. Accordingly, various forms of substitution, modification, and alteration may be made by those skilled in the art without departing from the scope of the claims and the technical spirit of the present invention. Will belong.

500: unit array
510: first logical combination
520: second logical combination portion
530: third logic combination
540: fourth logic combination portion
550: fifth logical combination portion

Claims (7)

A first logic combination unit generating an intermediate reset gate signal in response to the address signal and the reset signal;
A second logic combining unit generating an intermediate transfer gate signal in response to the address signal and the transmission signal;
A third logic combination unit generating a selection gate signal in response to the address signal and the selection signal;
A fourth logic combination section for generating a reset gate signal in response to a global reset signal and the intermediate reset gate signal for resetting a corresponding pixel irrespective of the address signal; And
A fifth logic combination unit generating a transmission gate signal in response to the global reset signal and the intermediate transmission gate signal;
Including,
Image Sensor Row Decoder.
The method of claim 1,
When the unit array is not selected by the address signal, the global reset signal for resetting the corresponding pixel is supplied.
Image Sensor Row Decoder.
A row decoder for addressing a plurality of pixels arranged in rows and columns in a CMOS image sensor,
The unit array of the row decoder,
A first logic combination unit generating an intermediate reset gate signal in response to the address signal and the reset signal;
A second logic combining unit generating an intermediate transfer gate signal in response to the address signal and the transmission signal;
A third logic combination unit generating a selection gate signal in response to the address signal and the selection signal;
A fourth logic combination unit generating a reset gate signal in response to a global reset signal and the intermediate reset gate signal for resetting a corresponding pixel among the plurality of pixels irrespective of the address signal; And
A fifth logic combination unit generating a transmission gate signal in response to the global reset signal and the intermediate transmission gate signal;
Including,
Image Sensor Row Decoder.
The method of claim 3,
When the unit array is not selected by the address signal, the global reset signal for supplying a corresponding pixel among the plurality of pixels is supplied.
Image Sensor Row Decoder.
The method of claim 3,
The preset first number of unit arrays form a group,
The predetermined second number of groups forms an entire array of the row decoders,
The global reset signal includes the first number of signals respectively corresponding to the unit array.
Image Sensor Row Decoder.
The method of claim 5,
In the sub-sampling mode of sampling a portion of the plurality of pixels, the global reset signal supplies a logic value at which the non-subsampled pixels are reset to a unit array corresponding to the pixels that are not subsampled,
Image Sensor Row Decoder.
The method of claim 5,
In the global reset mode for resetting all of the plurality of pixels, the global reset signal sequentially supplies a logic value for resetting the corresponding pixel to each of the predetermined second number of unit arrays of the group.
Image Sensor Row Decoder.

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