KR20110108987A - Cmos image sensor - Google Patents

Abstract

A CMOS image sensor comprising a unit pixel having a reset transistor, a transfer transistor, a selection transistor, and a photodiode, comprising: a first sample and hold portion connected to a source of the selection transistor to sample a reference voltage; A CMOS image sensor pixel is provided that includes a second sample and a hold portion coupled to sample an image signal converted photoelectrically from a photodiode, wherein the second sample and hold portion is a transfer transistor after the first sample and hold portion sample the reference voltage. The video signal is sampled while is on.

Description

CMOS image sensor {CMOS IMAGE SENSOR}

The present invention relates to a CMOS image sensor, and more particularly, to a CMOS image sensor capable of removing noise due to clock feedthrough, voltage inflow error, and charge redistribution of a transfer transistor.

In general, an image sensor is an apparatus for capturing an image by using a property of a semiconductor that responds to light. The image sensor includes a pixel array having transistors and image sensing elements, such as a plurality of photodiodes, and receives light from an object to generate an electrical image signal. In particular, an image sensor manufactured using CMOS technology is called a CMOS sensor.

The unit pixel of the CMOS sensor includes a photodiode, a transfer transistor, a reset transistor, a driving transistor, and a selection transistor. By operation of each transistor, an image signal obtained by the reference voltage and the photocharge received from the photodiode is sampled and processed into image data. do.

1 is a circuit diagram schematically illustrating a portion of a MOS switch and a floating capacitor which are reset or transfer transistors in a CMOS image sensor pixel. In FIG. 1, a MOS switch SW for outputting an input signal Vin and a sampling capacitor Cs for sampling a signal output from the MOS switch are illustrated through a switching operation in response to a control signal SAMPLE. Such a circuit has problems of clock feedthrough, charge injection error, and charge redistribution caused by using a metal oxide semiconductor (MOS) as a switch.

Clock feedthrough or charge injection error means that when the MOS transistor SW is used as a switch, the parasitic capacitance of the MOS switch SW is applied to the sampling capacitor Cs when the MOS transistor SW switches from on to off. A noise phenomenon that occurs.

In addition, charge redistribution causes the outflow of charges to the outside of the MOS switch SW when the MOS transistor SW is switched from on to off, and the discharged charges are redistributed to the source and drain sides of the MOS transistor SW1, respectively. In this case, noise may be further provided to the sampling capacitor Cs by charge redistribution.

Therefore, the amount of charge sampled in the sampling capacitor Cs may include noise components generated by clock feedthrough, charge injection error, and charge redistribution, thereby degrading the quality of the resultant image.

One embodiment of the present invention provides a CMOS image sensor capable of removing clock feedthrough, charge inflow error, and noise due to charge redistribution due to switching operations of a transmission transformer.

According to one aspect of the invention, a CMOS image sensor comprising a unit pixel having a reset transistor, a transfer transistor, a select transistor and a photodiode, comprising: a first sample and hold connected to a source of the select transistor to sample a reference voltage; And a second sample and hold portion connected to a source of a selection transistor and sampling a video signal photoelectrically converted by a photodiode, wherein the second sample and hold portion is provided with reference to the first sample and hold portion; After sampling the voltage, the image signal is sampled while the transfer transistor is on.

In one embodiment, the first sample and hold unit may include a first sampling capacitor for sampling a reference voltage and a first transistor connected between the selection transistor and the first sampling capacitor to switch a sampling operation of the first sampling capacitor. The second sample and hold unit may include a second sampling capacitor for sampling and outputting an image signal, and a second transistor connected between the selection transistor and the second sampling capacitor to switch a sampling operation of the second sampling capacitor. Can be.

In one embodiment, the first transistor is switched so that the first sampling capacitor samples the reference voltage after the reset transistor is on-off, and the second transistor is configured such that the second sampling capacitor is connected to the image signal while the transfer transistor is on. The switching operation may be performed to sample.

According to the CMOS image sensor according to the embodiment of the present invention, since the transfer transistor transitions from the on state to the off state after the sampling of the image signal, the clock feedthrough and the charge injection error occurring in the switching of the transfer transistor from on to off. And noise due to charge redistribution can be effectively removed, thereby improving the quality of the resulting image.

1 is a circuit diagram schematically illustrating a reset or transfer transistor and a floating capacitor portion in an image sensor pixel.
2 is a circuit diagram of a pixel of a CMOS image sensor according to the present invention.
3 shows an operation timing chart of a CMOS image sensor pixel according to the prior art.
4 illustrates an operation timing chart of a CMOS image sensor pixel according to an embodiment of the present invention.

Hereinafter, a CMOS image sensor according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a schematic circuit diagram of a unit pixel included in a CMOS image sensor according to the present invention. As shown in FIG. 2, the unit pixel of the image sensor includes one photodiode PD and four transistors Tx, Rx, Dx, and Sx, and four transistors are photoelectric charges generated in the photodiode PD. Is transferred to the sensing node FD and the charge stored in the floating capacitor Cf is discharged from the sensing node FD to detect the next signal and resets to read the level of the reference voltage. A drive that is a source follower for transmitting the received voltage of the sensing node FD by the transistor Rx and the image signal photoelectrically converted by the photodiode PD to the first and second samples and the holding units 210 and 220. The selection transistor Sx addresses the sampling of the sensing node FD voltage of the pixel in units of the transistor Dx and the row. In addition, the image sensor further includes a first sample and holder unit 210 and a second sample and holder unit 220.

Referring to the operation of the image sensor, when the reset gate signal RS is activated in the logic high state while the row select signal SL is activated in the logic high state, the sensing transistor is turned on and thus the sensing node is turned on. The voltage (reference voltage) of FD is output to the source terminal of the driving transistor Dx which is a source follower transistor. Since the selection transistor Sx is turned on by the row select signal SL having a logic high level, the voltage of the source terminal of the driving transistor Dx is controlled by the first source through the source of the selection transistor Sx, that is, the node N. And the second sample and hold portions 210 and 220.

On the other hand, after the reset gate signal Rx transitions to the logic low state while the row select signal SL is active in the logic high state, the image signal is sensed as the transfer transistor Tx transitions to the logic high state. And an image signal of the sensing node FD through the driving transistor Dx and the selection transistor Sx to the first and second samples and the holding parts 210 and 220 at the node N. do.

The first sample and hold unit 210 is connected to the source of the select transistor Sx to sample the reference voltage, and the second sample and hold unit 220 is connected to the source of the select transistor Sx to connect the photodiode PD. Sample a photoelectrically converted image signal.

The first sample and hold unit 210 includes a first transistor SW1 as an analog switch and a first sampling capacitor Cs1. In the first sample and hold unit 210, after the reset transistor Rx is turned on by the reset gate signal RS and then turned off again, the first transistor SW1 is turned on according to the reset read signal RST. While on, the reference voltage supplied from the node N is sampled and held in the first sampling capacitor Cs1 while the first transistor SW1 is turned on.

Similarly, the second sample and hold unit 220 includes a second transistor SW2 as an analog switch and a second sampling capacitor Cs2. The second sample and hold unit 220 may be configured according to the signal read signal SIG while the transfer transistor Tx is turned on by the transfer gate signal TF and the transfer transistor Tx remains on. 2 transistor SW2 is turned on. The image voltage supplied from the node N is sampled and held in the second sampling capacitor Cs2 while the second transistor SW2 is kept turned on.

That is, the CMOS image sensor pixel according to the exemplary embodiment of the present invention is configured to sample the video signal while the transfer transistor is turned on at the time of sampling the image signal, thereby providing a clock feedthrough generated by the switching operation of the transfer transistor. An image signal from which noise caused by a current injection error is removed may be sampled.

On the other hand, the noise due to the clock feed-through and the current injection error generated by the switching operation of the reset transistor Rx is not a big problem because it can be eliminated through the CDS (Correlated Double Sampling) operation.

3 shows an operation timing chart of a CMOS image sensor according to the prior art. As shown in FIG. 3, the reference voltage is sampled according to the reset read signal RST pulse after the reset transistor Rx is switched by the reset gate signal RS pulse. After the sampling of the reference voltage is completed, after the transfer transistor Tx is switched by the transfer gate signal TF pulse, the image signal is sampled according to the signal read signal SIG pulse.

As such, conventional CMOS image sensors sample clock signals after the transfer transistor Tx is switched from on to off as the transfer gate signal TF transitions from a logic high to a logic low, thereby providing clock feedthrough and charge. An image signal including noise caused by an injection error is sampled, which causes deterioration of image quality.

4 shows an operation timing chart of a CMOS image sensor according to an embodiment of the present invention. As shown in FIG. 4, after the reset transistor Rx is switched by the reset gate signal RS, the reset read signal RST pulse is applied to the first switch SW1 of the first sample and hold unit 210. The reference voltage is applied to the first sampling capacitor Cs1 to sample the reference voltage. After the sampling of the reference voltage is completed, while the transfer transistor Tx is turned on by the transfer gate signal TF pulse, the second switch SW2 of the second sample and hold unit 220 is maintained. A signal read signal SIG pulse is applied to the image signal from the second sampling capacitor Cs2. When the sampling of the video signal is completed, that is, when the second MOS switch SW2 is turned off, the transfer transistor Tx is turned off.

As such, in the CMOS image sensor according to the exemplary embodiment of the present invention, since the transfer transistor Tx transitions from the on state to the off state after sampling of the image signal, the CMOS image sensor is generated in the switching of the on / off state of the transfer transistor Tx. Noise caused by clock feedthrough, charge injection error and charge redistribution can be effectively removed, resulting in improved image quality.

It is intended that the present invention not be limited by the above-described embodiments and the accompanying drawings, but only by the appended claims. Accordingly, various forms of substitution, modification, and alteration may be made by those skilled in the art without departing from the scope of the claims and the technical spirit of the present invention. Will belong.

Tx: transfer transistor Rx: reset transistor
Dx: drive transistor Sx: select transistor
PD: photodiode
210: first sample and hold part 220: second sample and hold part
SW1: first transistor SW2: second transistor
Cs1: first sampling capacitor Cs2: second sampling capacitor

Claims (3)

A CMOS image sensor comprising a unit pixel having a reset transistor, a transfer transistor, a selection transistor, and a photodiode,
A first sample and hold unit connected to a source of the selection transistor to sample a reference voltage; And
A second sample and hold unit connected to a source of the selection transistor to sample an image signal photoelectrically converted by the photodiode;
Including,
The second sample and hold unit samples the image signal while the transfer transistor is in an on state after the first sample and hold unit samples the reference voltage.
CMOS image sensor.
The method of claim 1,
The first sample and hold unit,
A first sampling capacitor sampling the reference voltage; And
A first transistor coupled between the selection transistor and the first sampling capacitor to switch a sampling operation of the first sampling capacitor;
Including,
The second sample and hold unit,
A second sampling capacitor that samples and outputs the video signal; And
A second transistor coupled between the selection transistor and the second sampling capacitor to switch a sampling operation of the second sampling capacitor;
Including,
CMOS image sensor.
The method of claim 2,
The first transistor is configured to switch to cause the first sampling capacitor to sample the reference voltage after the reset transistor is on-off,
The second transistor is operative to switch such that the second sampling capacitor samples the image signal while the transfer transistor is on;
CMOS image sensor.

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