KR20110081958A - Serial-connected memory system with output delay adjustment - Google Patents

Abstract

A system and method for calibrating clock duty cycles and / or for performing output delay adjustment are provided for application to a serial connected device operating as a slave device. The master device provides a clock to the first slave device. Each slave device in turn passes a clock to the next slave device. The final slave device returns the clock to the master device. The master device compares the originating clock and the returning clock when duty cycle correction and / or output delay adjustment is needed. In such a case, the master device generates and outputs a command to the slave device to perform the duty cycle and / or output delay adjustment. The slave devices each have circuitry for performing duty cycle calibration and / or output delay adjustment. In some implementations, each slave device is a memory device and the master device is a memory controller.

Description

Serial-connected memory system with output delay adjustment {SERIAL-CONNECTED MEMORY SYSTEM WITH OUTPUT DELAY ADJUSTMENT}

The present invention generally relates to a solid state memory system characterized by a series of serially connected memory devices.

Typical NAND flash memory systems utilize multiple parallel signals for commanding, addressing, and data transfer operations. This is a very popular way of constructing a memory system and results in very fast system operation. This is especially true for random access memory devices such as dynamic random access memory (DRAM), static random access memory (SRAM), and the like.

A disadvantage arises from this approach that multiple parallel signal lines need to be sent to each and every memory device in the memory system. In addition, the system power supply must have higher capacity to deliver higher peak power for parallel signaling. Write and read throughput for a typical NAND flash memory can be increased directly by using higher operating frequencies. For example, the current operating frequency of about 40 MHz (25 ns for tRC in = NAND flash) can be increased to about 100 to 200 MHz. Although this approach seems straightforward, there is a significant problem with signal quality at such high frequencies that sets practical limits on the operating frequency of a typical NAND flash memory.

In particular, a typical NAND flash memory is a series of parallel inputs and outputs, numbered 8 or 16, depending on the required word configuration, which receives command instructions, receives input data, and provides output data. Communicate with other components using the (I / O) pin. This is commonly known as a parallel interface. High speed operation will cause well known communication degradation effects, such as cross-talk, signal skew and signal weakening, which degrade signal quality, for example. Such a parallel interface uses multiple pins to read and write data. As the number of input pins and wiring increases, so does the number of unwanted effects. These effects include inter-symbol interference, signal skew and cross talk.

To address some of these shortcomings, several serial connection systems have been provided that feature a series of ring connected memory devices. These are 'Multiple Independent Serial Link Memory' (US20070076479A1), 'Daisy Chain Cascading Devices' (US20070109833A1),' Memory, all of which are assigned to the same assignee as the present application and are hereby incorporated by reference in their entirety. with Output Control '(US20070153576A1),' Daisy chain cascade configuration recognition technique '(US2007233903A1), and' Independent Link and Bank Selection '(US2007143677A1). These systems generally have serial input and output data pins with two control signals for enabling and disabling the serial input port and the serial output port, respectively, to provide a memory controller with maximum flexibility of serial data communication. Part of this memory system configuration consists of a shared bus topology for system clock distribution, referred to as a 'common clock system' or a 'multi-drop clocking system'. Adopt. Some of these architectures are DLLs per memory chip to synchronize two clock signals in each memory device, one for the input clock received from the previous device or controller and the other for the output clock sent to the next device. It uses a point-to-point serially connected clocking architecture featuring either locked loops or phase locked loops (PLLs).

According to one broad aspect, the present invention provides a method for a slave device of a plurality of serially connected slave devices, and the present invention provides a method for mastering a command specifying an adjustment to a clock duty cycle. Receiving from a master device; Receiving an input clock signal; Generating a duty cycle corrected clock signal from the input clock signal in accordance with the command; And outputting the duty cycle corrected clock signal.

In some embodiments, the slave device is a memory device and the master device is a memory controller.

In some embodiments, the method further comprises: receiving a command from a master device specifying how the slave device adjusts a delay to be applied to at least one signal output by the slave device; Receiving at least one input signal comprising at least the input clock signal; For each of the at least one input signal: generating a delayed version of the input signal in accordance with the command; And outputting a delayed version of the input signal, the delayed version of the input clock signal further comprising a delayed version of the duty cycle corrected clock signal.

In some embodiments, receiving a command from a master device specifying an adjustment to the clock duty cycle includes a command identifier identifying the command as a duty cycle correction command and adjusting the duty cycle. Receiving the command further comprising data indicative.

In some embodiments, receiving the command further includes receiving a device address indicating which device (s) will act as a slave device to execute the command.

In some embodiments, if the command has a device address that matches the device address of the slave device, executing the step of generating the duty cycle corrected clock signal in accordance with the command; If the command has a device address that is a broadcast device address, generating the duty cycle corrected clock signal in accordance with the command.

In some embodiments, generating the duty cycle corrected clock signal comprises: a) generating a half rate clock signal from the input clock signal; b) delaying the half rate clock signal by a selected one of a plurality of delays to produce a delayed half rate clock signal; And c) combining the half rate clock signal with the delayed half rate clock signal to generate the duty cycle corrected clock signal.

In some embodiments, the data indicating how to adjust the duty cycle correction includes an indication of a selected one of the plurality of delays.

According to another broad aspect, the invention provides a method of a memory system comprising a plurality of serially connected slave devices and a master device comprising at least a first slave device and a final slave device, the method comprising: A method comprising: a) outputting a first clock signal functioning as an input clock signal of the first slave device; b) receiving a second clock signal that is an output clock signal of the last slave device; c) generating a duty cycle correction command as a function of the duty cycle of the second clock signal and outputting the duty cycle correction command; A first slave device of the plurality of serially connected slave devices, comprising: a) receiving the first clock signal from the master device as an input clock signal of the first slave device; b) generating an output clock signal from the input signal; In each other slave device of the plurality of serially connected slave devices: a) receiving an output clock signal of a previous slave device as an input clock signal of the slave device; b) generating an output clock signal from the input clock signal; 10. In each of at least one serially connected device of the plurality of serially connected devices serving as a slave device, the method comprising: a) receiving the duty cycle calibration command; b) generating a duty cycle corrected clock signal from the input clock signal in accordance with the duty cycle correct command; And c) outputting the duty cycle corrected clock signal as an output clock signal of the slave device.

In some embodiments, each slave device is a memory device and the master device is a memory controller.

In some embodiments, the method further comprises: at the master device: a) outputting at least one output signal, the at least one output signal to function as an input clock signal of the first slave device. Including the first clock signal; b) receiving a second clock signal that is an output clock signal of the last slave device; c) determining an amount of phase offset between the first clock signal and the second clock signal; And d) generating an output delay adjustment command as a function of a phase offset between the first clock signal and the second clock signal to output the output delay adjustment command.

In some embodiments, generating a duty cycle correction command and outputting the duty cycle correction command as a function of the duty cycle of the second clock signal may comprise any designated slave of the plurality of serially connected slave devices. Generating a duty cycle correction command for execution by the device.

In some embodiments, generating a duty cycle correction command and outputting the duty cycle correction command as a function of the duty cycle of the second clock signal is performed by all of the plurality of serially connected slave devices. Generating a duty cycle correction command for the device.

In some embodiments, receiving the duty cycle correction command includes receiving a command that includes a command identifier identifying the command as a duty cycle correction command and includes data indicating how to adjust the duty cycle. It includes.

In some embodiments, generating the duty cycle corrected clock signal comprises: a) generating a half rate clock signal from the input clock signal; b) delaying the half rate clock signal by a selected one of a plurality of delays to produce a delayed half rate clock signal; And c) combining the half rate clock signal with the delayed half rate clock signal to generate the duty cycle corrected clock signal.

In some embodiments, the data indicating how to adjust the duty cycle correction includes an indication of a selected one of the plurality of delays.

According to another aspect, the present invention provides a slave device for use in an arrangement comprising a plurality of serially connected slave devices, the slave device for receiving a command from the master device specifying an adjustment to the duty cycle. Command input; A clock input for receiving an input clock signal; A duty cycle correction circuit for generating a duty cycle corrected clock signal from the clock input in accordance with a control command; And a clock output for outputting the duty cycle corrected clock signal.

In some embodiments, the slave device is a memory device.

In some embodiments, the command input is also for receiving a command from the master device specifying an adjustment for an output delay; An output delay adjustment circuit for generating a delayed clock signal from the duty cycle corrected clock signal in accordance with the command; A clock output for outputting the duty cycle corrected clock signal outputs the delayed clock signal.

In some embodiments, the slave device further includes command processing circuitry to process the command, the command comprising: a command identifier identifying the command as a duty cycle correction command; And data indicating how to adjust the duty cycle.

In some embodiments, the device further comprises a device address register, the command further comprising a device address indicating which slave device is to execute the command, wherein the slave device is configured to: The command is executed when it matches the contents of the device address register.

In some embodiments, the duty cycle correction circuit comprises: a) a clock divider circuit for generating a half rate clock signal from the input clock signal; b) a delay circuit for delaying said half rate clock signal by a selected one of a plurality of delays to produce a delayed half rate clock signal; And c) a combiner for combining the half rate clock signal with the delayed half rate clock signal to produce the duty cycle corrected clock signal.

In some embodiments, the delay circuit comprises an M unit delay element, where M> = 2, wherein the duty cycle correction circuitry outputs a signal received on an N input line, where N> = 1. Delaying the half rate clock signal to produce the delayed half rate clock signal, further comprising an N to M decoder to decode with the choice of how much of the unit delay element is to be operated.

According to another broad aspect, the present invention provides a system, comprising: a plurality of serially connected devices acting as slave devices according to claim 13 including at least a first slave device and a final slave device; A master device coupled to the first slave device and to the last slave device; The master device is adapted to output a first clock signal functioning as an input clock signal of the first slave device; A clock input for receiving a second clock signal that is an output clock signal of the last slave device; A duty detector for determining a duty cycle of the second clock signal; A first generator of a plurality of serially connected devices acting as slave devices, the command generator generating a duty cycle correction command specifying an adjustment to a clock duty cycle as a function of the duty cycle of the second clock signal; A) receives the first clock signal from the master device as an input clock signal of the first slave device; b) generating an output clock signal from the input clock signal, wherein each other slave device of the plurality of serially connected devices serving as the slave device: a) outputs the output clock signal of the previous slave device to the input clock signal of the slave device; Receive as; b) generate an output clock signal from the input clock signal; At least one of the plurality of serially connected slave devices comprises: a) receiving the duty cycle calibration command; b) generate a duty cycle corrected clock signal in accordance with a control command; c) output the duty cycle corrected clock signal as an output clock signal of a slave device.

In some embodiments, the system is a memory system, each slave device is a memory device, and the master device is a memory controller.

In some embodiments, the memory system further comprises a phase detector that determines an amount of phase offset between the first clock signal and the second clock signal, the command generator further comprising an output delay adjustment command. Is generated as a function of the amount of the phase offset, wherein a first slave device of the plurality of serially connected slave devices: a) receives the first clock signal from the master device as an input clock signal of the first slave device; ; b) generate an output clock signal from the input clock signal; Each other slave device of the plurality of serially connected slave devices comprises: a) receiving an output clock signal of a previous slave device as an input clock signal of the slave device; b) generate an output clock signal from the input clock signal; At least one of the plurality of serially connected slave devices generates: an output clock signal of the device by a) receiving the output delay adjustment command and b) delaying the input clock signal of the device according to the control command. .

In some embodiments, the command generator generates a duty cycle correction command as a function of the duty cycle of the second clock signal and to a designated serially connected device of the plurality of serially connected devices serving as the slave device. The duty cycle correction command is output by generating a duty cycle correction command for execution.

In some embodiments, the command generator generates a duty cycle correction command as a function of the duty cycle of the second clock signal and executes by all of a plurality of serially connected devices serving as the slave device. The duty cycle correction command is output by generating a duty cycle correction command.

In some embodiments, receiving the duty cycle correction command includes receiving a command that includes a command identifier identifying the command as a duty cycle correction command and includes data indicating how to adjust the duty cycle. It includes.

According to one broad aspect, the present invention provides a method for a slave device of a plurality of serially connected slave devices, wherein the method adjusts a delay to be applied to at least one signal output by the slave device. Receiving a command from a master device specifying a scheme; Receiving at least one input signal comprising at least an input clock signal; For each of the at least one input signal: generating a delayed version of the input signal in accordance with the command; And outputting a delayed version of the input signal.

In some embodiments, the slave device is a memory device and the master device is a memory controller.

In some embodiments, the method comprises outputting a data output signal, at least one of the input signals comprising a data input signal, and outputting a delayed version of the data input signal: a Sometimes, the data output signal is a delayed version of the data input signal; b) sometimes after applying the delay according to the command to a signal generated locally for the slave device, the data output signal such that the data output signal is a delayed version of the signal generated locally for the slave device. Is executed as part of outputting

In some embodiments, receiving from the master device a command specifying an adjustment to the delay to be applied to the at least one signal output by the slave device comprises: command identifier identifying the command as an output delay adjustment command. Receiving the command that includes the command, wherein the command further includes data indicating how to adjust the delay.

In some embodiments, receiving the command further comprises receiving a device address indicating which device (s) serve as a slave device to execute the command.

In some embodiments, the method further comprises, for each of the at least one input signal, if the command has a device address that matches the device address of the slave device, in accordance with the command of the input signal. Executing the step of generating a delayed version; And if the command has a device address that is a broadcast device address, for each of the at least one input signal, generating a delayed version of the input signal in accordance with the command.

In some embodiments, generating a delayed version of the input signal for each input signal comprises: a) delaying the input signal by a selected one of a plurality of delays to produce a delayed version of the input signal. To generate.

In some embodiments, the data indicating how to adjust the delay includes an indication of a selected one of the plurality of delays.

In some embodiments, the plurality of input signals comprises: a clock signal; Command strobe signal; Data strobe signal; It includes a data signal containing commands and data.

According to another broad aspect, the present invention provides a method of a memory system comprising a plurality of serially connected devices and a master device serving as a slave device, comprising at least a first slave device and a final slave device. The master device comprises: a) outputting at least one output signal comprising a first clock signal to function as an input clock signal of the first slave device; b) receiving a second clock signal that is an output clock signal of the last slave device; c) determining an amount of phase offset between the first clock signal and the second clock signal; And d) generating an output delay adjustment command as a function of a phase offset between the first clock signal and the second clock signal and outputting the output delay adjustment command.

In some embodiments, each slave device is a memory device and the master device is a memory controller.

In some embodiments, the method comprises: a first slave device of a plurality of serially connected devices serving as the slave device: a) sending the at least one output signal to at least one of the first slave device; Receiving from the master device as corresponding to an input signal; b) for each input signal, generating an output signal based on the input signal; 10. Each other slave device of the plurality of serially connected devices serving as the slave device, comprising: a) receiving output signal (s) of a previous slave device corresponding to at least one input signal of the slave device; b) for each input signal, generating an output signal based on the input signal; At least one of the slave devices, the method comprising: a) receiving the output delay adjustment command; And b) generating the output signal (s) by generating a delayed version of the input signal (s) in accordance with the output delay adjustment command.

In some embodiments, the at least one output signal of the master device further comprises a plurality of output signal (s).

In some embodiments, generating the delay adjustment command includes generating a delay adjustment command for execution by a designated serially connected slave device of the plurality of serially connected slave devices.

In some embodiments, generating the delay adjustment command includes generating a delay adjustment command for execution by all of the plurality of serially connected slave devices.

In some embodiments, generating a delayed version of the input signal (s) in accordance with the output delay adjustment command comprises generating a delayed version of the input signal (s) delayed by a selected one of a plurality of delays. It includes.

In some embodiments, generating the delay adjustment command includes generating a command identifier that includes a command identifier that identifies the command as an output delay adjustment command and includes data indicating how to adjust the delay. It includes.

In some embodiments, the data indicating how to adjust the delay includes an indication of a selected one of the plurality of delays.

In some embodiments, the method includes an output delay adjustment command that adjusts the delay by adding a delay of one unit delay element in one slave device to the time until the phase offset can be tolerated. The master device further includes the output.

In some embodiments, the plurality of input signals comprises: a clock signal; Command strobe signal; Data strobe signal; It includes a data signal containing commands and data.

According to another broad aspect, the present invention provides a slave device for use in an arrangement comprising a plurality of serially connected slave devices, the slave device receiving a command from the master device specifying a method of performing output delay adjustment. Command input to perform; A clock input for receiving an input clock signal; An output delay adjustment circuit for generating a delayed clock signal from the clock input in accordance with the command; And a clock output for outputting the delayed clock signal.

In some embodiments, the slave device is a memory device.

In some embodiments, the slave device includes command processing circuitry to process the command, the command including a command identifier identifying the command as an output delay adjustment command, and adjusting the output delay. Contains data representing the manner.

In some embodiments, the slave device further comprises a device address register, the command further comprises a device address indicating which slave device is to execute the command, wherein the slave device has the device identifier selected by the slave device. The above command is executed when it matches the contents of the device address register.

In some embodiments, the output delay adjustment circuit, for each of a plurality of input signals, delays the input signal by a selected one of a plurality of delays, including the input clock signal, to delay the input signal. A delay circuit that generates a delayed version.

In some embodiments, each output delay circuit includes an M unit delay element, where M> = 2, and the duty cycle correction circuitry applies a signal received on the N input line, where N> = 1. Generating a delayed version of the input signal, further comprising an N to M decoder to decode with a choice of how much of the unit delay element is to be operated.

According to another broad aspect, the present invention provides a memory system, comprising: a plurality of serially connected slave devices including at least a first slave device and a final slave device; A master device coupled to the first slave device and to the last slave device; The master device is adapted to output a first clock signal functioning as an input clock signal of the first slave device; A clock input for receiving a second clock signal that is an output clock signal of the last slave device; A phase detector for determining an amount of phase offset between the first clock signal and the second clock signal; A command generator for generating an output delay adjustment command as a function of the amount of phase offset, wherein a first slave device of the plurality of serially connected slave devices comprises: a) inputting the first clock signal to the first slave device; Receive from the master device as a clock signal; b) generates an output clock signal from the input clock signal, wherein each other slave device of the plurality of serially connected slave devices: a) receives an output clock signal of a previous slave device as an input clock signal of the slave device; b) generate an output clock signal from the input clock signal; At least one of the plurality of serially connected slave devices includes: a) receiving the output delay adjustment command; b) generate an output clock signal of the device by delaying the input clock signal of the device in accordance with the control command.

In some embodiments, the system is a memory system, each slave device is a memory device, and the master device is a memory controller.

In some embodiments, the command generator is configured to generate the output delay adjustment command for execution by a designated serial connected slave device of the plurality of serial connected slave devices.

In some embodiments, the command generator is adapted to generate the output delay adjustment command for execution by all of the plurality of serially connected slave devices.

In some embodiments, generating the output delay adjustment command includes a command identifier identifying the command as an output delay adjustment command, and generating the command including data indicating how to adjust the output delay. It involves doing.

A method and apparatus are provided for clock duty cycle correction and / or phase synchronization that do not require a DLL or PLL for a serially connected memory system, which generally includes a plurality of memory chips and a memory controller connected in a ring configuration. In some embodiments, the memory controller has a phase / duty cycle detector for detecting the phase and duty cycle of the clock signal after moving around the ring, each memory device having a phase and / or duty cycle of the clock. It has one or more controller programmable delay lines used to adjust. These are adjusted by commands sent from the memory controller until the phase and duty cycle detected by the memory controller are acceptable.

The method and apparatus described herein can be applied to any kind of semiconductor integrated circuit system having any kind of semiconductor integrated circuit device as a slave device in a series connection configuration having a common interface between adjacent devices. Examples of integrated circuit types include central processing unit, graphics processing unit, display controller IC, disk drive IC, and NAND flash EEPROM, NOR flash EEPROM, AND flash EEPROM, DiNOR flash EEPROM, serial flash EEPROM, DRAM, SRAM, ROM, Memory devices such as EPROM, FRAM, MRAM, PCRAM, and the like.

1 is a system block diagram of a serially connected memory system having a controller programmable duty cycle correction scheme;
2 is a block diagram of a memory device having a controller programmable duty cycle correction scheme;
3 is a block diagram of a programmable delay line for duty cycle correction;
4 is a timing diagram of a controller programmable duty cycle calibration;
5 is a flowchart of a method of duty cycle correction;
6 is a timing diagram for a write duty cycle register command;
7 is a block diagram of a program delay line for output delay adjustment;
8 is a timing diagram of a controller programmable output delay adjustment;
9 is a flowchart of a method of performing output delay adjustment; And
10 is a timing diagram for a write output delay register command.

In the following detailed description of sample embodiments of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific sample embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, other embodiments may be utilized, and logical, mechanical, electrical, and other modifications may be made without departing from the scope of the invention. It is understood that it can be lost. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

Some memory system configurations mentioned in the background employ a shared bus topology for system clock allocation, referred to as a "common clock system" or a "multi-drop clocking system." If the system clock is applied to too many memory devices in parallel and the clock signal moves too far from the clock source, typically the memory controller, the maximum operating clock frequency is the total loading of the clock signal and the clock is the memory system. It may be limited by the distance traveled within the physical layout of the.

Some of the memory system configurations mentioned in the background art are each for synchronizing two clock signals in a memory device, one of which is an input clock received from the previous device or controller and the other of which is an output clock transmitted to the next device. It utilizes a point-to-point serially coupled clocking architecture featuring a DLL or PLL in a memory device. However, having an on-chip DLL or PLL in each memory device can lead to enormous power consumption. For on-chip DLLs or PLLs, various chip-to-chip clock delays (caused by various interconnect loadings, such as multi-chip stacking or packages, and different wiring junction loadings) are accumulated through multiple serially connected devices and system operation. It may not be acceptable for.

Referring now to FIG. 1, there is shown a system block diagram of a serially connected memory system, generally indicated at 101 employing a controller programmable duty cycle correction scheme. The memory system 101 includes a memory controller 10 as a master device connected to the first memory device 100-1. The memory device 100-1 is connected in a ring configuration, with a series of slaves including devices 100-1 through 100-8 in which the final device 100-8 is connected back to the memory controller 10. It is the first slave device among the slave devices. In the illustrated example, a highly multiplexed unidirectional point-to-point bus architecture is provided to transfer information such as commands, addresses and data from the memory controller 10 to the memory devices 100-1 through 100-8. have. This bus architecture includes a link 90 from the memory controller 10 to the original memory device 100-1, and individual links between each pair of adjacent memory devices, which are links 90-1 through 90-. 7) and a link 90-8 between the final memory device 100-8 and the memory controller 10.

In the illustrated example, each link includes a series of signals output by the previous device (memory controller 10 or memory device) for reception by the next device. Each link includes a series of output ports of the previous device, a series of input ports of the next device, and a series of physical interconnections between the output port and the input port. For convenience, the output ports will be given the same names as the signals they output and the input ports will be given the same names as the signals they receive. In the illustrated example, the signals (and output ports) of the previous device are CSO (Command Strobe Output), DSO (Data Strobe Output), Qn (Data Output), CKO / CKO Called # (differential clock output signals). Corresponding signals (and input ports) of the following devices are referred to as Command Strobe Input (CSI), Data Strobe Input (DSI), Data Input (Dn), and differential clock input signals (CKI / CKI #). There may be additional ports or signals (eg, chip enable (CE #) or RST # (reset) or power supply pins) not shown for better understanding and simplicity. Physical interconnections include differential clock buses S111, S111-1 through S111-8 for differential clock signals, S112 for command strobes, S112-1 through S112-8, and S113 and S113- for data strobes. 1 to S113-8, data S114, and S114-1 to S114-8.

In some embodiments, the data output Qn and the data input Dn are n = 0 for 1-bit link establishment; N = 0, 1 for 2-bit link configuration; N = 0, 1, 2, 3 for 4-bit link setup; For an 8-bit link setup it may have different data widths such as n = 0, 1, 2, 3, 4, 5, 6, 7 and the like. In some embodiments, the width of the link can be programmed through the link configuration register to utilize 1, 2, 4 or 8 of the available data input and output pins of the device package. This feature allows these memory devices to operate in a ring configuration with devices with smaller or larger maximum link widths, provided that they are all programmed to use the same link width. do. For example, the entirety of which is incorporated herein by reference. See 'Switching Method of Link and Bit Width' (WO 2008/070978).

CKI / CKI # is the input clock. Command / address packets on the Dn port depicted by the CSI are latched on the rising edge of CKI or on the falling edge of CKI #. Write data packets on Dn depicted by the DSI are latched on the rising edge of CKI or on the falling edge of CKI #.

CKO / CKO # is the output clock, which is a delayed version of CKI / CKI #. CSO, DSO and Qn signals are referenced to the rising edge of CKO or the falling edge of CKO #; For example, read data packets on Qn depicted by the DSO are referenced at the rising edge of CKO or the falling edge of CKO #.

When the command strobe input CSI is HIGH, the command / address packet through Dn is latched on the rising edge of CKI or the falling edge of CKI #.

The command strobe output (CSO) is the echo signal of the CSI. It echoes a CSI transition with latency tIOL, which, in certain implementations, is two clock cycle latency that is referenced to the rising edge of CKO or the falling edge of CKO #. 2 clock cycle latency is implementation detail; More generally it may be any number of clock cycles appropriate for a given design.

When the data strobe input (DSI) is high, even if the memory device is in 'read mode', it enables the read data output path and the Qn buffer (not shown). If the DSI is low, the Qn buffer holds previously accessed data. When the DSI is in the 'write-mode', it enables the Dn buffer and receives a write data packet on the rising edge of CKI or the falling edge of CKI #.

The data strobe output (DSO) is the echo signal of the DSI. It echoes a DSI transition with latency tIOL that is referenced to the rising edge of CKO or the falling edge of CKO #. As indicated above, tIOL is two clock cycles in a particular implementation.

The data input signal Dn (n = 0, 1, 2, 3, 4, 5, 6 or 7) carries the command, address and / or input data information. If the chip is configured for '1-bit link mode', DO is the only valid signal and receives 1 byte of the packet in 8 clock cycles. If the chip is configured for "2-bit link mode", DO & D1 is a valid signal and receives one byte of the packet in four clock cycles. If the chip is configured for '4-bit link mode', DO, D1, D2 & D3 are valid signals and receive one byte of the packet in two clock cycles. If the chip is configured in "8-bit link mode," DO, D1, D2, D3, D4, D5, D6, and D7 are all valid signals and receive one byte of a packet in one clock cycle.

The data output signal Qn (n = 0, 1, 2, 3, 4, 5, 6 or 7) carries output data during a read operation or bypasses input data, address or command received at Dn. . If the chip is configured in '1-bit link mode', Q0 is the only valid signal and transmits one byte of the packet in eight clock cycles. If the chip is configured in '2-bit link mode', Q0 and Q1 are valid signals and transmit 1 byte of the packet in 4 clock cycles. If the chip is configured in '4-bit link mode', QO, Q1, Q2 and Q3 are valid signals and transmit one byte of the packet in two clock cycles. If the chip is configured in '8-bit link mode', QO, Q1, Q2, Q3, Q4, Q5, Q6 and Q7 are all valid signals and transmit one byte of the packet in one clock cycle.

It should be clearly understood that the number of ports and signals they contain for transmission between adjacent pairs of devices and serially connected memory systems is implementation detail and is not necessarily depicted in FIG. 1. More generally, at least a clock signal is passed between each pair of consecutive devices. There may be additional signals transmitted between successive devices and specific examples thereof have been given above. It is also noted that the specific number of memory devices-eight in the example of FIG. 1-is implementation specific. Any suitable number of devices can be interconnected with a serial connection architecture. The expression "serial connection" in this context refers to the serial arrangement of memory devices, one in front of the other, not the nature of the link between each pair of adjacent devices, which may in fact be serial or parallel.

The memory controller 10 includes a phase detector 11, a duty detector 13 and a command generator 12. In some embodiments, memory controller 10 includes only phase detector 11, in which case only output delay adjustment is performed. In some embodiments, memory controller 10 includes only duty detector 13, in which case only duty cycle calibration is performed. In some embodiments, both phase detector 11 and duty detector 13 are included, in which case both output delay adjustment and duty cycle correction may be performed. This final case is assumed in the detailed description below. The phase detector 11 and the duty detector 13 are connected to the command generator via signal buses S11 and S12 respectively. The command generator 12 has an output signal bus S13 that is connected to CSO and Qn through which it can output a command.

The memory controller 10 drives the differential clock bus S111 from its own port CKO / CKO # and all of the eight memory devices 100-1-100-8 are series flow-through. through the CKO / CKO # port of the previous device through their own clock port CKI / CKI #. The memory controller 10 drives three different buses S112, S113 and S114 respectively through its own ports CSO, DSO and Qn. The first memory device 100-1 receives three buses S112, S113 and S114, respectively, via its own ports CSI, DSI and Dn, and the first memory device 100-1 receives two clock cycles. Redrive (echo) three corresponding buses S112-1, S113-1 and S114-1 through their own output ports CSO, DSO and Qn, respectively, with latency (= tIOL). The second memory device 100-2 receives three buses S112-1, S113-1 and S114-1 through its own input ports CSI, DSI and Dn, respectively. This approach includes the final bus S112-8, which is connected back to the memory controller 10 through the input ports CSI, DSI and Dn of the memory controller as well as all of the eight memory devices 100-1 to 100-8. S113-8 and S114-8) respectively.

In operation, for duty cycle correction, the duty detector 13 monitors the duty ratio of CKI / CKI #, which is the clock input after being passed between all devices 100-1 to 100-8 in the ring. . If the duty detector 13 detects a duty error from CKI / CKI #, that is, a deviation in the duty cycle from the required duty cycle, it is sent through the signal bus S12 to the duty cycle in which the duty cycle is required. Asserted 'Duty_Add' or 'Duty_Sub' to indicate that the duty cycle should be longer and shorter than the required duty cycle to indicate that it should be shorter and longer. In response, command generator 12 generates an appropriate 'write duty cycle register' command packet.

In operation, for output delay adjustment, phase detector 11 monitors the phase of CKI / CKI #. When the phase detector 11 detects a phase error PE between CKI / CKI # and CKO / CKO #, it asserts a 'PE' signal via the signal bus S11. In response, command generator 12 generates an appropriate 'write output delay register' command packet.

The command generator 12 issues an appropriate command packet in accordance with the signals received at S11 and S12 and transmits command information via the signal bus S13 and the CSO and Qn ports.

Referring now to FIG. 2, shown is a block diagram of an example implementation of the memory devices 100-1 through 100-8 of FIG. 1. The device, shown generally at 100, includes a memory core 150, command / address packet logic 130, data packet logic 140, and duty cycle correction logic 120. Memory core 150 may be a single bank of memory cell arrays or multiple banks of memory cell arrays, depending on design changes. Data packet logic 140 processes and stores all necessary data transfer information. The command / address packet logic 130 processes all command commands and / or address information received through the internal signal 'dn_lat' according to the internal control signal 'csi_lat' as described below.

Clock input processing

Device 100 includes a clock input receiver 102D for CKI / CKI # that may be, for example, a differential type input buffer to handle differential clock inputs CKI and CKI #. The clock input receiver 102D translates the external interface level of CKI / CKI # into the internal logic level of the internal clock signal 'cki_i'. The internal clock signal cki_i can be used in other internal logic blocks for various operations. As will be described in detail below, duty cycle correction logic 120 takes internal clock signal cki_i to generate duty cycle corrected clock signal clk_dcc. The duty cycle corrected clock signal 'clk_dcc' is delayed by the controller programmable delay line PDL2 105D, and the delayed signal 'clk_dcc_d' finally outputs an external clock output signal CKO / CKO # to the output driver block 108D. Is driven into the input port.

Command Strobe Input Processing

Device 100 includes a command strobe receiver 102A that generates a buffered signal 'csi_i' from a CSI input signal. The buffered signal 'csi_i' is connected to the D port of the D-type flip-flop 103A. Flip-flop 103A is driven by clock signal 'cki_i' and latches the state of the 'csi_i' signal on every rising edge of 'cki_i'. The latched signal 'csi_lat' is provided to the command / address packet logic 130 and the clock input port is also provided to the D port of another flip-flop 103E which is driven by the duty corrected clock signal clk_dcc. The output signal 'cso_i' of the flip-flop 103E is delayed by the controller programmable delay line PLD2 105A, the delayed signal 'cso_d' finally outputting the output driver block (the output signal CSO) Drive to the input port of 108A). Two stages of flip-flop logic 103A and 103E provide two clock cycles of input-to-output latency (= tIOL) for the bypass of CSI to CSO.

Data strobe input processing

Device 100 includes a data strobe input receiver 102C that generates a buffered signal 'dsi_i' from the DSI input signal. The buffered signal dsi_i is connected to the D port of the D-type flip-flop 103C. Flip-flop 103C is driven by clock signal 'cki_i' and latches the state of 'dsi_i' on every rising edge of 'cki_i'. The latched signal 'dsi_lat' is provided to the command / address packet logic 130 and the data packet logic 140 and the D port of another flip-flop 103G, whose clock input port is driven by the duty calibration clock signal clk_dcc. Is also provided. The output signal 'dso_i' of the flip-flop 103G is delayed by the controller programmable delay line PDL2 105C, and the delayed signal 'dso_d' finally outputs an external signal DSO of the output driver block 108C. Drive to the input port. Two stages of flip-flop logic 103C and 103G provide the same input-to-output latency (= tIOL) of two clock cycles for bypass of DSI to DSO.

Data processing

Device 100 includes a data receiver 120B to receive an external signal Dn. The number of receivers 102B may be one or more, depending on the bit width of the Dn port. For example, if the Dn port is designated DO, Dl, D-7 for an 8-bit wide data input / output implementation, receiver 102B will repeat eight times. The output 'dn_i' of the receiver 102B is provided to the D port of the D-type flip-flop 103B. Flip-flop 103B is driven by clock signal 'cki_i' and latches the state of 'dn_i' on every rising edge of 'cki_i'. The latched signal 'dn_lat' is provided to the command / address packet logic 130 and also to the data packet logic 140. The latched signal 'dn_lat' is also provided to one input port of the multiplexer 104. The other port of multiplexer 104 is driven by the signal 'core_data' from data packet logic 140. The output of the multiplexer 104 is connected to the D input port of the flip-flop 103F, whose clock input port is driven by the duty calibration clock signal clk_dcc, of the output of the multiplexer 104 on every rising edge of 'clk_dcc'. Latch the state. The latched signal 'q_i' is delayed by another controller programmable delay line PDL2 105B, and the delayed signal 'q_d' is finally driven to the input port of the output driver block 108B which outputs the external signal Qn. . The two stages of flip-flop logic 103B and 103F provide the same input to output latency (= tIOL) of two clock cycles for bypass of Dn versus Qn.

The internal signal dn_i includes both command content (as depicted by the command strobe input) and data input (as depicted by the data strobe input), if present. Each device has a device address stored in the device address register 131 in some embodiments. Each command includes a device address portion that includes a device address of one of the memory devices to which the command is addressed. There may also be a broadcast address that requires a command to be processed by all devices. The memory device 100 processes each command by examining the device address portion. If the device address information in the received command / address packet matches its own stored device address of the memory device 100, the command / address packet logic 130 processes the command, and the command is directed to that memory device. It also issues an "id_match" signal to mean that it is. The id_match signal is used to steer the data flow path of the multiplexer 104. If the "id_match" is in a high logic state (more generally a "match state" is defined) as a result of the device address matching process, the multiplexer 104 selects to output "core_data" so that the memory Data from core 150 may be sent to flip-flop 103F. On the other hand, when "id_match" is in a low logic state (more generally "non-match state" is defined) as a result of the device address matching process, the multiplexer 104 selects to output "dn_lat", Data received from data input Dn may be sent to flip-flop 103F to be echoed at output Qn.

Accordingly, the multiplexer 104 may: a) bypass the data received from the data input Dn by selecting the dn_lat input of the multiplexer 104 and b) core_data by selecting the core_data input of the multiplexer 104. Take into account the choice between outputting. The signal 'core_data' is generally sent from the memory core 150 to the data packet logic 140, for example, as part of a 'page read' operation upon request from the memory controller 10. Then, after the 'page read' operation is performed, the memory controller 10 may request 'BURST READ' for the memory device with a command addressed to the memory device. In that case, the memory device processes the corresponding address information including the 'burst read' command and the device address portion. If the device address information in the received command / address packet matches its own stored device address of the memory device 100, then the command / address packet logic 130, in order to steer the data flow path of the multiplexer 104, Issue an "id_match" signal. If "id_match" is in a high logic state as a result of the device address matching process, the multiplexer 104 selects to output "core_data" so that data previously transmitted from the memory core 150 to the data packet logic 140 is lost. May be sent to flip-flop 103F.

Note that if the command is addressed to the memory device but the command is not a burst read command, in some embodiments the core_data input of the multiplexer 104 is still selected, even if there is no data output there. The core_data signal may be a static signal in such a case. This results in the data input Dn not being echoed to the next device. This has the effect of reducing power consumption in subsequent devices by eliminating the need for them to process data associated with commands not addressed to them. This is described in more detail in US Application No. 12 / 018,272, filed Jan. 23, 2008, entitled “Semiconductor Device and Method for Reducing Power Consumption in a System Having Interconnected Devices”.

Thus, in some embodiments, the delayed version of the data input signal Dn is generated as one component of the data output signal Qn. Sometimes, the data output signal is a delayed version of the data input signal. For the described implementation, this may be the case where the data input signal contains content that is not specific to a particular memory device, but other scenarios are possible. Also, sometimes, the data output signal includes a delayed version of the locally generated signal to the memory device after applying a delay to the locally generated signal to the memory device in accordance with the command. For the described implementation, the signal generated locally at the memory device is the so-called core_data output from the data packet logic 140 but other scenarios are possible.

The command / address packet logic 130 may include a duty cycle correction register (DCR) that generates an output DCR <0: 3> to the duty cycle correction circuit 120 to control the amount of duty cycle correction performed as described below; ODR having a duty cycle correction register 132 and generating output ODR <0: 1> for packet delay lines 105A, 105B, 105C, 105D to control the amount of output delay applied as described below. (output delay register; has an output delay register 134. One of the available commands is a “write duty cycle calibration register” command for writing a value to the DCR 132. Similarly, one of the available commands is an ODR 134 is a "write output delay register" command for writing a value.

Write Duty Cycle Correction Register Command

The use of a “write duty cycle calibration register” command assumes an implementation, as described herein, in which the amount of delay applied when performing the duty cycle calibration is controlled by writing a value to the duty cycle calibration register. More generally, any command referred to herein as a duty cycle calibration command may be employed that has the effect of causing the device to set the manner in which the duty cycle calibration is to be executed. Thus, the described "Write Duty Cycle Calibration Register" command is considered to be a specific example of the duty cycle calibration command.

Write output delay register command

The use of a “write output delay register” command assumes an implementation, as described herein, wherein the amount of delay to be applied is controlled by writing a value to the output delay register. More generally, any command referred to herein as an output delay adjustment command can be employed that has the effect of causing the device to set the amount of delay to be applied. Thus, the described "write output delay register" command is considered a specific example of the output delay adjustment command.

Duty cycle correction

In the illustrated example, the duty cycle correction circuit 120 includes a clock divider 123 and a controller programmable delay line 121 that includes a '4 to 16 decoder' block and a 'programmable delay line PDL1'. Include. The individual outputs clk_ref, clk_del of clock divider 123 and controller programmable delay line 121 are input to XOR gate 122, and the output of XOR gate 122 is duty cycle corrected clock clk_dcc.

The clock divider 123 derives the output signal 'clk_ref' having a frequency that is one half of the input 'cki_i' signal. Clock divider circuits are well known in the art. In the specific example illustrated, clock divider 123 includes a D-type flip-flop 103D which is driven by an internal clock signal cki_i through its own clock input port. Output port Q of D-type flip-flop 103D is connected to input port D through inverter logic 124 to obtain a half frequency output signal.

Controller programmable delay line 121 generates output signal clk_del, which is a delayed version of clk_ref. The amount of delay is determined by the selection signal of the '4 to 16 decoder' logic block, which is controlled by the DCR <0: 3> signal information received from the command / address packet logic 130. The XOR logic gate 122 receives the two half clock signals clk_ref and clk_del and outputs a duty cycle adjusted complete clock signal clk_dcc.

3 is a block diagram of an example programmable delay line 121 for duty cycle correction that may be used, for example, in the duty cycle correction circuit of FIG. 2. The half frequency clock signal clk_ref is driven to each individual input of the 16 unit delay blocks UNIT_0 to UNIT_15. Each unit delay block has the same structure, and the unit delay block UNIT_15 will be described by way of example. The unit delay block consists of two NAND logic gates 1211 and 1212 and one inverter logic gate 1213. The first NAND logic gate 1211 receives clk_ref at its own first input and receives the output from the 4 to 16 decoder 1210 at its own second input. An output of the first NAND logic gate 1211 is input to a first input of the second logic NAND gate 1212. For the unit delay block UNIT_15, the second input of the second logic NAND gate 1212 is connected to Vdd. For all unit delay blocks except for the rightmost unit delay block UNIT_0, the output of the second NAND gate 1212 is connected via the inverter 1213 to the second input of the second NAND gate 1212 of the next unit delay block. do. The output of the second NAND gate of the rightmost unit delay block UNIT_0 is connected through an inverter to generate the full output clock clk_del signal. The 4 to 16 decoder block 1210 has a 4-bit wide input bus DCR <0: 3> as its own input. The decoder block 1210 decodes the input and outputs a 16-bit wide bus SEL <15: 0>, where one line of the bus is connected to each of the 16 unit delay blocks. The unit delay logic shown is an example of a known circuit technique that has been used to create a register controlled delay-locked-loop. Other unit delay logic may alternatively be employed. The use of a 16 unit delay block is implementation specific. For example, more generally, an N to M decoder may be used to decode a signal received on an N input line into an M control signal for an M unit delay block, where N> = 1 and M> = 2.

In operation, the '4 to 16 decoder' logic 1210 outputs 16 SEL <15: 0> so that only one of the 16 select signals is in the high logic state and all of the other 15 select signals are in the low logic state. Create Therefore, only one unit delay block is selected to transmit a 'clk_ref' signal through the unit delay block that is the right side of the selected unit delay block. The control input DCR <0: 3> is used to select the unit delay block to process the clk_ref input. The minimum delay is selected by selecting the rightmost unit delay block UNIT_0, in which case clk_del is the clk_ref signal delayed by one unit delay block, while the maximum delay selects the leftmost unit delay block UNIT_15. Clk_del is a clk_ref signal that is delayed by all of the 16 unit delay blocks.

For most processing techniques, the unit delay amount of the illustrated unit delay block is about 100 ps to 150 ps. However, in some embodiments, more sophisticated unit delay circuit blocks are employed for higher operating frequencies with more sophisticated delay tuning performance. The unit delay time is represented by “tUD” in FIG. 3 and the total delay time for the entire programmable delay is represented by “tPDL1” which is 16 times of “tUD”.

In some embodiments, the default setting for power-on startup is to have a logic high state on the SEL <7> bit, since it is in the middle of the delay line. However, for other design changes, the default settings may be different and it may be advisable to have a minimum delay setting to be ready for operation at the maximum frequency.

FIG. 4 is an example of a timing diagram of a controller programmable duty cycle calibration procedure as shown in FIG. 3 except for the CKI, which is the raw input clock signal to be duty calibrated. The timing diagram shows one extremely distorted clock input signal CKI at the top, for simplicity of illustration only. The half clock signal clk_ref is derived from the 'clock divider' block 123 of FIG. 2 and its rising and falling edges are aligned with the two rising edges of the CKI. For this example, the clock signal clk_dcc is 45% on, 55% off, without any change to the DCR <0: 3> value shown, for example, initially set to "0111b". Will have a distorted duty ratio such as After DCR <0: 3> is changed to “1000b”, the duty cycle of clock signal clk_dcc is at the selection of controller programmable delay line 121 from SEL 7 enabled to SEL 8 enabled. It is corrected to 50% on and 50% off as a result of the shift.

Control of Duty Cycle Calibration

Recall that the content of DCR 132 is used to control the amount of delay introduced by the controller programmable delay line 121 in the duty cycle correction circuit 120 and thereby control the duty cycle correction. As described above, the contents of the DCR 132 may be written along with the 'write duty cycle register' command.

5 is a flow chart for a duty cycle calibration procedure from the point of view of the controller. The method begins at block 5-1 with powering on the device. At this point, all of the delay lines are initialized and device addresses for all devices are assigned. In block 5-2, the memory controller 10 uses the duty detector 13 to monitor the duty ratio of CKI / CKI #. If there is a duty cycle error, in yes path block 5-3, block 5-4, duty detector 13 asserts a “Duty_Add” or “Duty_Sub” signal S12. After this, the command generator 12 issues a 'write duty cycle register' command with a value of "DCR + 1" or "DCR-1". If there is still a duty cycle error, yes path block 5-6, the method continues back at step 5-4 with further adjustment to the duty cycle register. If there is no longer a duty cycle error, no path block 5-6, duty cycle calibration is completed at 5-7. Similarly, if no duty cycle error is detected at block 5-3, the method is also completed at 5-7 at that point.

Table 1 is an exemplary command packet definition for writing to the duty cycle register (DCR). The first byte is a 'device address (= DA)' portion, the second byte contains a command code (= CMD = FAh), and the third byte contains a register value (= DCR <0: 3>). In some embodiments, a broadcast address is provided, such as FFh. If the DA is set to a broadcast address, it means that all the memory devices are expected to execute the command, since the command is a broadcasting command. Otherwise, only the specific memory device that matches the DA will execute the command. In some embodiments, to give the controller 10 more flexibility, a 'read duty cycle register' command is also implemented.

Example Command Packet Definitions for Duty Cycle Registers Command First byte Second byte Third byte Write Duty Cycle Register (DCR) DA FAh DCR <0: 3>

* Note:

1) If DA (device address) is FFh (= 255d), it is a broadcasting command, so all devices will respond to the command.

2) DA = device address

Table 2 is an exemplary bit definition of the duty cycle register (= DCR). It is entirely an example definition, so if the system configuration requires more granularity for unit delay adjustment, this table is easily extended to facilitate greater manageability in terms of programmable delay lines. Can be. For example, if bits <7: 0> are input from the controller as "0000 1000b = 08h", DCR <3: 0> will only allow Bit <3: 0> (= "1000b") for valid register values. The upper 4 bits Bit <7: 4> will be ignored. In other design variations, however, more sophisticated unit delay circuitry may be implemented for higher frequency operation, and additional bit allocations may be used.

Example Bit Definitions of Duty Cycle Registers and Output Delay Registers Explanation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Duty cycle
Register bits Inverted for future use
(low) DCR <3> DCR <2> DCR <1> DCR <0>

6 is an example of a timing diagram of a 'write duty cycle register' command packet sequence based on a Single Data Rate (SDR) operation. In this timing diagram, at time T1, the rising edge of CKI or falling edge of CKI # latches the high state of CSI and simultaneously latches DA (= device address = 0Oh) information on the Dn port (s). If DA is set as FFh (= 255 in decimal), this means that the 'write duty cycle register' command is a broadcasting command, thereby exemplifying that all memory devices execute the command. In some embodiments, broadcasting commands are used for duty cycle correction operations. However, the disclosed circuitry also allows for more flexible adjustment of the duty cycle calibration operation in individual devices. At the next rising edge time T2, the memory device latches the CMD (= command = FAh) information, and at the third rising edge T3, latches the DCR (= duty cycle register value = 08h) information. The CSO output and Qn output ports echo the CSI input and Dn input signals, respectively, with two clock latencies of tIOL (= Input-to-Output Latency). There is another latency specification, tWDCR (= Write Duty Cycle Register Latency), which is for the processing time of the write duty cycle register packet in the memory chip and is the controller programmable delay in the duty cycle correction circuit 120. For the processing time of the duty cycle adjustment in line 121. In some embodiments, the tWDCR value is set as four clock cycles as shown in FIG. After tWDCR (eg, at T8), memory controller 10 may issue any other command packet to the memory device.

The described embodiments assume that all devices of the serial connection architecture implement duty cycle correction. More generally, at least one of the devices implements duty cycle calibration.

Output delay adjustment

Referring back to FIG. 1, the programmable delay lines 105A, 105B, 105C, described to enable programmable delay of the output signals CSO, Qn, DSO and CKO / CKO # to enable phase correction. 105D) is provided. 1 also shows an output delay register signal bus ODR <0: 1> coupled to a two to four decoder logic block 106. The two-to-four decoder logic block 106 outputs four select signal buses SEL2 <0: 3>. The SEL2 <0: 3> select signals are connected to all four controller programmable delay lines 105A, 105B, 105C and 105D.

7 illustrates an example circuit block implementation for output delay adjustment. In the illustrated example, programmable delay lines 105A, 105B, 105C and 105D are made up of the same four unit delay elements as those used in FIG. 3. This means that the range of delay adjustment for the output, which is the range of delay of adjustment of the duty cycle, is only 4/16. However, this is an implementation detail and other numbers of delay elements could alternatively be employed. Each programmable delay line 105A, 105B, 105C, 105D receives individual signals cso_i, q_i, dso_i and clk_dcc as inputs of the delay lines and generates individual delayed outputs cso_d, q_d, dso_d and clk_dcc_d. If the memory system has a multi-bit output configuration, such as an 8-bit wide I / O configuration, the q_i and q_d signals will be correspondingly increased, e. The number of line blocks will correspondingly be increased such that the number is equal to eight.

In operation, the '2 to 4 decoder' logic 106 generates a SEL2 <0: 3> output such that only one of the four select signals is in a high logic state and that all of the other three select signals are in a logic low state. Create Only the selected unit delay block transmits individual input signals to the right side of the selected unit delay block through the remaining unit delay blocks. The control input ODR <0: 1> is used to select the unit delay block to process the individual inputs. The minimum delay is selected by selecting the rightmost delay block UNIT_0, in which case each output signal is an individual input signal delayed by one unit delay block, while the maximum delay is the leftmost unit delay. It is selected by selecting the block UNIT_3, in which case each output signal is an individual input signal delayed by four unit delay blocks.

'2 to 4 decoder' logic 106 with four unit delay blocks is implemented with this example circuit design. However, more generally, any required number of delay units and corresponding decoder logic can be used. The default delay setting can be used during the power-on initialization period. In this example, the default selection may be set to, for example, SEL2 <0>, and the memory device may be configured with a minimum for each output path after power-on or hard reset in some other design change. Will have a delay amount. The use of four unit delay blocks is implementation detail. For example, more generally, an N to M decoder may be employed to decode a signal received on an N input line into an M control signal for an M unit delay block, where N> = 1 and M> = 2.

8 is an exemplary timing diagram for a controller programmable output delay adjustment. The delayed version of the duty cycle correction clock clk_dcc and its clk_dcc_d before and after the change in the contents of the output delay register are shown. After the change from the value "00b = Od" to "01b = 1d" in the output delay register, it can be seen that the delayed clock is delayed by the amount of 2 x tUD, while before the adjustment it is delayed by 1 x tUD. The output of the delay adjustment, which is the command strobe output cso_i and cso_d before the output after the delay adjustment, is also shown. Once again, before the change to the output delay register, the delayed command strobe is delayed by 1 x tUD. After the change to the output delay register, the delayed command strobe is later by an amount of 2 x tUD.

Control of Output Delay Adjustment

Recall that the contents of ODR 134 are used to control the amount of delay introduced by delay lines 105A, 105B, 105C, and 105D, thereby controlling the amount of output delay adjustment. As discussed above, the contents of the ODR 134 may be written with the 'write output delay register' command.

If the phase detector 11 of the memory controller 10 detects an unacceptable phase difference between its own CKI / CKI # signal and the CKO / CKO # signal, the controller 10 may determine the first memory device (Fig. 1). It will issue one “write output delay register” command packet with one added unit delay amount allowing 100-1). After sufficient clock cycles for the first memory device, for example, for the total tIOL latency and tWODR (write output delay register latency) described below with respect to FIG. 10, if there is still an unacceptable phase difference, the controller 10 Another 'write output delay register' command may be issued to the second memory device, eg, the second memory device 100-2 of FIG. This sequence of operations may continue until the memory controller 10 obtains an acceptable phase difference. After the last memory device is commanded to adjust its own output delay, the memory controller 10 then instructs the first memory device with one additional unit delay value in the command packet, the phase difference being acceptable. Continue with the remaining memory devices until the range is reached.

The above procedure is shown in the flowchart of FIG. The method begins at block 9-1 with power on. At this point, all delay lines and device addresses are initialized. In block 9-2, the memory controller 10 uses the phase detector 11 to monitor the phase error between CKI / CKI # and CKO / CKO #. If there is a phase error, yes path 9-3, phase detector 11 asserts the “PE” signal S11 in block 9-4. The command generator 12 then issues a 'write output delay register' command with a value of &quot; ODR + 1 &quot; for each memory device from the first memory device to the last memory device, one during the monitoring of the phase error. do. In block 9-6, if there is still a phase error, the yes path, method continues back in block 9-4. If there is no phase error, no path block 9-6, phase calibration is completed in block 9-7. Similarly, if no phase error is detected in block 9-3, the method ends and phase calibration is completed in block 9-7.

Table 3 is an example command packet definition for a write output delay register command. The first byte includes a 'device address (= DA)' portion, the second byte includes a command code (= CMD = FBh), and the third byte includes a register value (ODR <0: 1>). In some embodiments, a broadcast address is provided, for example FFh. If the DA is set to a broadcast address, that means that the command is a broadcasting command, so that all memory devices are expected to execute the command. Otherwise, only the specific memory device that matches the DA will execute the command. In some embodiments, a 'read output delay register' is implemented to give the controller 10 more flexibility. For example, it can be used by the controller to read values from all memory devices and then rearrange the settings among the devices as needed.

Example Command Packet Definitions for a Controller Programmable Delay Line Register Command First byte Second byte Third byte Write Output Delay Register (ODR) DA FBh ODR <0: 1>

* Note:

1) If DA (device address) is FFh (= 255d), it is a broadcasting command, so all devices will respond to the command.

2) DA = device address

Table 4 is an exemplary bit definition of the output delay register (= ODR). It is entirely illustrative of the definition, and thus, if the system configuration requires more granular granularity for unit delay adjustment, this table is easily extended to facilitate more manageability in terms of programmable delay lines. Can be.

Example Bit Definitions of Duty Cycle Registers and Output Delay Registers Explanation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Output delay
Register bits Inverted for future use
(low) DCR <1> DCR <0>

10 is an example of a timing diagram of a 'write output delay register' command packet sequence based on SDR (single data rate) operation. In this timing diagram, at time T1, the rising edge of CKI or falling edge of CKI # latches the high state of CSI and simultaneously latches DA (= device address = 0Oh) information on the Dn port (s). At the next rising edge time T2, the memory device latches the CMD (= command = FBh) information, and at the third rising edge, latches the ODR (= output delay register value = 01h) information. The CSO output and Qn output ports echo the CSI input and Dn input signals, respectively, with two clock latencies of tIOL (= input to output latency). There is another latency specification, tWODR (= Write Output Delay Register Latency), which is for the processing time of the write output delay register packet in the memory chip and is the controller programmable delay line (2) (= PDL2 105). For the processing delay of the output delay adjustment in AD). In some embodiments, the tWODR value is set as four clock cycles as shown in FIG. After tWODR (eg, at T8), memory controller 10 may issue any other command packet to the memory device.

More generally, one embodiment of the application takes into account methods and circuits for implementing output delay adjustment embodiments in which a delayed version of at least one input signal is generated and the at least one input signal comprises at least a clock signal. . There may be additional input signals that are transferred between devices that are not subject to output delay adjustment. For some signals, generating a delayed version of the input signal for output involves conditionally generating a delayed version of the input signal for output. That is, some signals can be conditionally transferred between adjacent devices. The specific example in which the input data signal of the memory device is sometimes transferred to the next memory device is described below.

The above embodiments assume the use of a programmable delay line consisting of the same unit delay block. In some embodiments, the programmable delay line is such as a “coarse” and “fine” delay line to enable more programmability of delay adjustment for duty cycle correction and / or output delay adjustment. It is divided into two or more sections.

In the detailed example described, there is a second flip-flop near the output and a first flip-flop near the input for each signal. This is to generate two clock cycle latency. Of course, it is understood that other clock latencies may result by including different functionality between the input and the output.

In the described embodiments, the output delay line is located after the last flip-flop that is located near the output for each signal. In some embodiments, the output delay line is located before the last flip-flop.

In some embodiments, it is assumed that devices that are connected in a serial connection are substantially the same. In some embodiments, there are substantially the same memory devices. In other embodiments, different types of memory devices may be utilized as long as they have compatible serial interfaces.

Detailed embodiments have been assumed in which differential clock signals are employed. More generally, single ended or differential clock signals may be used. Similarly, any other input / output signal may be single ended or differential.

In some embodiments, a single multi-chip package (MCP) is provided that includes a plurality of memory devices and a controller that can be operated as described.

The methods and apparatus described herein assume a serial connection architecture featuring a series of memory devices and controllers connected in a ring. In such embodiments, the memory device is a slave device and the memory controller is a master device. More generally, the methods and apparatus described herein are common among adjacent devices having devices configured to act as master devices that control duty cycle calibration and / or phase calibration performed by slave devices. It can be applied to any kind of semiconductor integrated circuit system having any kind of semiconductor integrated circuit devices configured as slave devices in a serial connection configuration with an interface of. Examples of integrated circuit types include central processing unit, graphics processing unit, display controller IC, disk drive IC, and NAND flash EEPROM, NOR flash EEPROM, AND flash EEPROM, DiNOR flash EEPROM, serial flash EEPROM, DRAM, SRAM, ROM, Memory devices such as EPROM, FRAM, MRAM, PCRAM, and the like.

Some embodiments described herein assume a single data rate operation. More generally, the above embodiments may be applied to systems having a double rate operation with other data rates, such as appropriate modifications that would be understood by those skilled in the art upon reading the present disclosure.

Many modifications and variations of the present invention are possible in light of the above teachings. It is, therefore, to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.

Claims (60)

A method for a slave device of a plurality of serially connected slave devices,
Receiving a command from the master device that specifies an adjustment to a clock duty cycle;
Receiving an input clock signal;
Generating a duty cycle corrected clock signal from the input clock signal in accordance with the command; And
Outputting the duty cycle corrected clock signal. The method according to claim 1,
The slave device is a memory device and the master device is a memory controller. The method according to claim 1,
Receiving a command from a master device specifying a manner in which the slave device adjusts a delay to be applied to at least one signal output by the slave device;
Receiving at least one input signal comprising at least the input clock signal;
For each of the at least one input signal:
Generating a delayed version of the input signal in accordance with the command; And
Outputting a delayed version of the input signal, the delayed version of the input clock signal further comprising a delayed version of the duty cycle corrected clock signal. The method according to claim 1,
Receiving a command from a master device that specifies an adjustment to the clock duty cycle includes the command identifier identifying a command as a duty cycle correction command and further comprising data indicating how to adjust the duty cycle. Receiving the method. The method according to claim 4,
Receiving the command further comprises receiving a device address indicating which device (s) will act as a slave device to execute the command. The method according to claim 5,
If the command has a device address that matches the device address of the slave device, executing the step of generating the duty cycle corrected clock signal in accordance with the command;
If the command has a device address that is a broadcast device address, further comprising generating the duty cycle corrected clock signal in accordance with the command. The method according to claim 4,
Generating the duty cycle corrected clock signal may include:
a) generating a half rate clock signal from the input clock signal;
b) delaying the half rate clock signal by a selected one of a plurality of delays to produce a delayed half rate clock signal; And
c) combining the half rate clock signal with the delayed half rate clock signal to generate the duty cycle corrected clock signal. The method according to claim 7,
Data indicative of a manner of adjusting the duty cycle correction comprises an indication of a selected one of the plurality of delays. A method for a memory system comprising a plurality of serially connected slave devices and a master device including at least a first slave device and a last slave device, the method comprising:
In the master device,
a) outputting a first clock signal functioning as an input clock signal of the first slave device;
b) receiving a second clock signal that is an output clock signal of the last slave device;
c) generating a duty cycle correction command as a function of the duty cycle of the second clock signal and outputting the duty cycle correction command;
In the first slave device of the plurality of serially connected slave devices,
a) receiving the first clock signal from the master device as an input clock signal of the first slave device;
b) generating an output clock signal from the input signal;
In each of the other slave devices of the plurality of serially connected slave devices,
a) receiving an output clock signal of a previous slave device as an input clock signal of the slave device;
b) generating an output clock signal from the input clock signal;
In each of at least one serially connected device of the plurality of serially connected devices serving as a slave device,
a) receiving the duty cycle correction command;
b) generating a duty cycle corrected clock signal from the input clock signal in accordance with the duty cycle correct command; And
c) outputting the duty cycle corrected clock signal as an output clock signal of the slave device. The method according to claim 9,
Each slave device is a memory device and the master device is a memory controller. The method according to claim 9 or 10,
In the master device,
a) outputting at least one output signal, the at least one output signal comprising the first clock signal to function as an input clock signal of the first slave device;
b) receiving a second clock signal that is an output clock signal of the last slave device;
c) determining an amount of phase offset between the first clock signal and the second clock signal;
d) generating an output delay adjustment command as a function of a phase offset between the first clock signal and the second clock signal to output the output delay adjustment command. The method according to claim 9 or 10,
Generating a duty cycle calibration command and outputting the duty cycle calibration command as a function of the duty cycle of the second clock signal may include a duty cycle for execution by any designated slave device of the plurality of serially connected slave devices. Generating a calibration command. The method of claim 12,
Generating a duty cycle calibration command and outputting the duty cycle calibration command as a function of the duty cycle of the second clock signal may include generating a duty cycle calibration command for execution by all of the plurality of serially connected slave devices. Method comprising the same. The method according to claim 9,
Receiving the duty cycle correction command comprises receiving the command including a command identifier identifying the command as a duty cycle correction command and including data indicating how to adjust the duty cycle. The method according to claim 14,
Generating the duty cycle corrected clock signal may include:
a) generating a half rate clock signal from the input clock signal;
b) delaying the half rate clock signal by a selected one of a plurality of delays to produce a delayed half rate clock signal;
c) combining the half rate clock signal with the delayed half rate clock signal to generate the duty cycle corrected clock signal. The method according to claim 15,
And data indicating how to adjust the duty cycle correction comprises an indication of a selected one of the plurality of delays. A slave device for use in an array comprising a plurality of serially connected slave devices,
Command input for receiving a command from the master device specifying an adjustment for the duty cycle;
A clock input for receiving an input clock signal;
A duty cycle correction circuit for generating a duty cycle corrected clock signal from the clock input in accordance with a control command; And
And a clock output for outputting the duty cycle corrected clock signal. 18. The method of claim 17,
And the slave device is a memory device. The method according to claim 17 or 18,
The command input is also for receiving a command from the master device specifying an adjustment for an output delay;
An output delay adjustment circuit for generating a delayed clock signal from the duty cycle corrected clock signal in accordance with the command;
And a clock output for outputting the duty cycle corrected clock signal outputs the delayed clock signal. The method according to claim 17 or 18,
Further comprising a command processing circuit for processing the command,
The command is
A command identifier identifying the command as a duty cycle correction command; And
A slave device comprising data indicating how to adjust the duty cycle. The method of claim 20,
Further comprising a device address register,
The command further includes a device address indicating which slave device will execute the command, wherein the slave device is configured to execute the command if the device address matches the contents of the device address register. . The method according to any one of claims 17 to 21,
The duty cycle correction circuit,
a) clock divider circuit for generating a half rate clock signal from said input clock signal;
b) a delay circuit for delaying said half rate clock signal by a selected one of a plurality of delays to produce a delayed half rate clock signal;
c) a combiner for combining the half rate clock signal with the delayed half rate clock signal to produce the duty cycle corrected clock signal. The method according to claim 22,
The delay circuit comprises an M unit delay element (M> = 2) and the duty cycle correction circuit is
Decode the signal received at the N input line (N> = 1) and delay the half rate clock signal to produce the delayed half rate clock signal, decoded by the selection of how much of the unit delay element is to be operated. Further comprising an N to M decoder. As a system,
A plurality of serially connected devices acting as slave devices according to claim 17, including at least a first slave device and a final slave device;
A master device coupled to the first slave device and to the last slave device;
The master device is configured to output a first clock signal functioning as an input clock signal of the first slave device;
A clock input for receiving a second clock signal that is an output clock signal of the last slave device;
A duty detector for determining a duty cycle of the second clock signal;
A command generator for generating a duty cycle correction command that specifies adjustment to a clock duty cycle as a function of the duty cycle of the second clock signal,
Among a plurality of serially connected devices serving as slave devices, the first slave device is
a) receiving the first clock signal from the master device as an input clock signal of the first slave device;
b) generating an output clock signal from the input clock signal,
Each other slave device of the plurality of serially connected devices serving as slave devices,
a) receiving the output clock signal of the previous slave device as the input clock signal of the slave device;
b) generate an output clock signal from the input clock signal;
At least one of the plurality of serially connected slave devices,
a) receive the duty cycle correction command;
b) generate a duty cycle corrected clock signal in accordance with a control command;
c) output the duty cycle corrected clock signal as an output clock signal of a slave device. The method of claim 24,
The system is a memory system, each slave device is a memory device, and the master device is a memory controller. The method according to claim 24 or 25,
A phase detector for determining an amount of phase offset between the first clock signal and the second clock signal,
The command generator also generates an output delay adjustment command as a function of the amount of the phase offset,
The first slave device of the plurality of serially connected slave devices,
a) receiving the first clock signal from the master device as an input clock signal of the first slave device;
b) generate an output clock signal from the input clock signal;
Each other slave device of the plurality of serially connected slave devices,
a) receiving an output clock signal of a previous slave device as an input clock signal of the slave device;
b) generate an output clock signal from the input clock signal;
At least one of the plurality of serially connected slave devices,
a) receiving the output delay adjustment command,
b) generating an output clock signal of the device by delaying an input clock signal of the device in accordance with the control command. The method according to claim 24 or 25,
The command generator generates a duty cycle correction command as a function of the duty cycle of the second clock signal and executes the duty cycle correction command for execution by a designated serial connection device among a plurality of serial connection devices serving as the slave device. And output the duty cycle correction command by generating a. The method according to claim 24 or 25,
The command generator generates a duty cycle correction command as a function of the duty cycle of the second clock signal and generates a duty cycle correction command for execution by all of a plurality of serially connected devices serving as the slave device. Memory system to output the duty cycle correction command. The method according to any one of claims 24 to 28,
Receiving the duty cycle correction command comprises receiving the command including a command identifier identifying the command as a duty cycle correction command and including data indicating how to adjust the duty cycle. A method for a slave device of a plurality of serially connected slave devices,
Receiving a command from a master device specifying a manner in which the slave device adjusts a delay to be applied to at least one signal output by the slave device;
Receiving at least one input signal comprising at least an input clock signal;
For each of the at least one input signal:
Generating a delayed version of the input signal in accordance with the command;
Outputting a delayed version of the input signal. The method of claim 30,
The slave device is a memory device and the master device is a memory controller. The method of claim 30 or 31,
Outputting a data output signal,
At least one of the input signals comprises a data input signal, and outputting a delayed version of the data input signal,
a) sometimes the data output signal is a delayed version of the data input signal;
b) sometimes, after applying the delay to a signal generated locally for the slave device according to the command, such that the data output signal is a delayed version of the signal generated locally for the slave device;
Executed as part of outputting the data output signal. The method of claim 30 or 31,
Receiving from the master device a command specifying an adjustment to a delay to be applied to at least one signal output by the slave device comprises receiving the command comprising a command identifier identifying the command as an output delay adjustment command. And the command further comprises data indicating how to adjust the delay. The method according to claim 33,
Receiving the command further comprises receiving a device address indicating which device (s) serve as a slave device to execute the command. 35. The method of claim 34,
If the command has a device address that matches the device address of the slave device, executing for each of the at least one input signal, generating a delayed version of the input signal in accordance with the command; And
If the command has a device address that is a broadcast device address, further comprising: for each of the at least one input signal, generating a delayed version of the input signal in accordance with the command. The method according to claim 33,
Generating a delayed version of the input signal for each input signal,
a) delaying the input signal by a selected one of a plurality of delays to produce a delayed version of the input signal. 37. The method of claim 36,
Data indicative of a manner of adjusting the delay comprises an indication of a selected one of the plurality of delays. The method of claim 30,
The plurality of input signals,
Clock signal;
Command strobe signal;
Data strobe signal;
A data signal comprising a command and data. A method for a memory system comprising a plurality of serially connected devices and a master device, which serve as slave devices, comprising at least a first slave device and a final slave device, the method comprising:
In the master device,
a) outputting at least one output signal comprising a first clock signal to function as an input clock signal of the first slave device;
b) receiving a second clock signal that is an output clock signal of the last slave device;
c) determining an amount of phase offset between the first clock signal and the second clock signal;
d) generating an output delay adjustment command as a function of a phase offset between the first clock signal and the second clock signal and outputting the output delay adjustment command. The method of claim 39,
Each slave device is a memory device and the master device is a memory controller. The method of claim 39 or 40,
A first slave device of a plurality of serially connected devices serving as the slave device,
a) receiving the at least one output signal from the master device as corresponding to at least one input signal of the first slave device;
b) for each input signal, generating an output signal based on the input signal;
In each other slave device of the plurality of serially connected devices serving as slave devices,
a) receiving output signal (s) of a previous slave device corresponding to at least one input signal of the slave device;
b) for each input signal, generating an output signal based on the input signal;
In at least one slave device of the slave device,
a) receiving the output delay adjustment command; And
b) generating the output signal (s) by generating a delayed version of the input signal (s) in accordance with the output delay adjustment command. The method of claim 41,
At least one output signal of the master device further comprises a plurality of output signal (s). The method of claim 39 or 40,
Generating a delay adjust command comprises generating a delay adjust command for execution by a designated serial connected slave device of the plurality of serial connected slave devices. The method of claim 39 or 40,
Generating a delay adjustment command includes generating a delay adjustment command for execution by all of the plurality of serially connected slave devices. The method of claim 41,
Generating a delayed version of the input signal (s) in accordance with the output delay adjustment command comprises generating a delayed version of the input signal (s) delayed by a selected one of a plurality of delays. The method of claim 45,
Generating a delay adjustment command comprises generating the command including a command identifier identifying the command as an output delay adjustment command and including data indicating how to adjust the delay. The method of claim 46,
Data indicative of a manner of adjusting the delay comprises an indication of a selected one of the plurality of delays. The method of claim 39 or 40,
Further comprising the master device outputting an output delay adjustment command that adjusts the delay by adding a delay of one unit delay element in one slave device at a time until the phase offset can be allowed; Way. The method of claim 39 or 40,
The plurality of input signals,
Clock signal;
Command strobe signal;
Data strobe signal;
A data signal comprising a command and data. A slave device for use in an array comprising a plurality of serially connected slave devices,
Command input for receiving a command from the master device that specifies a manner of performing output delay adjustment;
A clock input for receiving an input clock signal;
An output delay adjustment circuit for generating a delayed clock signal from the clock input in accordance with the command; And
And a clock output for outputting the delayed clock signal. The method of claim 50,
And the slave device is a memory device. The method of claim 50 or 51,
A command processing circuit for processing the command, wherein the command includes a command identifier identifying the command as an output delay adjustment command and includes data indicating how to adjust the output delay. The method of claim 52, wherein
Further comprising a device address register,
The command further includes a device address indicating which slave device will execute the command, wherein the slave device is configured to execute the command if the device identifier matches the contents of the device address register. The method of claim 50 or 51,
The output delay adjustment circuit,
And for each of a plurality of input signals, a delay circuit including the input clock signal to delay the input signal by a selected one of a plurality of delays to produce a delayed version of the input signal. The method of claim 54, wherein
Each output delay circuit includes an M unit delay element (where M> = 2) and the duty cycle correction circuit is
Further comprising an N to M decoder to decode a signal received on an N input line (where N> = 1), producing a delayed version of the input signal, with a selection of how much of the unit delay element is to be operated, Slave device. As a memory system,
A plurality of serially connected slave devices as claimed in claim 47 comprising at least a first slave device and a final slave device;
A master device coupled to the first slave device and to the last slave device;
The master device is configured to output a first clock signal functioning as an input clock signal of the first slave device;
A clock input for receiving a second clock signal that is an output clock signal of the last slave device;
A phase detector for determining an amount of phase offset between the first clock signal and the second clock signal;
A command generator for generating an output delay adjustment command as a function of the amount of phase offset,
The first slave device of the plurality of serially connected slave devices,
a) receiving the first clock signal from the master device as an input clock signal of the first slave device;
b) generating an output clock signal from the input clock signal,
Each of the other slave device of the plurality of serially connected slave devices,
a) receiving an output clock signal of a previous slave device as an input clock signal of the slave device;
b) generate an output clock signal from the input clock signal;
At least one of the plurality of serially connected slave devices,
a) receiving the output delay adjustment command;
b) generating an output clock signal of the device by delaying an input clock signal of the device in accordance with the control command. The method of claim 56, wherein
The system is a memory system, each slave device is a memory device, and the master device is a memory controller. The method of claim 56 or 57,
And the command generator is configured to generate the output delay adjustment command for execution by a designated serial connected slave device of the plurality of serial connected slave devices. The method of claim 56 or 57,
And the command generator is configured to generate the output delay adjustment for execution by all of the plurality of serially connected slave devices. The method of claim 56 or 57,
Generating an output delay adjustment command includes generating the command including a command identifier identifying the command as an output delay adjustment command and including data indicating how to adjust the output delay.

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