KR20110078186A - Method for fabricating system in package - Google Patents

Abstract

PURPOSE: A method for manufacturing a system in a package is provided to increase production yield while reducing production costs by integrating at least three semiconductor devices without using a penetration electrode. CONSTITUTION: In a method for manufacturing a system in a package, a first semiconductor device(301), a second semiconductor device(401), and a third semiconductor device(501) are provided. The first semiconductor device is integrated as a filp-chip type. The first semiconductor device is directly connected to the second and third semiconductor device. The second semiconductor device and the third semiconductor device are electrically connected through the first semiconductor device. The first semiconductor device and the second and third semiconductor device are combined through copper wirings(331,431,531) and copper to copper Bonding.

Description

Method for Fabricating System In Package

The present invention relates to a method of manufacturing a semiconductor device. In particular, the present invention relates to a method and system for manufacturing a system in package by integrating three or more semiconductor devices vertically and horizontally.

Recently, in order to reproduce a complex circuit configuration in semiconductor technology, not only a fine circuit manufacturing technology of a semiconductor process but also a semiconductor device manufacturing method through stacking of various semiconductor chips are being actively developed. In other words, as the demand for high integration of a single chip increases as is well known, various types of semiconductor devices are stacked in a chip or wafer state and connected to through via holes or through wafer vias. There is a lot of research into the package technology. Nevertheless, the actual commercialization is not active yet, because the manufacturing cost of the package, a system for achieving high integration, is high.

The reason for the high cost of manufacturing the system in package in the related art is related to the through-electrodes required for the existing system in the package. The through electrode generally means a via hole penetrating tens to hundreds of micrometers, and means a via hole penetrating a semiconductor device. In the prior art, the connection between semiconductor devices is achieved through such a through electrode.

However, since the time and cost of implementing such a through electrode are several to several tens of times of a general semiconductor process, the process cost increases. In addition, defects often occur when the through electrode is formed due to lack of stabilization of the technology, and the yield of the product is significantly reduced due to the defect of the bump used for the coupling between the elements after the through electrode is formed. As described above, since the defects generated during the generation of the package consume a plurality of elements related to the generation of the package due to one defect, the process cost of the product is further increased.

Figure 1 shows an example of a system in a package formed by the prior art as described above. Three or more semiconductor devices 300, 400, and 500 are vertically integrated, and a predetermined bonding agent 320 exists between each device. Bumps 310 are disposed to form through electrodes 350 for connection between the devices.

In order to solve the above problems of the prior art, an object of the present invention is to reduce the cost of the product and to improve the yield by integrating without using a through electrode in a package process that is a system integrating three or more devices. .

In order to solve the above problems, an aspect of the present invention, in the method of manufacturing a system in a package (system in package) by integrating three or more semiconductor devices, providing a first, second and third semiconductor device And Cu-to-Cu bonding after the first semiconductor device faces the second and third semiconductor devices in a flip-chip form, wherein the flip-chip includes: The second and third semiconductor devices may be directly electrically connected to each other by a first semiconductor device having a chip shape.

According to a preferred embodiment of the present invention, the Cu-to-Cu bonding step, the step of forming a via hole in the first, second and third semiconductor device, and the first, second and third semiconductor device Forming an insulating film, a barrier metal film and a seed film in the via hole, forming a photoresist pattern on the first, second and third semiconductor devices on which the insulating film, the barrier metal film and the seed film are formed; Forming a copper plating film in the via holes of the second and third semiconductor devices;

According to a preferred embodiment of the present invention, the copper plating film of the first semiconductor device is bonded to the copper plating film of each of the second and third semiconductor devices to electrically connect the second and third semiconductor devices.

According to a preferred embodiment of the present invention, the copper plated films of the first, second and third semiconductor devices protrude out of the substrate by a height of 10 to 10000 mm.

According to a preferred embodiment of the present invention, in the bonding step, the copper plated films of the first, second and third semiconductor devices activated using plasma are bonded at 200 to 800 degrees.

According to a preferred embodiment of the present invention, the method may further include connecting the second and third semiconductor devices to the PCB substrate.

According to the present invention, by fabricating a system-in-package by integrating three or more semiconductor devices without a through electrode, a process cost can be lowered and a yield can be increased.

Hereinafter, the operating principle of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, if it is determined that a detailed description of a known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, terms to be described below are terms defined in consideration of functions in the present invention, which may vary according to a user's or operator's intention or custom. Therefore, the definition should be based on the contents throughout this specification.

On the other hand, when described as being on or above a layer or other layer or semiconductor substrate, the layer may be in direct contact with another layer or semiconductor substrate, except where expressly stated. It may be present, or a third layer may be interposed therebetween. In addition, in the drawings, the thickness or size of each side is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. Also, the size of each component does not fully reflect its actual size.

2 illustrates a system in package formed in accordance with one embodiment of the present invention.

As shown in FIG. 2, the system in package according to the present invention is formed by integrating three or more semiconductor devices. Specifically, the first semiconductor element 301 including the transistor 341, the second semiconductor element 401, and the third semiconductor element 501 are electrically connected to each other. The first semiconductor device 301 is integrated in the form of a flip chip to serve as a reference for electrically connecting the second semiconductor device and the third semiconductor device. That is, the first semiconductor element 301 is directly connected to the second and third semiconductor elements 401 and 501, respectively, and the second semiconductor element 401 and the third semiconductor element 501 are connected to each other through the first semiconductor element. Can be electrically connected.

In the first semiconductor device 301 and the second and third semiconductor devices 401 and 501, the copper wiring parts 331, 431, and 531 may be coupled through Cu-to-Cu bonding. . As will be described in more detail with reference to FIGS. 3A to 3E, Cu-to-Cu bonding refers to a technique in which copper wires activated by plasma are bonded in a high temperature atmosphere, for example, an atmosphere of 200 to 800 degrees.

Meanwhile, the second and third semiconductor devices of the system-in-package formed as described above may be used in connection with a PCB substrate as necessary.

Integrating three or more elements vertically and horizontally as described above eliminates the need to form through electrodes, thereby reducing process costs and improving yield.

3A to 3E illustrate a bonding method between semiconductor devices for manufacturing a system in package according to an embodiment of the present invention.

FIG. 3A illustrates the first semiconductor substrate 100. The via hole 110 may be formed on the semiconductor substrate 100 through a silicon etching process such as, for example, a single damascene or dual damascene process. ). Next, an insulating film 120, a barrier metal film 130, and a seed film 140 are deposited on the substrate 100 on which the via holes 110 are formed.

For example, the insulating film 120 may form SiO ₂ , SiN, or SiON to a thickness of 10 to 5000 kW using a chemical vapor deposition (CVD) method. In addition, the insulating film 120 may use a thermal oxidation method.

The barrier metal layer 130 is formed to prevent diffusion of copper, which is a buried material of the via hole 110. For example, chemical vapor deposition (PVD), physical vapor deposition (CVD), or atomic layer deposition (ALD) method may be used. By using Ta, TaN, TiSiN or TaSiN can be formed to a thickness of 10 ~ 5000Å.

The seed film 140 is formed along the step of the barrier metal film 130 to facilitate deposition of a metal material, which is a subsequent process, on the barrier metal film 130. The seed film 140 is formed of, for example, Cu, Au, or Pt by a thickness of 10 to 5000 kW using chemical vapor deposition (PVD), physical vapor deposition (CVD), or atomic layer deposition (ALD).

Next, as shown in FIG. 3B, after the photoresist film is coated on the seed film 140, the photoresist film formed on the seed film 140 is exposed and developed to expose the via holes 110, thereby forming a photoresist pattern ( 150). The photoresist pattern 150 is intended to form a copper wiring having a predetermined thickness or more than the seed film 140 in a subsequent process. It may be formed to a predetermined size, for example, larger than about 1 to 500㎛.

Thereafter, as illustrated in FIG. 3C, a copper plating layer 160 is formed by an electroplating method for via gap-fill on the first semiconductor substrate 100 on which the photoresist pattern 150 is formed. When via gap fill, the plating layer 160 may be formed by using a reverse pulse plating method, which is one of electroplating processes, and the plating layer 160 may be planarized. At this time, in order to planarize the plating film 160, the surface of the final plating film 160 is formed not to be higher than the photoresist pattern 150.

As described above, the plated film 160 should be protruded by a predetermined thickness on the substrate. In order to use the thermo compression method when the semiconductor devices are bonded as described below, the pressure around the copper plated film is increased. Because it must be passed to 160. Preferably, the plating film 160 is protruded, for example, about 10 to 10000 mm when viewed based on the substrate 100 layer.

3D, the seed layer 140, the barrier metal layer 130, and the insulating layer 120 are etched by removing the photoresist pattern 150 and using the plating layer 160 as an etching mask. do. Accordingly, the via hole is in a state in which the insulating film 120a, the barrier metal film 130a, the seed film 140a and the plating film 160a are stacked.

Next, the second semiconductor device 200 is manufactured and prepared according to the above-described process. That is, after the via hole is formed on the substrate 200, the insulating film 220a, the barrier metal film 230a, and the seed film 240a are deposited, a photoresist pattern is formed, and the copper plating film 260a is formed. After that, the photoresist pattern is removed.

3E, the surface of the plated film 160a of the manufactured first semiconductor substrate 100 and the surface of the plated film 260a of the second semiconductor substrate 200 are brought into contact with each other. Thereafter, the first and second semiconductor substrates 100 and 200 are bonded by applying predetermined heat and pressure. Therefore, the activated copper wiring portions 160a and 260a may be directly in contact with each other.

Although the embodiments have been described for the understanding of the present invention as described above, it will be understood by those skilled in the art, the present invention is not limited to the specific embodiments described herein, but variously without departing from the scope of the present invention. May be modified, changed and replaced. Therefore, it is intended that the present invention cover all modifications and variations that fall within the true spirit and scope of the present invention.

1 illustrates a system in a package formed by a through electrode according to the prior art.

2 illustrates a system in package formed in accordance with one embodiment of the present invention.

3A to 3E illustrate a bonding method between semiconductor devices for manufacturing a system in package according to an embodiment of the present invention.

Claims (6)

In a method of manufacturing a system in package by integrating three or more semiconductor devices, Providing first, second and third semiconductor devices, Cu-to-Cu bonding (Cu-to-Cu bonding) after the first semiconductor device to face the second and third semiconductor devices in the form of flip-chip, The second and third semiconductor devices may be directly electrically connected to each other by the first semiconductor device having the flip chip shape. System-in-Package Manufacturing Method. The method of claim 1, The Cu-to-Cu bonding step, Forming via holes in the first, second and third semiconductor devices; Forming an insulating film, a barrier metal film and a seed film in the via holes of the first, second and third semiconductor devices; Forming a photoresist pattern on the first, second and third semiconductor devices on which the insulating film, the barrier metal film and the seed film are formed; Forming a copper plating film in a via hole of the first, second and third semiconductor devices; And bonding the copper plated film of the first semiconductor device and the copper plated film of the second and third semiconductor devices to each other and then bonding them. System-in-Package Manufacturing Method. The method of claim 2, The copper plating film of the first semiconductor device is bonded to the copper plating film of each of the second and third semiconductor devices to electrically connect the second and third semiconductor devices. System-in-Package Manufacturing Method. The method of claim 2, The copper plated films of the first, second and third semiconductor devices protrude outwardly from the substrate by a height of 10 to 10000 Å. System-in-Package Manufacturing Method. The method of claim 2, In the bonding step, the copper plating films of the first, second and third semiconductor devices activated by using plasma are bonded at 200 to 800 degrees. System-in-Package Manufacturing Method The method of claim 1 And wire connecting the second and third semiconductor devices to a PCB substrate. System-in-Package Manufacturing Method.

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