KR20110076692A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: A semiconductor integrated circuit is provided to secure fast operation speed without signal delay by forming a switching unit with a transmission gate. CONSTITUTION: A bump pad(110) inputs and outputs data. A probe pad(120) tests an input/output probe. A data output unit(130) outputs data from the internal circuit to the bump pad or probe pad. A data input unit transmits data inputted from the bump pad or probe pad to the internal circuit. A switching unit(150) connects the data output unit and the data input unit to the probe pad in response to a probe test mode signal. An ESD(Electro Static Discharge) protection circuit is connected between the bump pad and data output unit and the data input unit, and between the probe pad and the data input unit and the data output unit.

Description

Semiconductor Integrated Circuits {SEMICONDUCTOR INTEGRATED CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to a test related technology of a semiconductor integrated circuit having bump pads.

Four key technologies that enable the rapid development of electronics today are semiconductor technology, semiconductor packaging technology, manufacturing technology and software technology. Semiconductor technology is developing with sub-micron line widths, more than one million cells, high speeds, and much heat dissipation. It is decided by. Indeed, the overall electrical signal delay of high-speed electronics is caused by package delays between 50% and more, which is expected to be more than 80% for large systems in the future. have.

With the advent of the digital network information age, products such as multimedia products, digital home appliances, and personal digital devices are growing rapidly. These products require very small size, high electrical performance, high performance and low cost. One of the package methods developed to satisfy these requirements is a chip on chip package method. This approach allows a large amount of memory to be packed together with a logic IC in the same package. The data transfer rate between memory and logic is also very fast. Until recently, mounting memory and logic in the same package required using a system on chip (SoC) using DRAM technology or a system in package (SiP) method of connecting the chips together using wire bonding. Each method has its advantages and disadvantages, but it was not easy to achieve high-speed data transfer and large memory at the same time between the memory chip and logic IC. CoC packaging technology, however, meets both requirements at the same time and can significantly lower manufacturing costs than 'Merged DRAM'.

The CoC packaging technology enabled both high-speed data transfer and large memory at the same time because the memory chips were stacked with logic ICs connected via micro bumps. By using discrete memory chips, the memory capacities of complex DRAMs can be removed essentially. In addition, by increasing the bit width and increasing the amount of micro bumps, data can be transmitted faster. This is due to the fact that the micro bumps are only a few tens of micrometers (μm) in diameter, resulting in lower resistance, inductance, parasitic capacitance and other characteristics, making it easier to increase the operating frequency. Herein, bump refers to a conductive protrusion for directly connecting a semiconductor chip with another semiconductor chip.

In order to connect a memory chip and a logic chip using CoC technology, bumps are formed on each chip, and then the memory chip and the logic chip are connected to each other to form a single chip. In the case of memory, the test is conducted to ensure its operation. When using CoC technology, data is inputted and outputted through bumps. However, the bumps are so small that you can run into problems with testing. This is because the bumps of the conventional semiconductor test equipment are too small to probe the test probe into the bumps.

The present invention seeks to provide a semiconductor integrated circuit that enables wafer level testing of a semiconductor integrated circuit having input / output bump pads.

According to an aspect of the present invention, a bump pad for data input / output, a probe pad for input / output probe test, a data output unit for outputting data transmitted from an internal circuit to the bump pad or the probe pad, bump And a data input unit for transferring the data input through the pad or the probe pad to the internal circuit, and a switching unit for connecting the data output unit and the data input unit and the probe pad in response to the probe test mode signal, wherein the switching unit is a transmission gate. A semiconductor integrated circuit is provided.

The present invention enables the test at the wafer level by using the test probe pad, and the switching unit is configured as a transmission gate to secure a fast operation speed without signal delay.

DETAILED DESCRIPTION Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

1 is a block diagram according to an embodiment of the present invention.

Referring to FIG. 1, an embodiment of the present invention includes a bump pad 110, a probe pad 120, a data output unit 130, a data input unit 140, and a switching unit 150.

An operation of an embodiment of the present invention will be described with reference to FIG. 1.

Firstly, bumps are conductive protrusions for directly connecting semiconductor chips with other semiconductor chips. The bumps are very small in size, for example micro-bumps are only a few tens of micrometers in diameter.

The bump pad 110 refers to a pad through which data is input / output between a semiconductor chip (ex: memory chip) and an external system (ex: logic IC). Input / output of data is made through one bump pad. The probe pad 120 refers to a pad that is large enough to accommodate the probe of the semiconductor test equipment.

First, data input / output operations between an external system and a semiconductor chip will be described.

In the data output operation, first, data loaded on the global input / output lines GIO <0: n> is received from the data output unit 130 and controlled, and output to the bump pad 110 in accordance with the output timing.

In the data input operation, data is applied to the data input unit 140 through the bump pad 110 from an external system. The data input unit 140 outputs the received data to the global input / output lines GIO <0: n>.

In the data input / output operation between the external system and the semiconductor chip as described above, the switching unit 150 is turned off, and the presence of the probe pad 120 does not affect the data transfer path.

Next, the operation during the test will be described.

First, the switching unit 150 is turned on in response to the probe test mode signal TM. Therefore, a data transfer path is formed between the probe pad 120, the data output unit 130, and the data input unit 140. Thereafter, the probe pad 120 probes the probe of the test equipment to input / output data between the test equipment and the semiconductor chip to test the semiconductor chip.

The switching unit 150 is a transmission gate formed by a transmission gate TG and a probe test mode signal TM for forming a data transfer path between the probe pad 110, the data input unit 130, and the data output unit 140. It consists of an inverter INV for controlling TG.

By implementing the switching unit 170 using only one transmission gate and one inverter, the delay of the probe test mode signal TM can be minimized, and the gain in area is generated due to the smaller area. .

3 is a block diagram according to another embodiment of the present invention.

Referring to FIG. 3, another embodiment of the present invention is an electrostatic discharge protection circuit 160 connected to the bump pad 110, and an electrostatic discharge protection circuit 160 connected between the probe pad 120 and the switching unit 150. It is the same as the configuration of FIG. 1 except for further including.

Electrostatic discharge (ESD) refers to a discharge phenomenon caused by static electricity, and may cause device destruction when ESD is generated in a semiconductor chip. High voltage static electricity generated momentarily on an external pad connected to an input or output circuit may cause a gate insulating layer breakdown in a semiconductor device, particularly a MOS device, and a transient current caused by static electricity may be a part of an input or output circuit. May cause destruction. Therefore, an electrostatic discharge protection circuit is provided at the input and output ends of the data to protect the semiconductor from such damage caused by ESD.

Although the technical spirit of the present invention has been described in detail according to the above embodiments, it should be noted that the above embodiments are for the purpose of description and not for the limitation. In addition, it will be understood by those skilled in the art that various implementations within the technical scope of the present invention are possible.

1 is a block diagram according to an embodiment of the present invention.

2 is a block diagram according to another embodiment of the present invention.

Claims (3)

Bump pads for data input / output; Probe pads for input / output probe testing; A data output unit for outputting data transferred from an internal circuit to the bump pad or the probe pad; A data input unit for transferring data input through the bump pad or the probe pad to the internal circuit; And And a switching unit for connecting the data output unit and the data input unit and the probe pad in response to a probe test mode signal. The switching unit is a semiconductor integrated circuit, characterized in that the transmission gate. The method of claim 1, And an electrostatic discharge protection circuit connected between the bump pad and the data output unit and the data input unit, and between the probe pad and the data input unit and the data output unit, respectively. The method of claim 1, The probe test mode signal is a signal that is activated inside or outside the semiconductor during a test operation.

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