KR20110001098A - Program Method of Nonvolatile Memory Device - Google Patents

Abstract

According to an aspect of the present invention, there is provided a nonvolatile memory device including multilevel cell blocks including memory cells capable of storing two or more bits of data; Programming data input according to a program command to some of the multi-level cell blocks in a single level cell program method; A first program execution step of generating a multi-level cell program command to program the stored data to the entire selected multi-level cell block when the stored data reaches the capacity to be programmed in the entire multi-level cell block; And a second program performing step of setting a second verification voltage higher than a first verification voltage level used in the first program performing step, and overlapping the stored data in the entire selected multi-level cell block. A program method of a volatile memory device is provided.

Program, MLC, SLC

Description

Method of programming a non volatile memory device

The present invention relates to a method of programming a nonvolatile memory device.

In general, flash memories are widely used in computers, memory cards, and the like because they have a function of electrically erasing data of cells collectively. In recent years, as the use of portable information devices such as mobile phones, PDAs, digital cameras, and the like proliferates, flash memory is widely used as a storage device instead of a hard disk. The mobile devices described above increasingly require large storage devices in order to provide various functions (eg, a video playback function). Various efforts have been made to meet that need. As one of such efforts, a multi-bit memory device for storing 2-bit data or more data bits in one memory cell has been proposed. A memory cell in which multi-bit data is stored per memory cell is called a multi-leveled cell (MLC). In contrast, a memory cell storing one bit of data per memory cell is called a single-level cell (SLC).

Flash memory devices employing multi-level cells are capable of increasing usable capacity, but increase the time required to write data. On the other hand, a flash memory device employing a single level cell has a relatively small usable capacity, but has a high operating speed compared to MLC because the time required for writing data is short.

Accordingly, an aspect of the present invention is to provide a method of programming a nonvolatile memory device capable of increasing data reliability while minimizing interference between memory cells and increasing data reliability.

Program method of a nonvolatile memory device according to an aspect of the present invention,

Providing a nonvolatile memory device including multilevel cell blocks including memory cells capable of storing two or more bits of data; Programming data input according to a program command to some of the multi-level cell blocks in a single level cell program method; A first program execution step of generating a multi-level cell program command to program the stored data to the entire selected multi-level cell block when the stored data reaches the capacity to be programmed in the entire multi-level cell block; And a second program performing step of setting a second verification voltage higher than a first verification voltage level used in the first program performing step, and overlapping the stored data in the entire selected multi-level cell block.

The single level cell program method may be configured to program only one bit information into memory cells of the multi-level cell block.

The multi-level cell program command has a capacity that is enough to program the data stored in the data storing step to the entire multi-level cell block, so that the nonvolatile memory device does not perform any operation or the power-off command is executed. Characterized in that it is generated when input.

And setting a third verification voltage higher than a second verification voltage level used in the second program execution step, and repeating the stored data in the entire multi-level cell block.

When the program of the multi-level cell block is terminated, the stored data may be erased.

Program method of a nonvolatile memory device according to an aspect of the present invention,

Providing a non-volatile memory device including multi-level cell blocks including memory cells capable of storing two or more bits of data, and a buffer unit capable of temporarily storing data to be programmed; Temporarily storing data input according to a program command in the buffer unit; Performing a first program of generating a multi-level cell program command to program the stored data to the entire selected multi-level cell block when the data stored in the buffer unit has a capacity to be programmed in the entire multi-level cell block; And a second program performing step of setting a second verification voltage higher than a first verification voltage level used in the first program performing step, and overlapping the stored data in the entire selected multi-level cell block.

The buffer unit is characterized in that a separate storage means having a faster data storage speed than the speed of programming data in the multi-level cell block.

The multi-level cell program command has a capacity such that data stored in the buffer unit is programmed to the entire multi-level cell block, and a standby state in which the nonvolatile memory device does not operate or a power-off command is input. When it is generated.

And setting a third verification voltage higher than a second verification voltage level used in the second program execution step, and repeating the stored data in the entire multi-level cell block.

When the program of the multi-level cell block is terminated, the data stored in the selected multi-level cell block is deleted from the stored data.

As described above, the method of programming a nonvolatile memory device according to the present invention can improve the reliability of data by minimizing interference between memory cells while improving program speed.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

1 illustrates a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 1, the nonvolatile memory device 100 may include a memory cell array 110, a page buffer unit 120, a Y decoder 130, an X decoder 140, a voltage providing unit 150, and a controller 160. ).

The memory cell array 110 includes a multi level cell (MLC) block unit 111 and a single level cell (MLC) block unit 112.

The MLC block unit 111 includes first to Nth MLC blocks, and the SLC block unit 112 includes first to Kth SLC blocks.

The first through Nth MLC blocks include memory cells capable of storing two bits of data, and the first through Kth SLC blocks include memory cells capable of storing one bit of data.

Memory cells capable of storing two bits of data or memory cells capable of storing one bit of data are identical in structure.

The memory cells are connected to word lines WL and bit lines BL in the first to Nth MLC blocks and the first to Kth SLC blocks.

The page buffer unit 120 includes page buffers connected to one or more bit lines. Each page buffer includes latch circuits for temporary data storage and operates for program and read operations.

The Y decoder 130 provides a data input / output path of the plurality of page buffers to the page buffer unit 120, and the X decoder 140 may be configured to match the first to Nth MLC blocks in the memory cell array 110 according to a control signal. One of the first to K th SLC blocks is enabled, and a global word line (GWL) to which an operating voltage is input is connected to a word line of the enabled block.

The voltage provider 150 generates and provides an operating voltage for a program, data read or erase operation.

The controller 160 outputs a control signal for controlling a program, data read or erase operation. In particular, the control unit 160 causes the SLC block unit 112 to program data input in accordance with a program command, and then all of the SLC block units 112 of the nonvolatile memory device 100 are in a program state or operate. If it is not in the idle state or receives a power-off command, the data stored in the SLC block unit 112 is loaded in units of blocks and transferred to the MLC block unit 111 to be programmed.

In particular, when programming the MLC block unit 111, the control unit 160 selects one of the first to Nth MLC blocks to program the data of the entire block, and once again increases the verification voltage with the same data. do. A detailed description thereof will be described later with reference to FIG. 3.

Since data of two SLC blocks of the first to Kth SLC blocks may be stored in one MLC memory block, the controller 160 may program the MLC block until all the data of at least two SLC blocks are programmed. I never do that.

Since the program speed of the SLC block is faster than that of the MLC block, the nonvolatile memory device may increase the program speed. In addition, the reliability of the data can be improved by applying the method of programming the same data twice as the method of programming the MLC block.

As another embodiment, the SLC block and the MLC block may not be separately designated, but a separate buffer may be provided to temporarily store data that can be programmed in one block.

2 illustrates a nonvolatile memory device according to another embodiment.

Referring to FIG. 2, the nonvolatile memory device 200 has a configuration similar to that of the nonvolatile memory device 100 of FIG. 1. That is, the memory cell array 210, the page buffer unit 220, the Y decoder 230, the X decoder 240, the voltage provider 250, and the controller 260 are included. And a buffer 260.

The memory cell array 210 includes first to Nth MLC blocks, and each memory block includes memory cells capable of storing two bits of data.

The memory cells are connected to word lines WL and bit lines BL.

The page buffer unit 220, the Y decoder 230, the X decoder 240, and the voltage provider 250 may include the page buffer unit 120, the Y decoder 130, the X decoder 140, and the voltage regulator of FIG. 1. The same function as the study (150).

The controller 260 also outputs a control signal for a program, data read or erase operation, and performs two programs using the same data when programming data to the first to Nth MLC blocks, and one block. The data to be programmed are temporarily stored in the buffer unit 270 until data that can be programmed in its entirety is input.

Therefore, the buffer unit 270 should have a capacity that is larger than all the data that can be stored in one MLC block. The buffer unit 270 may be configured as a storage device such that a DRAM has a faster program speed than an MLC block.

When the data stored in the buffer unit 270 is enough to be programmed in one MLC block, the controller 260 starts the program of the MLC block.

1 and 2 can compensate for the drawback that the program speed of the MLC is significantly slower than that of the SLC. In addition, by performing the MLC program as in the exemplary embodiment of the present invention, an error of data due to an interference between neighboring cells can be reduced.

3 is a flowchart illustrating a program method of a nonvolatile memory device according to an exemplary embodiment of the present invention.

Before the program operation as shown in FIG. 3 is performed, as much as the amount of data capable of programming the entire MLC block must be stored in the SLC block or the buffer unit 270 as described above with reference to FIGS. 1 and 2.

In addition, the program of the MLC block may be executed when there is no buffer unit 270 or an SLC block capable of storing data anymore. However, most of the nonvolatile memory devices 100 and 200 are waiting or the power off command is executed. This is done before ending the operation.

FIG. 3 is representative of a program operation in the nonvolatile memory device 100 as shown in FIG. 1.

Referring to FIG. 3, when the control unit 160 of the nonvolatile memory device 100 is in a standby state (S301) or a power off command is input (S303), a program of an MLC block is started (S305).

The program command of the MLC block is a command generated inside the controller 160, and is generated only when there is enough data to program in one entire MLC block. That is, since only one SLC block is programmed in the entire MLC block, the MLC program command may be generated in at least two SLC blocks.

In the embodiment of the present invention, it is assumed that data stored in the first and second SLC blocks are programmed into the first MLC block.

When the program is started, the controller 160 first reads data from the first SLC block so that the controller 160 can store the data in the page buffer unit 120. In more detail, two bits of data may be stored in the page buffer unit 120 by sequentially reading the data of the first and second word lines of the first SLC block.

This is possible by storing the data read from the first word line and the data read from the second word line in each latch since the page buffers each have two or more latches in the page buffer unit 120.

The controller 160 selects a first MLC block and selects a first word line (S309) to perform an operation control to program and verify (S311).

When the program is completed, it is checked whether the program for all the word lines of the first MLC block has been made (S313), and if the program for all the word lines has not yet been completed, the next word line is selected to execute the program (S307 to S315). Hereinafter, the operations of steps S307 to S315 will be referred to as a first program execution process.

Since the data stored in the two word lines of the SLC block are programmed for the word lines of each MLC block, the data of the two SLC blocks is required.

On the other hand, when the program for all word lines is completed, the level of the verification voltage required in the MLC program process is changed (S317).

The change in the verification voltage will be described with reference to FIGS. 4A and 4B below.

4A and 4B show the shift of the threshold voltage distribution of the memory cell by the program operation of the MLC block.

FIG. 4A illustrates a shift in threshold voltage distribution of memory cells during steps S307 to S315 in FIG. 3. That is, the threshold voltage of the memory cell when the MLC program is first completed is equal to 'A'.

However, while the program is in progress for another word line, the threshold voltage distribution continues as 'B' to 'C' due to interference (I) from surrounding memory cells and back pattern (B) of program data. Change in the worst case, the threshold voltage overlaps, and the reliability of the data is deteriorated.

In the program state of FIG. 4A, the controller 160 performs a second program operation of reloading and programming the same data. At this time, considering that there is an overlap part between threshold voltage distributions as shown in 'C' of FIG. 4A and that the program operation only increases the threshold voltage of the memory cell, the verification voltage is higher than the initial program operation. Set it.

Although there is already an overlap between the threshold voltage distribution, the controller 160 can know the data to be reprogrammed through the SLC block, so that the programming of only the verification voltage does not reduce the reliability of the data.

As shown in FIG. 4B, the memory cells affected by the interference between the neighboring cells and the back pattern phenomenon are much less affected by the second program.

That is, as shown in FIG. 4B, when the second program is executed, the threshold voltage distribution is formed as shown in 'D', and the threshold voltage distribution is slightly widened as shown in 'E' even though it is affected during the program of other memory cells. It is possible to prevent overlapping between the threshold voltage distributions, which are late but worst. This is because the characteristics of the memory cell have already been affected by interference and back pattern, and the second is much more affected.

Referring to FIG. 3 again, after changing the verification voltage by increasing the predetermined level, the process of loading data of the first and second SLC blocks, selecting and programming word lines is repeated (S319 to S327). Hereinafter, operations of steps S319 to S327 will be referred to as a second program execution process. When all programs are finished, the first and second SLC blocks are erased so that other data can be stored.

The first program execution process and the second program execution process only change the verify voltage level, and operate the same data in the same MLC block. To further increase the reliability of the data, it is also possible to perform a third program after raising the verification voltage level slightly.

By performing the program operation as described above, the data stored in the SLC block or the buffer portion is increased by increasing the speed of the program data input from the outside, and internally, the same data is programmed when the data is programmed in the MLC block. Data reliability can be ensured by performing the program more than once.

In addition, in the case of the nonvolatile memory device 200 in which the buffer unit 270 is separately provided as shown in FIG. 2, when the data enough to be programmed in the entire MLC block is stored in the buffer unit 270, the MLC block program is immediately executed. You can also proceed. If the capacity of the buffer unit 270 is equal to one MLC block, the MLC block program is performed when data is no longer stored in the buffer unit 270. The buffer unit 270 is deleted to store the next program data.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention can be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 illustrates a nonvolatile memory device according to an embodiment of the present invention.

2 illustrates a nonvolatile memory device according to another embodiment.

3 is a flowchart illustrating a program method of a nonvolatile memory device according to an exemplary embodiment of the present invention.

4A and 4B show the shift of the threshold voltage distribution of the memory cell by the program operation of the MLC block.

Claims (10)

Providing a nonvolatile memory device including multilevel cell blocks including memory cells capable of storing two or more bits of data; Programming data input according to a program command to some of the multi-level cell blocks in a single level cell program method; A first program execution step of generating a multi-level cell program command to program the stored data to the entire selected multi-level cell block when the stored data reaches the capacity to be programmed in the entire multi-level cell block; And A second program execution step of setting a second verification voltage higher than the first verification voltage level used in the first program execution step and programming the stored data over the selected multi-level cell block. Program method of a nonvolatile memory device comprising a. The method of claim 1, The single level cell program method, And programming one bit information into memory cells of the multi-level cell block. The method of claim 1, The multi-level cell program command,  Characterized in that the data stored in the data storage step becomes large enough to be programmed in the entire multi-level cell block, and is generated when the nonvolatile memory device does not perform any operation or when a power-off command is input. Program method of a nonvolatile memory device. The method of claim 1, And a third program performing step of setting a third verification voltage higher than a second verification voltage level used in the second program performing step, and overlapping the stored data in the entire selected multi-level cell block. Program method of volatile memory device. The method of claim 4, wherein When the program of the multi-level cell block is finished, And erasing the stored data. Providing a nonvolatile memory device including multi-level cell blocks including memory cells capable of storing two or more bits of data, and a buffer unit capable of temporarily storing data to be programmed; Temporarily storing data input according to a program command in the buffer unit; Performing a first program of generating a multi-level cell program command to program the stored data to the entire selected multi-level cell block when the data stored in the buffer unit has a capacity to be programmed in the entire multi-level cell block; And A second program execution step of setting a second verification voltage higher than the first verification voltage level used in the first program execution step and programming the stored data over the selected multi-level cell block. Program method of a nonvolatile memory device comprising a. The method of claim 6, The buffer unit, And a separate storage means having a higher data storage speed than a speed of programming data in the multi-level cell block. The method of claim 6, The multi-level cell program command, The data stored in the buffer unit has a capacity that can be programmed in the entire multi-level cell block, and is generated when the nonvolatile memory device is in a standby state in which no operation is performed or when a power-off command is input. Program method of volatile memory device. The method of claim 6, And a third program performing step of setting a third verification voltage higher than a second verification voltage level used in the second program performing step, and overlapping the stored data in the entire selected multi-level cell block. Program method of volatile memory device. The method of claim 9, When the program of the multi-level cell block is finished, And deleting data stored in the selected multi-level cell block among the stored data.

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