KR20100136061A - Memory device and method of manufacturing the same - Google Patents

Abstract

PURPOSE: Since the active area of device is controlled with the thickness since the memory device and manufacturing method thereof manufacture the traverse direction resistance alteration memory device, the integrated limit formed with the lithography is over. CONSTITUTION: The information storage unit(30) is formed on the insulating layer. The information storage unit records data with the resistance alteration according to the applied voltage or it eliminates. In the first electrode(43) is the top of the information storage unit, it is formed so that width over the time change into the lower part.

Description

MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

The present invention relates to a memory device, and more particularly, to a resistance change memory device in which the operating voltage of the resistance change layer is changed by adjusting the contact area between the resistance change layer and the electrode, the length of the resistance change layer between the electrodes, and the like.

Recently, memory technology has reached physical and technical limitations in patterning for integration of devices, and due to various problems caused by scaling down of conventional NAND flash memory devices, resistive random access memory (RERAM) There is an active research on.

The resistance change memory device (ReRAM) stores data bits in a memory cell by using a resistance change such as a metal oxide generated by applying a short electric pulse.

The resistance change memory device has a resistance of about 10 to 1,000 times due to the filament type, the oxidation / reduction reaction at the interface, and the schottky barrier change.

The resistance change memory device can operate at a high speed of about 10 to 100 nsec, can be driven at a low voltage, and can repeatedly write and erase data 10 to ¹⁰ times.

On the other hand, the resistance change memory device currently developed acts as an active device even in a very small area (<5 × 5nm ² ) where filaments are formed among the two electrodes where they meet, but due to the limitations of current lithography, the vertical structure In devices of less than 20nm it is difficult to integrate.

The present invention provides a resistance change memory device in which an insulating film and a resistance change element are sequentially stacked between two electrodes in the transverse direction so as to overcome the above limitations of integration and enable multi-bit data storage. The purpose is.

Another object of the present invention is to provide a method of manufacturing a resistance change memory device in which an insulating film and a resistance change element are sequentially stacked between two electrodes in a lateral direction.

Memory device according to an embodiment of the present invention for achieving the above object is formed on the insulating layer, the insulating layer and the insulating layer from the top of the information storage unit, the information storage unit for recording or erasing data by the resistance change according to the applied voltage It includes a first electrode and a second electrode formed in a shape that changes in width toward the top of the lower.

In accordance with another aspect of the present invention, there is provided a method of manufacturing a memory device, the method including: providing an insulating layer, forming an information storage unit on the insulating layer, forming a contact hole and forming an electrode in the formed information storage unit; And planarizing the formed information storage unit and the electrode.

Specific details of other embodiments are included in the detailed description and the drawings.

According to the memory device of the present invention as described above has the following advantages.

First, by fabricating a transverse resistance change memory device, the active area of the device can be controlled by thickness, thus exceeding the integration limit formed by lithography.

Second, multi-bit data can be stored by forming a resistance change layer in multiple layers between the metal electrodes in the lateral direction.

Third, the operation voltage / current and the ON / OFF resistance ratio can be changed by varying the length of the resistance change layer between metal electrodes by changing the width in the vertical direction of the metal electrode in the transverse direction.

The effects of the present invention are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various different forms, and the present embodiments merely make the disclosure of the present invention complete, and are common in the art to which the present invention pertains. It is provided to fully inform those skilled in the art of the scope of the invention, which is to be defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, a memory device and a method of manufacturing the same according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail to avoid unnecessarily obscuring the subject matter of the present invention.

1 is a cross-sectional view illustrating a stacked structure of a memory device 100 according to an embodiment of the present invention.

As shown in FIG. 1, the memory device 100 according to an exemplary embodiment of the present invention is formed on the insulating layer 10 and the insulating layer 10 and writes or erases data by a resistance change according to an applied voltage. The first and second electrodes 43 and 45 are formed to vary in width from the upper portion of the information storage portion 30 and the upper portion of the insulating layer 10 to the upper portion of the insulating layer 10.

The insulating layer 10 is a layer in which the memory device 100 according to the present invention is electrically insulated from a circuit, and is formed by chemical vapor deposition using silicon dioxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ). To form).

However, the material of the insulating layer 10 is not limited to the above, and any material can be used as long as it can achieve electrical insulation.

The information storage unit 30 is formed on the insulating layer 10 and writes or erases data by a resistance change according to an applied voltage.

The information storage unit 30 has a multilayer structure in which at least one interlayer insulating film 33 and the resistance change layer 35 are sequentially stacked.

The interlayer insulating layer 33 is formed to electrically insulate the resistance change layer 35 formed in the information storage unit 30, and is formed by chemical vapor deposition using silicon dioxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ). vapor deposition).

The resistance change layer 35 is a layer that exhibits a property of varying resistance according to an applied voltage, and forms a material exhibiting NDR (Negative Differential Resistance) behavior, which is a phenomenon in which a current decreases rapidly with voltage, by electro-forming.

When the resistance change layer 35 is applied with a voltage higher than or equal to the _set voltage V _set , the resistance of the resistance change layer 35 decreases (ON state), and when the voltage greater than or equal to the reset voltage V _reset is applied, the resistance change layer 35 ) Resistance increases (OFF state).

The resistance change layer 35 is connected in parallel with the first and second electrodes 43 and 45 of the memory device 100 to be different from each other in the plurality of resistance change layers 35 by input pulses applied from the electrodes. It will show driving characteristics.

In addition, an area in contact with the first and second electrodes 43 and 45 may change from the upper portion to the lower portion of the resistance change layer 35 formed in the information storage unit 30. This is caused by the first electrode 43 and the second electrode 45 having a tapered shape, and the thicknesses of the resistance change layer forming the information storage portion differ from each other at the top and the bottom.

In this case, the tapered angle of the electrode may have a range between 91 and 135 ° between short sides and hypotenuses (sides connecting parallel sides) of the parallel sides in the electrode having a trapezoidal cross section shown in FIG. 1. .

In addition, since the first and second electrodes 43 and 45 are formed while the width thereof is changed below the information storage unit 30, the plurality of resistance change layers 35 are formed between the first and second electrodes 43 and 45, respectively. As the length is changed, the resistance characteristic is changed as a result. That is, although the thicknesses of the resistance change layer 35 are the same at the top and the bottom, the actual resistance of the resistance change layer 35 disposed between the two electrodes is set differently by the tapered shape of the electrodes. This is due to the change in the length of the resistance change layer 35 disposed between the two electrodes.

In addition, the plurality of resistance change layers 35 formed may be stacked to have different thicknesses, whereby the resistance characteristics of the resistance change layer 35 may be changed.

The material used for the resistance change layer 35 is a material that exhibits resistance change characteristics according to an electrical signal. The two-component oxides Nb ₂ O ₅ , TiO ₂ , NiO, Al ₂ O ₃ , and Pr _{1 -x} doped with metal Ca _x MnO _3, Kell Koji arsenide may be at least one selected from (chalcogenide) substance of GeSeTe and metal doped Fe lobe Scar the teugye oxide (SrTiO _3, SrZrO ₃ or the like Cr or Nb-doped material).

The memory device 100 of the present invention is electrically connected to a switching device (not shown) in which any one of the first and second electrodes 43 and 45 is provided for controlling information stored in the resistance change layer 35. do. In this case, the switching element may be a transistor or a diode. Therefore, in FIG. 1, although the two electrodes 40 and 50 are disposed at the same position on the insulating layer 10, when the switching element is formed under the insulating layer 10, at least one electrode The insulating layer 10 may be electrically connected to one electrode of the switching device.

Method of manufacturing a memory device 100 according to a preferred embodiment of the present invention comprises the steps of providing an insulating layer 10, forming an information storage unit 30 on the insulating layer 10, formed information storage unit ( Forming a contact hole in 30 and forming an electrode, and planarizing the formed information storage unit 30 and the electrode.

In addition, the step of forming the information storage unit 30 includes sequentially stacking at least one interlayer insulating film 33 and the resistance change layer 35 to form a multi-layer structure.

2 to 4 are cross-sectional views illustrating a method of manufacturing the memory device shown in FIG. 1 according to a preferred embodiment of the present invention.

Referring to FIG. 2, first, an insulating layer 10 is formed on a substrate 5. The substrate 5 having the insulating layer 10 may further include a switching element (not shown) under the insulating layer 5.

Referring to FIG. 3, the information storage unit 30 is formed on the insulating layer 10 of the substrate 5. The information storage unit 30 is achieved by sequentially stacking the interlayer insulating film 33 and the resistance change layer 35 on the insulating layer 10 and repeating the same.

The interlayer insulating film 33 forms silicon dioxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ) on the insulating layer 10 in a thin film form by chemical vapor deposition.

The resistance change layer 35 is formed by chemical vapor deposition on the formed interlayer insulating film 33, and a plurality of thicknesses of the resistance change layer 35 formed may be deposited differently.

Referring to FIG. 4, the interlayer insulating film 33 and the resistance change layer 35 are sequentially formed, and then contact holes are formed from the top of the resistance change layer 35 to the top of the insulating layer 10 by lithography and etching. Form.

In this case, a lithography and etching process is performed so that the size of the contact hole increases or decreases from the top to the bottom of the information storage unit 30. That is, the contact hole is provided so that the width of the upper and lower portions are different from each other.

When the contact hole is formed, the conductor 40 is embedded in the contact hole to form an electrode. The conductor 40 embedded in the contact hole to form the electrode is preferably a conductive metal material. By filling the conductor 40, the contact hole is filled with the conductor 40, and the conductor 40 is also formed on the information storage unit 30 other than the contact hole.

1 and 4, after filling the conductor 40, the conductor 40 on the information storage unit 30 is removed by a chemical mechanical planarization (CMP) process. Only the electrodes 43 and 45, which are the conductors 40 embedded in the contact holes, remain.

5 and 6 are graphs illustrating the results of calculating the current-voltage change and the total resistance value on the premise that the resistance change layer of the memory device is composed of three layers (layer 1, layer 2, and layer 3).

In this case, it is assumed that the resistances of layers 1, 2, and 3 change to 8 MΩ / 1 MΩ, 16 MΩ / 2 MΩ, and 32 MΩ / 4 MΩ, respectively.

FIG. 5 is a current-voltage graph of a resistance change memory device having three resistance change layers, and each resistance change layer has a different V _set / V _reset and accordingly, different ON / OFF resistances.

FIG. 6 is a diagram illustrating resistances between metal electrodes when the resistances of the three resistance change layers are changed.

In this case, when the resistance change layers are connected in parallel, the total resistance is expressed by the following equation.

Where R is the total resistance, r1 is the resistance of layer 1, r2 is the resistance of layer 2, and r3 is the resistance of layer 3.

As shown in FIG. 6, it can be seen that a multi-bit memory device may be implemented using a resistance change memory device including three resistance change layers.

The memory device according to the present invention is a resistance change memory device using a material causing resistance change by an applied voltage, and may store one or more data bits per memory device.

In addition, the resistance change memory device according to the present invention has a transverse electrode structure and the width of the electrode can be changed in the vertical direction to change the resistance characteristics of the resistance change layer in a variety of ways can change the characteristics of the memory device in various ways have.

Due to the above effects, the resistance change memory device according to the present invention is considered to have a high industrial applicability in the future next-generation memory market.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that.

It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. .

1 is a cross-sectional view of a memory device according to an exemplary embodiment of the present invention.

2 to 4 are cross-sectional views illustrating a method of manufacturing a memory device according to an exemplary embodiment of the present invention.

FIG. 5 is a diagram illustrating operating characteristics of a device when a memory device is implemented using three resistance change layers.

FIG. 6 is a diagram illustrating resistance values between metal electrodes when the resistance change layers of three layers of the memory device shown in FIG. 5 are different.

<Description of Symbols for Main Parts of Drawings>

5: substrate 10: insulating layer

30: information storage unit 33: interlayer insulating film

35: resistance change layer 40: conductor

43: first electrode 45: second electrode

100: memory device

Claims (10)

Insulating layer; An information storage unit formed on the insulating layer and configured to record or erase data by a resistance change according to an applied voltage; A first electrode formed to vary in width from an upper portion to an lower portion of the information storage unit; And And a second electrode formed to face the first electrode with respect to the information storage part and to change in width from an upper portion to a lower portion of the information storage portion. The method of claim 1, wherein the information storage unit, And a multilayer structure in which at least one interlayer insulating film and a resistance change layer are sequentially stacked. The method of claim 2, wherein the resistance change layer, And a memory device connected in parallel with the first and second electrodes. The method of claim 2, wherein the resistance change layer, The contact area with the first and second electrodes is changed from the stacked top to the bottom. The method of claim 2, wherein the resistance change layer, And a distance between the first and second electrodes is different from each other. The method of claim 2, wherein the resistance change layer, A memory device, characterized in that each having a different thickness. The method of claim 2, wherein the resistance change layer, At least one selected from Nb ₂ O ₅ , TiO ₂ , NiO, Al ₂ O ₃ , Pr _{1 - x} Ca _x MnO ₃ , GeSeTe, AgGeSe, and metal-doped perovskite oxides. Providing an insulating layer; Forming an information storage unit on the insulating layer; And And forming an electrode having a tapered shape in the formed information storage unit. The method of claim 8, wherein the forming of the information storage unit comprises: And sequentially stacking at least one interlayer insulating film and a resistance change layer to form a multilayer structure. The method of claim 9, wherein the information storage unit includes a plurality of resistance change layers, and each resistance change layer has a different thickness.

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