KR20100100397A - Nonvolatile memory device - Google Patents

Abstract

PURPOSE: A nonvolatile memory device is provided to laminate more active patterns on the substrate by electrically connecting the active patterns by a first pad unit. CONSTITUTION: The gate patterns and the insulation patterns oxides are alternately laminated on a substrate(110). An activity pattern(ACT) is expanded according to the sidewalls of the gate patterns and insulation patterns. Data store patterns(133, 134) are formed between the gate patterns and the active patterns.

Description

Nonvolatile Memory Device {NONVOLATILE MEMORY DEVICE}

The present invention relates to a memory device, and more particularly to a nonvolatile memory device.

With the miniaturization / multifunctionalization trend of electronic devices, semiconductor devices embedded therein also need to be more integrated. However, in order to achieve high integration of the semiconductor device, not only the components of the micronized device are formed, but also the characteristics of each component must be maintained. Expensive equipment is required to form finer components. However, even with expensive equipment, there is a limit to miniaturization of components, and as an alternative, studies for high integration of semiconductor devices continue.

One technical problem to be solved by the present invention is to provide a nonvolatile memory device optimized for high integration.

Another technical problem to be solved by the present invention is to provide a nonvolatile memory device having improved reliability.

A nonvolatile memory device for solving the above technical problems is provided. The nonvolatile memory device includes gate patterns and insulating patterns alternately stacked on a substrate, an active pattern extending upward along sidewalls of the gate patterns and the insulating patterns on the substrate, and the gate patterns and the insulating patterns. Include data storage patterns between patterns. The active pattern includes a first sub-active pattern, a second sub-active pattern on the first resilient pattern, and the first and second resilient patterns. It may include a first pad unit for connecting. The cross-sectional area of the upper surface of the first pad part may be wider than the cross-sectional area of the upper surface of the first resilient pattern.

In an embodiment, the active pattern may be disposed in an opening passing through the gate patterns and the insulating patterns. The first resilient pattern may be disposed along a sidewall of the opening to define an inner space surrounded by the first resilient pattern. The inner space may be filled by the filling insulating layer, and the first pad part may be disposed on the filling insulating layer.

In an embodiment, the upper surface of the first pad part may be coplanar with the upper surface of the first resilient pattern.

In an embodiment, the lower surface of the second resilient pattern may contact the upper surface of the first pad part. The lower sidewall of the second resilient pattern may be laterally moved from the side wall of the first resilient pattern toward the center of the first pad part.

The data storage pattern may include a first storage unit between the first resilience pattern and the gate patterns next to the first resilience pattern, and the side of the second and second resilience patterns. It may include a second storage unit between the gate patterns. The first storage unit and the second storage unit may be separated from each other.

In an embodiment, the alternately stacked gate patterns and insulating patterns may constitute one gate group. The pair of gate groups may be spaced apart from each other on the substrate, and a groove may be defined between the pair of gate groups. A pair of the first resilient patterns spaced apart from each other may be disposed on both sidewalls of the groove. A charge insulating layer may be further disposed between the pair of first activating patterns. The first pad part may be disposed on the filling insulating layer.

In example embodiments, the first resilient pattern, the second resilient pattern, and the first pad part may include the same semiconductor material.

In example embodiments, the nonvolatile memory device may further include a first pad part on the second resiliency pattern and a bit line electrically connected to the first pad part. An area of an upper surface of the first pad part may be larger than an area of an upper surface of the second active pattern.

In an embodiment, the ohmic layer between the first pad part and the bit line may be further interposed.

In example embodiments, the data storage pattern may include a tunnel barrier adjacent to the active pattern, a blocking barrier adjacent to the gate pattern, and a charge storage layer between the tunnel barrier and the blocking barrier.

According to embodiments of the present invention, a plurality of activating patterns are stacked on a substrate. The resilient patterns may be electrically connected by the first pad part. Accordingly, more activating patterns can be stacked on the substrate. Thus, a nonvolatile memory device optimized for high integration is provided.

Hereinafter, a nonvolatile memory device according to embodiments of the present invention will be described with reference to the accompanying drawings. The described embodiments are provided so that those skilled in the art can easily understand the spirit of the present invention, and the present invention is not limited thereto. Embodiments of the invention may be modified in other forms within the spirit and scope of the invention. In this specification, 'and / or' is used to include at least one of the components listed before and after. In this specification, the fact that one component is 'on' another component means that another component is directly positioned on one component, and that a third component may be further positioned on the one component. It also includes meaning. Each component or part of the present specification is referred to using the first, second, and the like, but the present disclosure is not limited thereto. In the present specification, each component or part is referred to using the expressions of the upper and lower, but this is a relative positional relationship used for clarity, and thus the positional relationship of each component or part is not limited. The thickness and relative thickness of the components represented in the drawings may be exaggerated to clearly express embodiments of the present invention.

1, 2A and 2B, a nonvolatile memory device according to an embodiment of the present invention is described. 1 is a plan view of a nonvolatile memory device according to an embodiment of the present invention. FIG. 2A is a cross-sectional view taken along the line II ′ of FIG. 1, and FIG. 2B is a cross-sectional view taken along the line II-II ′ of FIG. 1.

1, 2A, and 2B, a substrate 110 including a well region is prepared. The substrate 110 may be a semiconductor-based semiconductor substrate. The well region may be a region doped with a dopant in the substrate 110. The well region may be doped with, for example, a dopant of a first conductivity type. The common source region 112 may be disposed in the well region. The common source region 112 may be a region doped with a dopant of a second conductivity type. The well region and the common source region 112 may be disposed throughout the cell region of the substrate 110.

A base insulating pattern 122 is disposed on the substrate 110. Gate patterns LSG, CG1, CG2, and USG and inter-gate insulating patterns 122, 124a, 124b, and 126 are stacked on the base insulating pattern 122. The gate patterns LSG, CG1, CG2, and USG may be formed of lower first gate patterns LSG and CG1 and upper second gate patterns CG2 and USG.

The gate pattern LSG disposed at the lowermost of the gate patterns LSG, CG1, CG2, and USG may be a lower select gate pattern LSG. The lower selection gate pattern LSG may be disposed in a flat shape on the entire area of the cell area of the substrate 110.

Cell gate patterns CG1 and CG2 may be disposed on the lowermost inter-gate insulating pattern 124. The cell gate patterns CG1 and CG2 may be formed of first cell gate patterns CG1 adjacent to the lower gate pattern LSG and second cell gate patterns CG2 adjacent to the upper gate pattern USG. Can be configured. The cell gate patterns CG1 and CG2 may have a flat plate shape parallel to the lower selection gate pattern LSG.

The gate pattern USG disposed at the top of the gate patterns LSG, CG1, CG2, and USG may be an upper selection gate pattern USG. The upper selection gate pattern USG may be disposed on a portion of the second cell gate pattern CG2. For example, the upper selection gate pattern USG may have a line shape extending in a first direction. As illustrated in FIG. 1, a plurality of upper selection gate patterns USG may be disposed on a cell region of the substrate 110. The upper selection gate patterns USG may extend in parallel along the first direction on the uppermost gate insulating pattern 124.

Inter-gate insulating patterns 124a and 124b may be interposed between the gate patterns LSG, CG1, CG2 and USG. A first inter-gate insulating pattern 124a may be interposed between the first cell gate patterns CG1, and a second inter-gate insulating pattern 124b may be interposed between the second cell gate patterns CG2. have. The lowermost first inter-gate insulating pattern 124a may be interposed between the lowermost first cell gate pattern CG1 and the lower selection gate pattern LSG. The first inter-gate insulating pattern 124a and the second inter-gate insulating pattern 124b may be interposed between the uppermost first cell gate pattern CG1 and the lowermost second cell gate pattern CG2. Can be. The uppermost second inter-gate insulating pattern 124b may be interposed between the uppermost second cell gate pattern CG2 and the upper selection gate pattern LSG.

An upper insulating pattern 126 may be disposed on the upper selection gate pattern USG. The upper insulating pattern 126 may extend to cover sidewalls in a length direction of the upper selection gate pattern USG.

The opening 130 penetrating the gate patterns LSG, CG1, CG2, and USG is disposed on the substrate 110. The opening 130 is defined by the sidewalls defined by the sidewalls of the gate patterns LSG, CG1, CG2, and USG and the insulating patterns 122, 124a, 124b, and 126 and the substrate 110. It may include a bottom. The opening 130 may be a hole type.

The opening 130 may include a first hole 131 penetrating the lower selection gate pattern LSG and the first cell gate patterns CG1, and a second cell gate pattern CG2 and the upper selection gate pattern USG. ) May be a space in which the second hole 132 penetrates vertically. The surface extending from the sidewall of the first hole 131 and the surface extending from the sidewall of the second hole 132 may be parallel to each other but may not coincide with each other. That is, the side wall of the first hole 131 and the side wall of the second hole 131 may not be located on the same surface. In an embodiment, the first hole 131 may have the narrowest width in the area adjacent to the substrate 110 and the widest width in the area adjacent to the second hole 132. That is, the first hole 131 may have an inclined sidewall. The second hole 132 may have the narrowest width in the area adjacent to the first hole 131 and have the widest width in the area adjacent to the upper insulating pattern 126.

An active pattern ACT may be disposed on sidewalls of the opening 130. The active pattern ACT extends upward from the substrate 110 along sidewalls of the gate patterns LSG, CG1, CG2, and USG and the insulating patterns 122, 124a, 124b, and 126.

The active pattern ACT may include a first sub-active pattern 142, a second sub-active pattern 148 on the first reactivity pattern 142, and the first sub-active pattern 142. The first pad part 146 connects the resiliency pattern 142 and the second resiliency pattern 148.

The first resilience pattern 142 may be disposed on sidewalls of the first hole 131 of the opening 130. The first resilient pattern 142 may have an inner space defined by sidewalls of the first resilient pattern 142. For example, the first resilience pattern 142 may be in the form of a shell. The first activation pattern 142 may include a bottom portion in contact with the substrate 110. In contrast, the first resilient pattern 142 may not include a bottom portion. The first resilient pattern 142 may have sidewalls that are inclined from the normal of the upper surface of the substrate 110. In one embodiment, the first resiliency pattern 142 may be a truncated corn shape or a frustum of pyramid shape. The width of the lower portion of the first resilient pattern 142 having a truncated cone shape or a truncated cone shape may be narrower than the width of the upper portion. An upper surface of the first resilient pattern 142 may be a closed loop type. For example, an upper surface of the first resilient pattern 142 may be annular.

The first activation pattern 142 may include a semiconductor material. For example, the first activating pattern 142 may include a single crystal semiconductor material or a polycrystalline semiconductor material.

In one embodiment, the inner space may be filled with a first filling insulating layer 152. The first charge insulating layer 152 may be surrounded by sidewalls of the first active pattern 142. An upper surface of the first charge insulating layer 152 may be lower than an upper surface of the first inter-gate insulating pattern 124b.

The first pad part 146 may be disposed on the first charge insulating layer 152. An upper surface of the first pad part 146 may be coplanar with an upper surface of the first resilient pattern 142. Alternatively, the first pad part 146 may be disposed on an upper surface of the first resilient pattern 142. The cross-sectional area of the upper surface of the first pad part 146 may be wider than the cross-sectional area of the upper surface of the first resilient pattern 142. In an embodiment, an inner space of the first resilience pattern 142 may be closed.

The first pad part 146 may include the same semiconductor material as the first resilient pattern 142. Thus, the first resilience pattern 142 may be electrically connected to the first pad part 146. The area where the first resilient pattern 142 may be in electrical contact with another element of the memory device may be increased by the first pad part 146.

The second resilient pattern 148 may be disposed on sidewalls of the second hole 132 of the opening 130. The second resilient pattern 148 may have a sidewall inclined from a normal of an upper surface of the substrate 110. The circumference of the second resilient pattern 148 is farther away from the substrate 110. Can be large. In one embodiment, the second resiliency pattern 148 may be truncated or pyramidal. The width of the lower portion of the conical or pyramidal second resilient pattern 148 may be narrower than the width of the upper portion.

The second resiliency pattern 148 may have an inner space. When the second resiliency pattern 148 has an internal space, the second resiliency pattern 148 may have a shape similar to that of the first resiliency pattern 142. In contrast, the second resilience pattern 148 may have a shape of filling the second hole 132 without having an internal space. As shown, the second resiliency pattern 148 may include a bottom portion. In contrast, the second resilient pattern 148 may not include a bottom portion.

The second resilient pattern 148 may include a semiconductor material. The second resilient pattern 148 may include a single crystal semiconductor material or a polycrystalline semiconductor material. The second resilient pattern 148 may be formed of the same material as the first resilient pattern 142 and the first pad part 146.

The second resiliency pattern 148 may be electrically connected to the first resiliency pattern 142 by the first pad part 146. The outer wall of the second resilient pattern 148 adjacent to the first pad part 146 is formed from the outer wall of the first resilient pattern 142 adjacent to the first pad part 146. The pad may be moved laterally toward the center of the pad 146. An outer wall of the first resilience pattern 142 means a sidewall adjacent to the first storage unit 133 of the data storage pattern. In an embodiment, the bottom surface of the second resilient pattern 148 may be narrower than the top surface of the first pad part 146. Therefore, a portion of the upper surface of the first pad part 146 may not contact the second resiliency pattern 148. A portion of the upper surface of the first pad portion 146 that is not in contact with the second resilience pattern 148 may be an edge of the upper surface of the first pad portion 146.

In one embodiment, a portion of the second resiliency pattern 148 may directly contact the first resiliency pattern 142. That is, a portion of the second resilient pattern 148 is electrically connected to the first resilient pattern 142 through the first pad part 146, and the second resilient pattern 148 may be electrically connected to the first resilient pattern 148. The other part may be directly connected to the first resiliency pattern 142.

By the first pad part 146, the second resiliency pattern 148 and the first resiliency pattern 142 may be more stably contacted. As described above, the second resiliency pattern 148 may be electrically connected to the first resiliency pattern 142 through a direct path or an indirect path through the first pad part. In one embodiment, the first resilience pattern 142 may be formed in a shell shape having an internal space. When the first resilient pattern 142 is formed in a shell shape, the first resilient pattern 142 may have a narrow upper surface. The first pad part 146 is disposed above the internal space defined by the first resilience pattern 142 to electrically connect the first resilience pattern 142 with the second resilience pattern 148. Connect. As a result, the first resilience pattern 142 and the second resilience pattern 148 may be electrically connected more stably. Accordingly, a nonvolatile memory device having improved reliability may be provided.

When the sidewall of the second resilient pattern 148 defines an inner space, the inner space defined by the sidewall of the second resilient pattern 148 may be filled by the second filling insulating layer 154. The second charge insulating layer 154 may be positioned lower than an upper surface of the uppermost second gate-to-gate insulating pattern 126. The second pad part 150 may be further disposed on the second charge insulating layer 154.

The second pad part 150 may include the same semiconductor material as the second resilient pattern 148. Accordingly, other components of the memory device may be in contact with the second pad part 150 to be electrically connected to the second resilience pattern 148. For example, the bit line to be described later may be electrically connected to the second resiliency pattern 148 by contacting the second pad part 150 and / or the second resiliency pattern 148. Accordingly, the bit line may be electrically connected to the second resiliency pattern 148 more easily.

Although an embodiment including two resiliency patterns and a pad portion connecting the resilience patterns has been described above, embodiments of the present invention include two or more resilience patterns and a first pad portion between the resilience patterns. It includes a nonvolatile memory device including. In detail, a third resilience pattern, third gate patterns, and components connected thereto may be further disposed on the second resilience pattern and the second gate patterns. In this case, the gate pattern of the uppermost of the second gate patterns may be a cell gate pattern, as described above. That is, the nonvolatile memory device according to the embodiment of the present invention includes at least two activating patterns and a pad unit connecting the activating patterns.

Data storage patterns 133 and 134 are interposed between the active pattern ACT and the gate patterns LSG, CG and USG. The data storage patterns 133 and 134 may be disposed on sidewalls of the opening 130. The data storage patterns 133 and 134 may include a plurality of layers. The data storage patterns 133 and 134 may include a blocking barrier adjacent to the gate patterns LSG, CG, and USG, a tunnel barrier adjacent to the active pattern ACT, and a charge storage layer between the blocking barrier and the tunnel barrier. It may include. In one embodiment, the data storage patterns 133 and 134 may include an ONO layer.

 The data storage patterns 133 and 134 may include a first storage unit 133 disposed on sidewalls of the first hole 131, and a second storage unit disposed on sidewalls of the second hole 132. 134). The first storage unit 133 and the second storage unit 134 may not be connected to each other. Alternatively, a part of the first storage unit 133 and the second storage unit 134 may be connected. In an embodiment, the upper surface of the first storage unit 133 of the data storage pattern may be coplanar with the upper surface of the first pad unit 146 and the upper surface of the first resiliency pattern 142. . In addition, the lower surface of the second storage unit 134 of the data storage pattern may contact the upper surface of the first pad unit 146.

The bit line 168 may be disposed on the active pattern ACT. The bit line 168 may extend in a direction crossing the upper select gate pattern USG. That is, the bit line 168 may extend in a second direction perpendicular to the first direction in which the upper selection gate pattern USG extends. The second direction may correspond to the x-axis direction.

A bit line contact 167 may be disposed between the active pattern ACT and the bit line 168. The active pattern ACT and the bit line 168 may be electrically connected by the bit line contact 167. An ohmic layer 165 may be further interposed between the active pattern ACT and the bit line contact 167.

Hereinafter, a method of forming a nonvolatile memory device according to an embodiment of the present invention will be described with reference to FIGS. 1, 2A, 2B, and 3A to 3I. 3A to 3I are cross-sectional views taken along the line II ′ of FIG. 1. The above description may be partially omitted.

Referring to FIG. 3A, a substrate 110 including a well region is prepared. The well region may be formed by doping a dopant of a first conductivity type to an upper portion of a cell region of the substrate 110. The common source region 112 may be formed in the well region. The common source region 112 may be formed by doping a dopant of a second conductivity type on an upper portion of the well region.

A preliminary base insulating pattern 121 may be formed on the substrate 110. The preliminary base insulation pattern 121 may cover the cell region of the substrate 110. First preliminary gate patterns PLSG and PCG1 and first preliminary inter-gate insulating patterns 123a are stacked on the preliminary base insulating pattern 121. Specifically, a preliminary lower selection gate pattern PLSG is formed on the preliminary base insulation pattern 121. A lowermost first inter-gate insulating pattern 123a is formed on the preliminary lower selection gate pattern PLSG1. Thereafter, the first preliminary cell gate patterns PCG1 and the first preliminary inter-gate insulating patterns 123a are alternately stacked. The first preliminary cell gate pattern PCG1 formed at the top may be covered by the first preliminary inter-gate insulating pattern 123a.

Referring to FIG. 3B, the gate patterns LSG and CG1 and the insulating patterns 122 and 124a are formed by etching the preliminary gate patterns PLSG and PCG1 and the preliminary insulating patterns 121 and 123a. . In detail, the preliminary lower gate pattern PLSG is etched to form a lower gate pattern LSG, and the first preliminary cell gate patterns PCG1 are etched to form first cell gate patterns CG. do. The preliminary base insulating pattern 121 is etched to form a base insulating pattern 122, and the first preliminary inter-gate insulating patterns 123a are etched to form first inter-gate insulating patterns 124a. . Sidewalls of the gate patterns LSG and CG1 and the first insulating patterns 122 and 124 may define sidewalls of the first hole 131. The first hole 131 may include a bottom defined by an upper surface of the substrate 110.

The sidewall of the first hole 131 may not be perpendicular to the top surface of the substrate 110. That is, an angle between the sidewall of the first hole 131 and the normal of the upper surface of the substrate 110 may be greater than 0 °. Widths of the upper portion and the lower portion of the first hole 131 may be different. In an embodiment, the first hole 131 may have the narrowest width at the portion adjacent to the substrate 110 and the largest width at the portion farthest from the substrate 110. The width of the first hole 131 may increase as the distance from the substrate 110 increases.

Referring to FIG. 3C, the first storage part 133 and the first activating layer 141 of the data storage pattern are formed on sidewalls of the first hole 131. The first storage unit 133 of the data storage pattern may be formed on the gate patterns LSG and CG1. The first storage unit 133 of the data storage pattern may be formed by forming a blocking barrier on the gate patterns LSG and CG1 and sequentially forming a charge storage layer and a tunnel barrier on the blocking barrier. In example embodiments, the blocking barrier may be formed by forming a thermal oxide layer on the gate patterns LSG and CG1. The charge storage layer and the tunnel barrier may be formed by sequentially forming a nitride layer and an oxide layer on the thermal oxide layer.

The first activating film 141 may include a single crystal semiconductor material or a polycrystalline semiconductor material. The first activator layer 141 may be conformally formed on the first storage unit 133 of the data storage pattern 133. The first resilient film 141 may have an inclined sidewall along the sidewall of the first hole 131.

Referring to FIG. 3D, a first filling insulating layer 152 is formed in the first hole 131. An upper portion of the first charge insulating layer 152 may be etched. Accordingly, an upper surface of the first charge insulating layer 152 may be lower than an upper surface of the first inter-gate insulating pattern 124a of the uppermost portion. The first filling insulating layer 152 may be removed until a portion of the top surface and the sidewall of the first activating layer 141 is exposed.

Referring to FIG. 3E, a pad layer 145 may be formed to fill an upper portion of the first hole 131. The pad layer 145 may include a semiconductor material. The pad layer 145 may include a single crystal semiconductor material or a polycrystalline semiconductor material. The pad layer 145 may include the same semiconductor material as the first active layer 141.

Referring to FIG. 3F, a portion of the pad layer 145 may be etched to form a first pad portion 146. When the pad layer 145 is removed, a portion of the first resilient layer 141 on the uppermost first inter-gate insulating pattern 124a and the first storage unit 133 of the data storage pattern may also be removed. . As a result, the first resilience pattern 133 may be formed. The pad layer 145 and the first activating layer 141 may be etched until the upper surface of the uppermost first gate insulating pattern 124a is exposed.

An upper surface of the first pad part 146 may be coplanar with an upper surface of the first inter-gate insulating pattern 124a of the uppermost part. In addition, an upper surface of the first pad part 146 may be coplanar with an upper surface of the first storage part 133 of the data storage pattern. The first pad portion 146 may extend an electrically contactable region of the first resilient pattern 142. That is, one component of the memory device electrically connected to the first resilient pattern 133 may be directly connected to the first resilient pattern 133 or may be formed through the first pad part 146. 1 may be connected to the resurrection pattern 133.

Referring to FIG. 3G, second preliminary inter-gate insulating layers 123b and 125 and second preliminary gate patterns PCG2 and PUSG may be alternately stacked on the structure formed by FIG. 3F. The second preliminary inter-gate insulation pattern 123b formed at the lowermost portion may contact the first inter-gate insulation pattern 124a disposed at the uppermost portion.

The preliminary gate pattern PUSG formed at the top of the second preliminary gate patterns PCG2 and PUSG may be a preliminary upper selection gate pattern PUSG. The second preliminary gate patterns CG2 between the second preliminary inter-gate insulating pattern 123b and the preliminary upper selection gate pattern PUSG may be second preliminary cell gate patterns CG2. A preliminary upper insulating pattern 125 may be formed on the upper selection gate pattern USG.

Referring to FIG. 3H, the second preliminary inter-gate insulating layers 123b and 125 and the second preliminary gate patterns PCG2 and PUSG are etched. The second preliminary inter-gate insulating layers 123b and 125 and the preliminary gate patterns PCG2 and PUSG may be etched until the first pad portion 146 is exposed. By the etching, the second cell gate patterns CG2, the upper selection gate pattern USG, and the insulating patterns 124b and 126 are formed.

The second hole 132 is defined by sidewalls of the gate patterns CG and USG and the insulating patterns 124b and 126 and an upper surface of the first pad part 146. The second hole 132 may form an opening 130 together with the first hole 131.

The sidewall of the second hole 132 may not be perpendicular to the upper surface of the substrate 110. That is, an angle between the sidewall of the second hole 132 and the normal of the upper surface of the substrate 110 may be greater than 0 °. Widths of the upper portion and the lower portion of the second hole 132 may be different. In an embodiment, the second hole 132 may be larger as it moves away from the first hole 131. The lowermost part of the second hole 132 may have a smaller width than the uppermost part of the first hole 131. An upper end of the side wall of the first hole 131 and a lower end of the side wall of the second hole 132 may not be connected.

At least a portion of the bottom of the second hole 132 may be defined by an upper surface of the first pad part 146. The second hole 132 may expose an upper surface of the first resilient pattern 142. The bottom of the second hole 132 may be defined within an upper surface of the first pad part 146 and an upper surface of the first resilient pattern 142. Alternatively, the bottom of the second hole 132 may extend to the top surface of the data storage pattern first storage unit 133.

Referring to FIG. 3I, a second storage unit 134 and a second resiliency pattern 148 of the data storage pattern are formed in the second hole 132. The second storage unit 134 of the data storage pattern may not be connected to the first storage unit 133 of the data storage pattern. This may be due to the sidewalls of the first hole 131 and the second hole 132 not being connected to each other. Alternatively, some of the first and second storage units 133 and 134 of the data storage pattern may be connected.

In an embodiment, the second resilience pattern 148 may be formed on sidewalls of the second storage unit 134 of the data storage pattern. The lower surface of the second resilient pattern 148 may contact the upper surface of the first pad part 146. A portion of the lower surface of the second resilient pattern 148 may contact the upper surface of the first resilient pattern 142. The second resiliency pattern 148 may be connected to the first resiliency pattern 142 by the first pad part 146. The first resiliency pattern 142, the first pad part 146, and the second resiliency pattern 148 may constitute one active pattern ACT.

The second resiliency pattern 148 may be stably connected to the first resiliency pattern 142 by the first pad part 146. For example, when the first pad portion is not disposed on the first resilient pattern, the process margin for forming the second hole and the second resilient pattern is due to the area of the narrow upper surface of the first resilient pattern. This may not be secured enough. However, in the case of forming the first pad part 146, when forming the second hole 132 and the second resilience pattern 148, a larger process margin may be secured. Can be. In detail, even when the second hole 132 is not aligned with the first hole 131, the second resilience pattern 148 is regenerated by the first pad part 146. It may be connected to the sex pattern 142. Accordingly, it is possible to easily form a plurality of holes and accompanying memory components on one substrate. That is, a nonvolatile memory device optimized for high integration may be formed.

The second resiliency pattern 148 may have an inner space. For example, the second resiliency pattern 148 may be in the form of a shell. In one embodiment, the second resiliency pattern 148 may be an unfilled truncated cone or pyramidal. When the second resilient pattern 148 is formed in a truncated cone shape or a pyramidal shape, the width of the upper portion of the second resilient pattern 148 may be larger than the width of the lower portion. Alternatively, the second resilient pattern 148 may be a filled cone or a pyramidal shape having no internal space.

When the second resilient pattern 148 has an inner space, the inner space of the second resilient pattern 148 may be filled with the second filling insulating layer 154. An upper surface of the upper filling insulating layer 154 may be lower than an upper surface of the second resilient pattern 148. That is, the upper filling insulating layer 154 may not fill the uppermost part of the inner space of the second resilient pattern 148.

When the second resilient pattern 148 has an internal space, a second pad part 150 may be formed on the upper filling insulating layer 154. The second pad part 150 may fill an uppermost portion of an inner space of the second resiliency pattern 148. An upper surface of the second pad part 150 may be coplanar with an upper surface of the second resilient pattern 148. In addition, the second pad part 150 may be coplanar with an upper surface of the second storage part 134 of the data storage pattern.

The second pad part 150 may include a semiconductor material. The second pad part 150 may include a single crystal semiconductor material or a polycrystalline semiconductor material. The second pad part 150 may include the same semiconductor material as the second resilient pattern 148. The second pad part 150 may widen an area where other components of the device may electrically contact the second resiliency pattern 148.

Specifically, when the second pad part 150 is absent, in order for one component to electrically connect with the second resiliency pattern 148, the one component is at least the second resiliency pattern 148. You must contact some of the However, according to one embodiment of the present invention, when the second pad portion 150 is formed in contact with the second resilience pattern 148, the one component may be formed of the second resilience pattern 148 or the first. The second pad 150 may be electrically connected to the second resiliency pattern 148 by contacting the pad portion 150.

Referring back to FIGS. 1 and 2A through 2B, the upper select gate pattern USG may be additionally patterned. Unlike the above description, the upper selection gate pattern USG may be formed by forming a separate conductive layer on the uppermost inter-gate insulating pattern 124b and then patterning the conductive layer. The patterned upper selection gate pattern USG may have a line shape extending in a first direction. The first direction may correspond to the x-axis direction. By the patterning, a plurality of upper selection gate patterns USG extending in parallel in a first direction may be disposed in the cell region of the substrate 110. An insulating pattern may be formed next to a sidewall of the patterned upper selection gate pattern USG. The insulating pattern formed on the sidewall of the upper selection gate pattern USG and the insulating pattern on the upper surface of the upper selection gate pattern USG may constitute the upper insulating pattern 126.

An interlayer insulating layer 162 is formed on the second active pattern 148. The interlayer insulating layer 162 is etched to form a contact hole 163 exposing the top surface of the second activation pattern 148 and / or the second pad part 150. An ohmic layer 165 may be formed on an upper surface of the second resilient pattern 148 and / or the second pad part 150. The ohmic layer 165 may be formed by reacting the exposed upper surface of the second resilient pattern 148 and / or the second pad part 150 with a metal. A bit line contact 167 is formed by filling a conductive material in the contact hole 163. A bit line 168 may be formed on the bit line contact 167. The bit line 168 may extend in a second direction crossing the upper select gate pattern USG. The second direction may correspond to the y-axis direction.

4 and 5, a nonvolatile memory device according to another embodiment of the present invention will be described. 4 is a plan view of a nonvolatile memory device according to another exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view of the nonvolatile memory device taken along line II ′ of FIG. 4.

The substrate 210 including the well region is prepared. The well region may be a region doped with a dopant of a first conductivity type in the substrate 210. The common source region 212 may be disposed in the well region. The common source region 212 may be a region doped with a dopant of a second conductivity type.

As illustrated in FIG. 5, a plurality of gate patterns LSG ′, CG1 ′, CG2 ′, and USG ′ and insulating patterns 222, 224a, 224b, and 226 are alternately stacked on the substrate 210. Can be. The gate pattern LSG 'disposed at the bottom of the gate patterns LSG', CG1 ', CG2', and USG 'is a lower select gate pattern LSG', and the gate pattern USG 'disposed at the top thereof is It may be a top select gate pattern USG '. Gate patterns CG1 ′ and CG2 ′ between the lower select gate pattern LSG ′ and the upper select gate pattern USG ′ may be formed of first cell gate patterns CG1 ′ and second cell gate patterns CG2. May be '). The gate patterns LSG ', CG1', CG2 ', and USG' may have a line shape extending in a first direction. Gate patterns LSG ', CG1', CG2 ', and USG' stacked vertically on the substrate 210 may constitute one gate pattern group GG.

The lowermost of the insulating patterns 222, 224a, 224b, and 226, that is, the insulating pattern 222 interposed between the substrate 210 and the lower selection gate pattern LSG ′ may be a base insulating pattern 222. have. The insulating patterns 224a interposed between the lower selection gate pattern LSG 'and the lowermost cell gate pattern CG1' and between the first cell gate patterns CG1 'may include a first inter-gate insulating pattern. 224a. The insulating patterns 224b interposed between the uppermost cell gate pattern CG2 ′ and the upper selection gate pattern USG ′ may be second inter-gate insulating patterns 224b. The first inter-gate insulating pattern 224a and the second inter-gate insulating pattern 224b may be interposed between the uppermost first cell gate pattern CG1 ′ and the lowermost second cell gate pattern CG2 ′. . The insulating pattern 226 disposed on the upper selection gate pattern USG 'may be an upper insulating pattern 226.

As shown in FIG. 4, a plurality of gate pattern groups GG extending in one direction may be disposed in the cell region of the substrate 210. The gate pattern groups GG may extend in parallel to each other in a first direction. The first direction may correspond to the y-axis direction.

An opening 230 extending along the first direction may be defined between the pair of gate pattern groups GG. The opening 230 is a bottom defined by the substrate 210, and sidewalls of the gate patterns LSG ′, CG1, CG2 ′ and USG ′ and the insulating patterns 222, 224a, 224b, and 226. It can have a sidewall defined by. The opening 230 may include the first groove 231 and the second cell gate patterns CG2 ′ defined by sidewalls of the lower selection gate pattern LSG ′ and the first cell gate patterns CG1 ′. And the second groove 232 defined by sidewalls of the upper selection gate pattern USG 'may be spaces connected vertically.

The first groove 231 and the second groove 232 may have inclined sidewalls. That is, the gate patterns LSG ', CG1', CG2 ', and USG' defining the sidewalls of the first groove 231 and the second groove 232 and the insulating patterns 222, 224a, 224b, and 226. Sidewalls of the substrate 210 may not be perpendicular to the top surface of the substrate 210. For example, sidewalls and bottom surfaces of the gate patterns LSG ', CG1', CG2 ', and USG' may be at an acute angle.

An active pattern ACT ′ extending upward along some sidewalls of the opening 230 may be disposed on the substrate 210. As illustrated in FIG. 4, a plurality of active patterns ACT ′ may be horizontally spaced apart from one opening 231. As shown in FIG. 5, the active pattern ACT ′ is disposed on sidewalls of the first resilient pattern 242 and the second groove 232 disposed on sidewalls of the first groove 232. The second resilience pattern 248, and the first pad portion 246 connecting the first resilience pattern 242 and the second resilience pattern 248 may be included. The first and second resilient patterns 242 and 248 and the first pad part 246 may each include a semiconductor material. In some embodiments, the first and second resilient patterns 242 and 248 and the first pad part 246 may all include the same semiconductor material.

 The first resilient pattern 242 may have an inclined sidewall. This may be due to the inclined sidewall of the first groove 231 described above. It may be in the form of a flat plate covering a portion of the sidewall of the first groove 231. Accordingly, an inner space may be defined between the first resilient patterns 242 disposed on the sidewalls of the pair of gate pattern groups GG. The first charge insulating layer 252 may fill an internal space between the first resilient patterns 242. In one embodiment, the first resilient pattern 242 may include a bottom portion extending on the top surface of the substrate 210. In this case, the bottom portion may be interposed between the substrate 210 and the first charge insulating layer 252. In contrast, the first resilient pattern 242 may not include a bottom portion.

The first pad part 246 may have a sidewall contacting an upper sidewall of the first resilient pattern 242. In one embodiment, the first pad portion 246 is disposed between the pair of first resilient patterns 242 facing each other, and coplanar with the top surfaces of the pair of first resilient patterns 242. It may have an upper surface constituting. The cross-sectional area of the upper surface of the first pad part 246 may be larger than the cross-sectional area of the upper surface of the first resilient pattern 242.

The second resilient pattern 248 may have an inclined sidewall. This may be due to the inclined sidewalls of the second groove 232 described above. The lower sidewall of the second resilient pattern 248 may be moved laterally from the upper sidewall of the first resilient pattern 242 toward the center of the first pad part 246.

In an embodiment, the sidewalls of the second resilient pattern 248 may be formed in a flat plate shape on some sidewalls of the second groove 232 similar to the first resilient pattern 242. In this case, an inner space may be defined by second resilient patterns 248 on both sidewalls of the second groove 232. The internal space defined by the second resilient patterns 248 may be filled by the second filling insulating layer 254. Alternatively, the second resilience pattern 248 may be formed to fill the internal space.

The second resiliency pattern 248 may be electrically connected to the first resiliency pattern 242. To this end, a lower surface of the second resilient pattern 248 may contact the upper surface of the first pad part 246 and / or the upper surface of the first resilient pattern 242.

The second activation pattern 248 may be easily electrically connected to the first activation pattern 242 by the first pad part 246. Specifically, in order for the first resilient pattern and the second resilient pattern to be electrically connected without the first pad part, the upper surface of the first resilient pattern and the lower surface of the second resilient pattern must be directly contacted. . As described above, since the first resilient pattern has an inner space and is formed to have a narrow upper surface, contact with the second resilient pattern may not be easy. However, when the first pad part 246 is disposed in the active pattern ACT, the bottom surface of the second resiliency pattern 248 may be the first pad part ( It may also be electrically connected to the first resilient pattern 242 by being in contact with the top surface of 246. Therefore, it may not be necessary that the first resiliency pattern 242 and the second resiliency pattern 248 are exactly self aligned. As such, more resilient patterns and accompanying memory components may be stacked on the substrate. Thus, a nonvolatile memory device optimized for high integration is provided.

When the second resiliency pattern 248 defines an internal space in the second groove 232, the first pad part 250 may be disposed on the second resiliency pattern 248. The first pad part 250 may have an upper surface coplanar with an upper surface of the second resilient pattern 248. The sidewall of the first pad part 250 may contact the inner side wall of the uppermost part of the second resilient pattern 248.

Data storage patterns 232 and 234 may be interposed between the active pattern ACT and the gate patterns LSG ', CG1', CG2 ', and USG'. The data storage patterns 232 and 234 may extend on upper and lower surfaces of the gate patterns LSG ', CG1', CG2 'and USG'. In addition, the data storage patterns 232 and 234 may extend on sidewalls of the insulating patterns 222, 224a, and 226 that do not contact the active pattern ACT. Alternatively, the data storage patterns 233 and 234 may be disposed only on the top, bottom and one sidewall of the gate patterns LSG ', CG1', CG2 'and USG'.

The data storage patterns 232 and 234 may include a first storage unit 233 between the first cell gate patterns CG1 ′, the lower selection gate pattern LSG ′, and the first resiliency pattern 242. The second cell gate patterns CG2 ′ and the second storage unit 234 between the upper selection gate pattern USG ′ and the second resiliency pattern 248 may be included. The first storage unit 233 and the second storage unit 234 may be a plurality of films separated from each other. An upper surface of the first storage unit 233 may be in contact with the second storage unit 234 interposed below the second cell gate pattern CG2 ′ at the lowermost portion.

The bit line 268 may be disposed on the second resiliency pattern 248. The bit line 268 may extend in a second direction crossing the first direction in which the gate pattern groups GG extend. The second direction may correspond to the x-axis direction.

A bit line contact 267 may be interposed between the bit line 268 and the second resiliency pattern 248. An ohmic layer 265 may be interposed between the bit line contact 267 and the second resilience pattern 248. The ohmic layer 265 may lower the resistance between the second resilience pattern 248 and the bit line contact 267.

When the second resiliency pattern 248 defines an internal space, the bit line contact 267 and the second resiliency pattern 248 may be electrically connected by the first pad part 250. When the second resilience pattern 248 defines an internal space, the second resilience pattern 248 may have a relatively narrow upper surface. In this case, since the first pad part 250 is disposed, electrical connection between the second resiliency pattern 248 and the bit line 268 may be facilitated.

Although an embodiment including two resiliency patterns and a pad portion connecting the resilience patterns has been described above, embodiments of the present invention include two or more resilience patterns and a first pad portion between the resilience patterns. It includes a nonvolatile memory device including. In detail, a third resilience pattern, third gate patterns, and components connected thereto may be further disposed on the second resilience pattern and the second gate patterns. In this case, the gate pattern of the uppermost of the second gate patterns may be a cell gate pattern, as described above. That is, the nonvolatile memory device according to the embodiment of the present invention includes at least two activating patterns and a pad unit connecting the activating patterns.

4, 5, and 6A through 6K, a method of forming a nonvolatile memory device according to another embodiment of the present invention will be described. 6A through 6K are cross-sectional views illustrating a nonvolatile memory device taken along the line II ′ illustrated in FIG. 4. The foregoing description may be partially omitted.

Referring to FIG. 6A, a well region is formed by doping the substrate 210 with a dopant of a first conductivity type. The upper portion of the well region is doped with a second conductivity type dopant to form a common source region 212. An upper surface of the common source region 212 may be the same as an upper surface of the substrate 210.

A preliminary base insulation pattern 221 is formed on the substrate 212. First sacrificial layers SC1 and first pre-gate insulating patterns 221 and 223a are alternately stacked on the preliminary base insulating pattern 221. The first sacrificial layers SC1 and the first preliminary gate insulating patterns 221 and 223a may be formed of materials having different etching amounts under the same etching conditions. For example, the first sacrificial layers SC1 may be formed of a nitride layer, and the preliminary insulating patterns 221 and 223a may be formed of an oxide layer.

Referring to FIG. 6B, the first sacrificial layers SC1 and the first preliminary gate insulating patterns 221 and 223a are anisotropically etched to insulate the first sacrificial layers SC1 and the first preliminary gates. The first groove 231 penetrating the patterns 221 and 223a is formed. The first groove 231 may extend along the first direction. The first direction may correspond to the y-axis.

The first groove 231 may have an inclined sidewall. That is, sidewalls of the first sacrificial layers SC1 and the first preliminary inter-gate insulating patterns 221 and 223a defining the sidewalls of the first groove 231 are normal to the upper surface of the substrate 210. Can be tilted from. The sidewall of the first groove 231 is inclined with respect to the normal of the upper surface of the substrate 210, and the insulating patterns 221 between the first sacrificial layers SC1 and the first preliminary gate are stacked. 223a) may be proportional to the thickness. When the first groove 231 is formed, a portion of the common source region 212 may also be etched to expose the well region.

Referring to FIG. 6C, a first activating film 241 may be formed on the sidewall of the first groove 231. The first activation film 241 may be formed on sidewalls of the first groove 231. In detail, a semiconductor film conformally covering the first groove 231 may be formed. The semiconductor film may include a single crystal semiconductor material or a polycrystalline semiconductor material. Spacers may be formed in the first groove 231 on the semiconductor film. The spacer may cover sidewalls of the first groove 231 and the semiconductor film. In addition, the spacer may expose a portion of the semiconductor film on the substrate 210. A portion of the exposed semiconductor film may be etched to form a first activating layer 241 on sidewalls of the first groove 231. Alternatively, the process of removing the semiconductor film formed on the substrate 210 may be omitted. The first activating film 241 formed by this may include a bottom portion disposed on the substrate 210.

A first filling insulating layer 252 may be formed to fill the first groove 231. An upper surface of the first charge insulating layer 252 may be formed to have an upper surface lower than an upper surface of the uppermost first inter-gate insulating pattern 223a. As a result, a portion of the upper sidewall of the first groove 231 may be exposed.

Referring to FIG. 6D, a first pad part 246 may be formed on the first groove 231. The first pad part 246 may be formed by forming a semiconductor film filling the first groove 231 and then removing a portion of the semiconductor film. The semiconductor layer may be removed until the uppermost first inter-gate insulating pattern 223a is exposed. In this case, the first activating layer 241 on the uppermost first inter-gate insulating pattern 223a may also be removed. As a result, the first resilience pattern 241 may be formed. An upper surface of the first pad part 246 may be coplanar with an upper surface of the first inter-gate insulating pattern 223a. An upper surface of the first pad part 246 may be coplanar with an upper surface of the first resilient pattern 241. The first pad part 246 may include the same semiconductor material as the first resilient pattern 241.

Referring to FIG. 6E, the first sacrificial layers SC1 and the first preliminary insulating patterns 221 and 223a are patterned. As a result, the first inter-gate insulating patterns 224a and the base insulating pattern 222 may be formed. The first trench 255 may be defined by sidewalls of the first insulating patterns 222 and 224a and the first sacrificial layers SC1. The first trench 255 may have a groove shape extending in a direction parallel to a direction in which the first groove 231 extends. Sidewalls of the first insulating patterns 222 and 224a and the first sacrificial layers SC1 may be exposed by the first trench 255. The first trench 255 may have an inclined sidewall.

Referring to FIG. 6F, the first sacrificial layers SC1 exposed in the first trench 255 are removed. Accordingly, a first empty space 255u may be formed between the first inter-gate insulating patterns 224a and between the lowermost first inter-gate insulating pattern 224a and the base insulating pattern 222. A portion of the sidewall of the first resilient pattern 242 may be exposed in the first empty space 255u. The upper and lower surfaces of the inter-gate insulating patterns 224a and the upper surface of the base insulating pattern 222 may be exposed by the formation of the first empty space 255u.

The first storage unit 233 of the data storage pattern may be formed in the first trench 255 and the first empty space 255u. The first storage unit 233 of the data storage pattern may conformally cover the first trench 255 and the first empty space 255u. The first storage unit 233 of the data storage pattern may include a plurality of layers. Specifically, forming the first storage unit 233 of the data storage pattern may include forming a tunnel barrier in contact with the first resiliency pattern 242, forming a charge storage layer on the tunnel barrier, and It may include forming a blocking barrier on the charge storage layer. In an embodiment, the tunnel barrier may be formed by oxidizing exposed sidewalls of the first resilient pattern 242.

Referring to FIG. 6G, a gate layer GL may be formed to fill the first trench 255 and the first empty space 255u. The gate layer GL may include a doped semiconductor material, a metal, or a metal compound. An upper surface of the gate layer GL may be planarized. When the planarization is performed, the first storage part 233 of the gator storage pattern formed on the upper surface of the upper gate insulating pattern 224a may be removed. As a result, an upper surface of the first pad part 246 and the uppermost inter-gate insulating layer 224a may be exposed.

Referring to FIG. 6H, first gate patterns LSG ′ and CG1 ′ may be formed by etching the gate layer GL. The first gate patterns LSG 'and CG1' may be the gate layer GL remaining in the first empty space 255u. Among the first gate patterns LSG 'and CG1', the gate pattern LSG 'between the base insulating pattern 222 and the lowermost inter-gate insulating pattern 224a may be a lower selection gate pattern LSG'. have. Gate patterns CG1 ′ formed between the inter-gate insulating patterns 224a may be cell gate patterns CG ′.

A first charge insulating layer 256 may be formed in the first trench 255. The first charge insulating layer 256 may be planarized until the upper inter-gate insulating pattern 224a and the upper surfaces of the first pad part 246 are exposed.

Referring to FIG. 6I, second sacrificial layers SC2 and second preliminary insulating patterns 223b and 225 may be alternately stacked on the structure of FIG. 6H. The second preliminary insulating patterns 223b and 225 may include second preliminary inter-gate insulating patterns 223b between the sacrificial layers SC2 and a preliminary upper insulating pattern on the uppermost second sacrificial layer SC2. 225). The lowermost second sacrificial layer SC2 may be in contact with the upper inter-gate insulating pattern 224a and the upper surfaces of the first pad part 246. The second sacrificial layers SC2 and the second preliminary insulating patterns 223b may be formed of materials having different etching selectivity.

A second groove 232 may be formed to penetrate the second sacrificial layers SC2 and the second preliminary insulating patterns 223b and 225. The second groove 232 is a sidewall defined by sidewalls of the second sacrificial layers SC2 and the second preliminary insulating patterns 223b, and a bottom defined by the first pad part 246. It may include. Sidewalls of the second groove 232 may be inclined.

The second groove 232 may be connected to the first groove 231 up and down. The second groove 232 may extend in a direction parallel to the first groove 231, that is, in a first direction. The first groove 231 and the second groove 232 may constitute one opening 230.

A second resilience pattern 248 may be formed in the second groove 232. The second resilience pattern 248 may be formed by the same method as the first resilience pattern 242 described above. In this case, the second filling insulating layer 254 may be formed in the inner space defined by the second resilient pattern 248. An upper surface of the second charge insulating layer 254 may be lower than an upper surface of the preliminary upper insulating pattern 225. Alternatively, the second resilience pattern 248 may be formed to fill the second groove 232. In this case, the second filling insulating layer 254 may not be formed in the second groove 232.

The second pad part 250 may be formed on the second resilient pattern 248. The second pad part 250 may be formed next to an upper portion of the second resilient pattern 248. When the second resiliency pattern 248 defines an internal space, the second pad part 250 may fill the internal space defined by the second resiliency pattern 248. An upper surface of the second pad part 25 may be coplanar with an upper surface of the second resilient pattern 248 and an upper surface of the preliminary upper insulating pattern 225.

Referring to FIG. 6J, the second sacrificial layers SC2 and the second preliminary insulating patterns 223b and 225 may be patterned. As a result, the second insulating patterns 224b and 226 may be formed. The insulating patterns 224b and 226 may include second inter-gate insulating patterns 224b between the patterned second sacrificial layers SC2 and an upper insulating pattern 226 on the uppermost second sacrificial layer SC2. It may be configured as.

By the patterning, a second trench 257 may be formed. The second trench 257 may expose sidewalls of the second insulating patterns 224b and 226 and the patterned second sacrificial layers SC2.

Referring to FIG. 6K, the exposed second sacrificial layers SC2 may be removed to form a second empty space 257u between the insulating patterns 224b and 226. The second empty space 257u may expose sidewalls of the second resilient pattern 248 and upper and lower surfaces of the second insulating patterns 224b and 226. The lowermost second empty space 257u may expose an upper surface of the uppermost first inter-gate insulating pattern 224a.

The second storage unit 234 of the data storage pattern covering the second trench 257 and the second empty space 257u may be formed. The second storage unit 234 of the data storage pattern may be formed by the same method as the first storage unit 233 of the data storage pattern. The second storage unit 234 of the data storage pattern may contact the upper surface of the first storage unit 233 of the data storage pattern.

Referring to FIG. 5 again, second gate patterns CG2 ′ and USG ′ may be formed to fill the second empty space 257u. The second gate patterns CG2 ′ and USG ′ are formed by forming a gate layer filling the second trench 257 and the second empty space 257u, and then removing the gate layer in the second trench 257. Can be. Prior to removal of the gate film in the second trench 257, the top surface of the gate film may be planarized. In this case, a portion of the data storage pattern 234 on the upper insulating pattern 226 and the second pad part 250 may also be removed. After the control of the gate layer, an insulating layer 258 may be formed to fill the second trench 257.

The conductive layer remaining in the second empty space 257u may form the second gate patterns CG2 'and USG'. The gate pattern USG 'formed at the top of the second gate patterns CG2' and USG 'is an upper selection gate pattern USG', and is disposed between the second inter-gate insulating patterns 224b and the top. The gate patterns CG2 'between the first inter-gate insulating pattern 224a and the lowermost second inter-gate insulating pattern 224b may be second cell gate patterns CG2'.

An interlayer insulating layer 262 may be formed on the second pad part 250 and the upper insulating pattern 226. The interlayer insulating layer 262 may include a contact hole exposing an upper surface of the second pad part 250. An ohmic layer 265 may be formed on the second pad part 250. The ohmic layer 265 may be formed by metallizing an upper surface of the exposed second pad part 250.

The contact hole may be filled with a conductive material to form a bit line contact 267. A bit line 268 may be formed on the bit line contact 267. The bit line 268 may be in the form of a line extending in a second direction. The bit line contact 267 and the bit line 268 may be formed at the same time.

7, an application example of embodiments of the present invention is described. 7 is a block diagram illustrating an example of a memory card 1100 including a semiconductor device according to an embodiment of the present invention. In this application example, the semiconductor device may be applied to the flash memory 1110. A semiconductor device according to an embodiment of the present invention is mounted in a memory card 1100 for supporting a high capacity of data storage capability. The memory card 1100 according to the present exemplary embodiment may include a memory controller 1120 that controls overall data exchange between the host and the flash memory 1110.

The memory controller 1120 may include a processing unit 1122, an SRAM 1120, an error correction block 1124, a host interface 1123, and a memory interface 1125 for controlling an operation of a memory card. The SRAM 1121 may be used as an operating memory of the processing unit 1122. The host interface 1123 may include a data exchange protocol of a host connected to the memory card 1100. The error correction block 1124 may detect and correct an error included in data read from the flash memory 1110. The memory interface 1125 may interface with the flash memory 1110. The processing unit 1122 may perform various control operations for exchanging data of the memory controller 1120. The memory card 1100 according to the present application may provide a system having high reliability due to the improved reliability of the flash memory 1110 according to the embodiment of the present invention.

8 is a diagram for describing another application example of the semiconductor device according to example embodiments. 8 is a block diagram illustrating an information processing system 1200 including a memory system 1210. In the present application, the semiconductor device according to the embodiments of the present invention may be included in the memory system 1210. An information processing system such as a mobile device or a desktop computer may be equipped with a memory system 1210 according to embodiments of the present invention. The information processing system 1200 according to the present application includes a modem 1220, a central processing unit 1230, a RAM 1240, and a user interface 1250 electrically connected to a memory system 1210 and a system bus 1260, respectively. It may include. The memory system 1210 may store data processed by the CPU 1230 or data externally input. In the present application, the memory system 1210 according to the embodiments of the present invention may be configured as a semiconductor disk device (SSD), in which case the information processing system 1200 stores a large amount of data in the memory system 1210. Can be stored reliably. In addition, according to the above-described improvement of the reliability of the semiconductor device, the memory system 1210 may reduce resources required for error correction, thereby providing the information processing system 1200 with a high speed data exchange function.

In addition, the semiconductor device according to example embodiments may be implemented in various types of packages. For example, the semiconductor device according to the present invention may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package (WSP) or the like can be packaged and mounted.

1 is a plan view of a nonvolatile memory device according to an embodiment of the present invention.

FIG. 2A is a cross-sectional view taken along the line II ′ of FIG. 1, and FIG. 2B is a cross-sectional view taken along the line II-II ′ of FIG. 1.

3A to 3I are diagrams for describing a method of forming a nonvolatile memory device according to an embodiment of the present invention.

4 is a plan view of a nonvolatile memory device according to another exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view taken along the line II ′ of FIG. 4.

6A to 6K are diagrams for describing a method of forming a nonvolatile memory device according to another exemplary embodiment of the present invention.

7 and 8 are diagrams for describing devices to which embodiments of the present invention are applied.

Claims (10)

Gate patterns and insulating patterns alternately stacked on a substrate; An active pattern extending upward along sidewalls of the gate patterns and the insulating patterns on the substrate; And A data storage pattern between the gate patterns and an active pattern, The active pattern may include a first sub-active pattern, a second resilient pattern on the first resilient pattern, and a first pad portion connecting the first and second resilient patterns. Include, The cross-sectional area of the upper surface of the first pad portion is larger than the cross-sectional area of the upper surface of the first resilient pattern. The method according to claim 1, The active pattern is disposed in an opening that passes through the gate patterns and the insulating patterns, and the first resilient pattern is disposed along a sidewall of the opening to define an inner space surrounded by the first resilient pattern. The internal space is filled by a charge insulating pattern, and the first pad portion is disposed on the charge insulating layer. The method according to claim 2, The upper surface of the first pad portion is coplanar with the upper surface of the first activation pattern. The method according to claim 3, The lower surface of the second resilient pattern is in contact with the upper surface of the first pad portion, The lower portion of the sidewall adjacent to the data storage pattern of the second resilient pattern is moved laterally toward the center of the first pad portion from the sidewall adjacent to the data storage pattern of the first resilient pattern. The method according to claim 1, The data storage pattern may include a first storage unit between the first resilience pattern and the gate patterns next to the first resilience pattern, and the gate patterns next to the second and second resilience patterns. Including a second reservoir of And a first storage unit and a second storage unit separated from each other. The method according to claim 1, The alternately stacked gate patterns and insulating patterns constitute one gate group, A pair of the gate groups are spaced apart from each other on the substrate, a groove is defined between the pair of gate groups, A pair of the first resilient patterns spaced apart from each other are disposed on both side walls of the groove, And a filling insulating layer between the pair of first activation patterns, wherein the first pad part is disposed on the filling insulating layer. The method according to claim 1, The first volatile pattern, the second volatile pattern, and the first pad portion include the same semiconductor material. The method according to claim 1, A second pad portion on the second resilience pattern; And Further comprising a bit line electrically connected to the second pad portion, The area of the upper surface of the second pad portion is larger than the area of the upper surface of the second activation pattern. The method according to claim 8, And a ohmic layer between the second pad portion and the bit line. The method according to claim 1, The data storage pattern includes a tunnel barrier adjacent to the active pattern, a blocking barrier adjacent to the gate pattern, and a charge storage layer between the tunnel barrier and the blocking barrier.

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