KR20100058224A - Test system for liquid crystal display - Google Patents

Abstract

PURPOSE: A system for testing an LCD device which embodies a test pattern using a switchboard is provided to embody a suitable test pattern according to the purpose of a user by displaying the test pattern according to a handling signal of a switchboard including the test pattern in an LCD(Liquid Crystal Display) device. CONSTITUTION: A timing controller(140) controls operation timing of drive circuits(120,130). The timing controller comprises a plurality of test pattern data. A switchboard comprises a plurality of pattern alternate switches. The switchboard supplies a pattern change signal to an LCD device(100). The pattern change signal is generated by turning on one among pattern change switches. One of test pattern data is selected as test pattern data for a display on the LCD panel.

Description

Test System For Liquid Crystal Display

The present invention relates to an inspection system for a liquid crystal display device used for inspection of a liquid crystal display device.

In today's information society, display elements are more important than ever as visual information transfer media. Cathode ray tubes or cathode ray tubes, which are currently mainstream, have problems with weight and volume. Many kinds of flat panel displays have been developed to overcome the limitations of the cathode ray tube.

The flat panel display includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) and an organic light emitting diode display (OLED). OLED), and most of them are commercially available and commercially available.

Liquid crystal display devices can meet the trend of light and short and short of electronic products and mass production is improving, and are rapidly replacing cathode ray tubes in many applications. In particular, an active matrix type liquid crystal display device that drives a liquid crystal cell using a thin film transistor (hereinafter, referred to as a TFT) has excellent image quality and low power consumption. As a result of research and development, it is rapidly developing into larger size and higher resolution.

A manufacturing process for manufacturing an active matrix type liquid crystal display device is divided into a substrate cleaning, a substrate patterning process, an alignment film forming / rubbing process, a substrate bonding / liquid crystal injection process, a mounting process, an inspection process, a repair process, and the like.

Among these, the inspection process includes detailed inspection steps such as auto probe inspection, tab inspection, board assembly inspection, liquid crystal module final inspection and reliability test. Each inspection step is performed using the inspection system for the liquid crystal display device as shown in FIG.

Referring to FIG. 1, a conventional inspection system for a liquid crystal display device includes a liquid crystal display device 10 in which an inspection pattern is displayed, a signal generator 40 for generating an inspection pattern, a signal generator 40, and a liquid crystal display device 10. And an interface board 20 connected to each other to perform a test pattern transmission function, and a power supply 30 to supply power to the interface board 20. The liquid crystal display device 10 supplies a liquid crystal display panel for displaying an inspection pattern, an inspection pattern from the interface board 20 to the liquid crystal display panel, and mounts a timing controller 16 to drive the liquid crystal display panel. A printed circuit board 15 for generating a plurality of driving signals required is provided. The interface board 20 includes one or more video integrated circuits used for signal transmission. The printed circuit board 15 and the interface board 20 of the liquid crystal display device 10 are electrically connected through the first connection cable 18, and the interface board 20 and the signal generator 40 are connected to the second connection cable. It is electrically connected via 28. The conventional inspection system for a liquid crystal display device displays the inspection pattern as shown in FIG. 2 on the liquid crystal display panel of the liquid crystal display device 10 through the above configuration. Then, the user can determine the state of good health of the liquid crystal display device based on the displayed image.

However, since the liquid crystal display device cannot implement the test pattern on its own without supplying a signal from the outside, a signal generator, an interface board, and a connection cable must be provided in the conventional liquid crystal display inspection system. Further, since the resolution of the liquid crystal display panel differs depending on the model of the liquid crystal display device to be inspected, the timing signal of the signal generator should be changed every time the model of the liquid crystal display device changes. In addition, since the liquid crystal display device to be inspected has different interface methods and pin maps for each model, the conventional liquid crystal display device inspection system for each liquid crystal display device changes the model of the liquid crystal display device to an interface board and connection cable suitable for the corresponding model. Change must be preceded. In other words, in the case of using the inspection system for a conventional liquid crystal display device, in response to the change of the model of the liquid crystal display device, the timing signal of the signal generator and the replacement of the interface board and the connection cable are required, which is disadvantageous in terms of time and cost. In addition, there are disadvantages in the process of separately managing the interface board and the connection cable for each model.

Accordingly, it is an object of the present invention to provide an inspection system for a liquid crystal display device in which an inspection pattern is embedded in the liquid crystal display device so that the inspection pattern can be implemented without a separate signal generator and an interface board.

In order to achieve the above object, an inspection system for a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display panel having intersections of gate lines and data lines and having liquid crystal cells formed at respective intersection regions thereof, for driving the data lines. A liquid crystal display having a data driving circuit, a gate driving circuit for driving the gate lines, and a timing controller for controlling an operation timing of the driving circuits and embedding a plurality of inspection pattern data to be displayed on the liquid crystal display panel; A switch board for supplying a pattern change signal to the liquid crystal display device including a plurality of pattern change switches; And a power supply for generating a driving voltage necessary for the operation of the liquid crystal display and the switchboard. The pattern change signal may be generated by turning on any one of the pattern change switches to select one of the test pattern data as the test pattern data to be displayed on the liquid crystal display panel.

The pattern change switches may include a first pattern change switch that is turned on every user's operation to generate a first pattern change signal and a second pattern change switch that is turned on every user's operation to generate a second pattern change signal. And a third pattern change switch that is turned on every time a user operates to generate a third pattern change signal.

Each time the first pattern change signal is generated, inspection pattern data selected from the inspection pattern data is shifted in the first direction; When the second pattern change signal is generated, inspection pattern data selected from the inspection pattern data is determined as inspection pattern data designated as a default value; Each time the third pattern change signal is generated, the inspection pattern data selected from the inspection pattern data is shifted in a second direction opposite to the first direction.

The inspection system for the liquid crystal display device is connected to the switch board via a first connector, and is connected to the liquid crystal display device through a second connector, further comprising a connection cable for electrically connecting the switch board and the liquid crystal display device. Equipped; The second connector has a plurality of input terminals for receiving digital video data from the outside; The first to third pattern change signals may be supplied to the liquid crystal display through some of the input terminals.

The switch board is configured to generate option information indicating that the test driving state is performed and to transfer the driving voltage from the power supply to the liquid crystal display.

The timing controller may include: an inspection pattern usage determination unit configured to change a logic level of a usage determination signal according to whether the option information is input; An output path selector including a plurality of logic gate elements whose output is controlled according to a logic level of the use decision signal, and determining an output path of the first to third pattern change signals input to the logic gate elements; ; An inspection pattern storage unit which stores the inspection pattern data; An inspection control signal generator configured to generate a data control signal and a gate control signal for controlling operation timing of the driving circuits by using an oscillation clock generated in response to the input of the option information; And reading the corresponding test pattern data from the test pattern storage unit in response to the pattern change signal from the output path selector, and then, together with the read test pattern data, a data control signal from the test control signal generator. And an inspection pattern & control signal output section for supplying the data to the data driving circuit and for supplying a gate control signal from the inspection control signal generator to the gate driving circuit.

The output path selector may receive the first to third pattern change signals through some of a plurality of input terminals for receiving digital video data from the outside.

The plurality of logic gate elements may include: a first logic gate element configured to supply the first pattern change signal to the test pattern & control signal output in response to the use decision signal of a high logic level; A second logic gate element configured to supply the second pattern change signal to the test pattern & control signal output in response to the use decision signal at a high logic level; And a third logic gate element configured to supply the third pattern change signal to the test pattern & control signal output part in response to the use decision signal of a high logic level.

Each of the first to third logic gate elements may be implemented as a tri-state buffer.

The inspection system for a liquid crystal display according to the present invention embeds the inspection pattern in the liquid crystal display, and then displays the inspection pattern in response to a switch operation signal supplied from the switch board, thereby eliminating a separate signal generator and an interface board. The test pattern can be implemented according to.

Furthermore, the inspection system for the liquid crystal display device according to the present invention uses a switch board that can be used in common for all models irrespective of the model of the liquid crystal display device, and thus, the signal generator and the interface board must be replaced for each model to implement the inspection pattern. Compared to the conventional one, it has a very advantageous effect in terms of time, cost, and management.

Furthermore, the inspection system for the liquid crystal display according to the present invention uses some of the terminals for receiving the existing (normal driving state) digital video data in order to receive the pattern change signals supplied from the switchboard. There is no need to assign an additional input pin (terminal) to the connector and the timing controller of the circuit board, which is economically advantageous in the product application.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 10.

3 and 4, an inspection system for a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal display 100, a connection cable 180, a switch board 200, and a power supply 250. .

As shown in FIG. 4, the liquid crystal display device 100 includes a liquid crystal display panel 110, a timing controller 140, a data driving circuit 12, a gate driving circuit 13, and a common voltage generating circuit 14.

The liquid crystal display panel 110 includes a liquid crystal layer formed between two glass substrates. The liquid crystal display panel includes a plurality of liquid crystal cells Clc arranged in a matrix by a cross structure of a plurality of data lines DL and a plurality of gate lines GL.

Data lines DL, gate lines GL, TFTs, and a storage capacitor Cst are formed on the lower glass substrate of the liquid crystal display panel 110. The liquid crystal cells Clc are connected to the TFT and are driven by an electric field between the pixel electrodes 1 and the common electrode 2. The black matrix, the color filter, and the common electrode 2 are formed on the upper glass substrate of the liquid crystal display panel 110. The common electrode 2 is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, but the in-plane switching (IPS) mode and the fringe field switching (FFS) mode In the same horizontal electric field driving method, the pixel electrode 1 may be formed on the lower glass substrate. A polarizing plate is attached to each of the upper glass substrate and the lower glass substrate of the liquid crystal display panel 110, and an alignment layer for setting a pre-tilt angle of the liquid crystal is formed.

The timing controller 140 operates the data driving circuit 120 using timing signals Hsync, Vsync, DE, and DCLK supplied from a system (not shown) in a normal driving state in which option information is not input. The first data control signal DDC1 for controlling the timing and the first gate control signal GDC1 for controlling the operation timing of the gate driving circuit 130 are generated and the digital video data supplied from the system ( RGB is rearranged to match the resolution of the liquid crystal display panel 110 and supplied to the data driving circuit 120.

On the other hand, the timing controller 140 is configured to control the operation timing of the data driving circuit 120 using an oscillation clock generated by an internal oscillator (not shown) in the test driving state in which option information is input. The second data control signal DDC2 and the second gate control signal GDC2 for controlling the operation timing of the gate driving circuit 130 are generated, and the pattern change signals PAS supplied from the switch board 200 are provided. In response, the test pattern data TPS stored therein is rearranged to match the resolution of the liquid crystal display panel 110 and supplied to the data driving circuit 120.

The timing controller 140 is mounted on the printed circuit board 160 electrically connected to the data driving circuit 120 and the gate driving circuit 130. The printed circuit board 160 includes bus wires for transmitting data RGB / TPS, bus wires for transmitting data control signals DDC1 / DDC2, and bus for transmitting gate control signals GDC1 / GDC2. Bus wirings through which the wirings and the driving voltage VCC are transmitted are formed.

In response to the first data control signal DDC1 from the timing controller 140 in the normal driving state, the data driving circuit 120 converts the input digital video data RGB into an analog gamma compensation voltage with reference to the gamma reference voltage. The analog gamma compensation voltage is converted into a data voltage and supplied to the data lines DL. On the other hand, the data driving circuit 120 responds to the second data control signal DDC1 from the timing controller 140 in the test driving state, and performs analog gamma compensation on the test pattern data TPS input by referring to the gamma reference voltage. A voltage is converted into a voltage, and the analog gamma compensation voltage is supplied as a data voltage to the data lines DL. To this end, the data driving circuit 120 may include a shift register for sampling a clock signal, a register for temporarily storing digital video data RGB or test pattern data TPS, and a digital video in response to a clock signal from the shift register. A latch for storing the data RGB or the test pattern data TPS by one line and simultaneously outputting the stored digital data for one line, and positive / negative under the reference of the gamma reference voltage in response to the digital data value from the latch. Digital / analog converter for selecting polar gamma compensation voltage, multiplexer for selecting data line (DL) to which analog gamma compensation voltage converted by positive / negative gamma voltage is supplied, and multiplexer and data line (DL) A plurality of data drive ICs, including an output buffer connected between them.

The gate driving circuit 130 selects a horizontal line of the liquid crystal display panel 110 to which a data voltage is supplied in response to the first gate control signal GDC1 supplied from the timing controller 140 in the normal driving state. Are sequentially supplied to the gate lines GL. On the other hand, the gate driving circuit 130 selects a horizontal line of the liquid crystal display panel 110 to which the data voltage is supplied in response to the second gate control signal GDC2 supplied from the timing controller 140 in the test driving state. The scan pulse is sequentially supplied to the gate lines GL. To this end, the gate driving circuit 130 is connected to a shift register, a level shifter for converting an output signal of the shift register into a swing width suitable for TFT driving of the liquid crystal cell Clc, and connected between the level shifter and the gate line GL. And a plurality of gate drive ICs each including an output buffer.

The switch board 200 includes a plurality of pattern change switches 201, 202, and 203 to generate pattern change signals PAS to be supplied to the liquid crystal display 100 as shown in FIG. 5. The first pattern change switch 201 is turned on every time a user operates to generate a first pattern change signal Up. The first pattern change signal Up is a signal for selecting any one of the plurality of test pattern data TPSs embedded in the timing controller 140 and is selected whenever the first pattern change signal Up is generated. The test pattern data TPS is shifted in the first direction. The second pattern change switch 202 is turned on every time a user operates to generate a second pattern change signal Reset. The second pattern change signal Reset is a signal for selecting the inspection pattern data TPS specified as a default value among the plurality of inspection pattern data TPSs embedded in the timing controller 140. In addition, the third pattern change signal Down is a signal for selecting any one of the plurality of test pattern data TPSs built in the timing controller 140 and when the third pattern change signal Down is generated. The test pattern data TPS selected for each shift is shifted in the second direction opposite to the first direction.

In addition, the switch board 200 generates option information (Option) for informing the timing controller 140 that the test driving state is connected, and also connects the driving voltage VCC from the power supply 250. Since the switch board 200 can be used in common for all models regardless of the model of the liquid crystal display device 100, it is very advantageous compared to the conventional in terms of management and cost.

The power supply 250 generates a driving voltage VCC necessary for driving the liquid crystal display 100 and the switch board 200.

The connection cable 180 electrically connects the liquid crystal display device 100 and the switch board 200 to convert the pattern change signals PAS, option information, and driving voltage VCC from the switch board 200. The printed circuit board 160 of the liquid crystal display device 100 is supplied. To this end, the connection cable 180 is connected to the switch board 200 through the first connector C1 and to the printed circuit board 160 of the liquid crystal display device 100 through the second connector C2. .

6 shows the timing controller 140 shown in FIG. 4 in detail.

Referring to FIG. 6, the timing controller 140 according to an exemplary embodiment of the present invention may determine whether or not to use a test pattern, an output path selector 142, an test pattern storage unit 143, and a test pattern & control signal. An output unit 144, an inspection control signal generator 145, and an external data & control signal output unit 146 are provided.

The test pattern use decision determiner 141 changes the logic level of the use decision signal SEL according to whether option information Option from the switch board 200 is input. The inspection pattern use determination unit 141 generates the use determination signal SEL at the first logic level HIGH in response to the input of the option information Option in the inspection driving state, and the option information in the normal driving state. The use decision signal SEL is generated at the second logic level LOW in response to no input of (Option).

As shown in FIG. 7, the output path selector 142 includes a plurality of r terminals r0 to r5 to which R data is input, a plurality of g terminals g0 to g5 to which G data is input, and B in a normal driving state. And a plurality of b terminals b0 to b5 to which data are input. The output path selector 142 receives the pattern change signals PAS using three terminals of the plurality of terminals r0 to b5 in the test driving state. For example, the r terminal r0 is used for the input of the first pattern change signal Up, the g terminal g0 is used for the input of the second pattern change signal Reset, and the b terminal b0 is the third It can be used for input of the pattern change signal Down. Here, the pattern change signals PAS are input to corresponding terminals through bus lines formed on the connection cable 180 and the printed circuit board 160. In this way, when some of the input terminals to which the digital video data RGB is supplied are used for input of the pattern change signals PAS, in order to input the pattern change signals PAS to the output path selector 142. There is no need to add additional input terminals. In addition, the second connector C2 of the printed circuit board 160 also eliminates the need for additional pin assignment.

The configuration of the output path selector 142 will now be described with reference to FIGS. 8A to 8C. The output path selector 142 includes first to sixth logic gate elements 142a to 142f whose outputs are controlled according to the logic level of the use decision signal SEL. The output path of the input data in the output path and the normal driving state is different from each other.

In the test driving state, the first logic gate element 142a is controlled by the use decision signal SEL of the first logic level HIGH to check the first pattern change signal Up from the r terminal r0. & Outputs to control signal output unit 144. The third logic gate element 142c is controlled by the use-decision signal SEL of the first logic level HIGH to check the second pattern change signal Reset from the g terminal g0 to the inspection pattern & control signal output unit. Output to (144). The fifth logic gate element 142e is controlled by the use decision signal SEL of the first logic level HIGH to check the third pattern change signal Down from the b terminal b0 for the inspection pattern & control signal output unit. Output to (144). Here, the first, third, and fifth logic gate elements 142a, 142c, and 142e are turned on by a state determination signal SEL of the first logic level HIGH. It can be implemented as.

In contrast, in the normal driving state, the second logic gate element 142b is controlled by the use decision signal SEL of the second logic level LOW to control the R0 data from the r terminal r0 to the external data & second control. Output to the signal output unit 146. The fourth logic gate element 142d is controlled by the use decision signal SEL of the second logic level LOW to transfer the G0 data from the g terminal g0 to the external data & second control signal output unit 146. Output The sixth logic gate element 142f is controlled by the use decision signal SEL of the second logic level LOW to transfer the B0 data from the b terminal b0 to the external data & second control signal output unit 146. Output Here, the second, fourth, and sixth logic gate elements 142b, 142d, and 142f are turned on by a state determination signal SEL of the second logic level LOW. It can be implemented as.

The inspection pattern storage unit 143 stores a plurality of inspection pattern data TPSs used in the inspection process. Here, the inspection pattern data TPSs include the first inspection pattern data Red, the second inspection pattern data Green, the third inspection pattern data Blue, the fourth inspection pattern data White, and the first inspection pattern data Red as shown in FIG. 5 may include test pattern data Black, 6th test pattern data 16 Gray, and 7th test pattern data 32 Gray. The test pattern storage unit 143 may include a nonvolatile memory capable of updating and erasing data, for example, an electrically erasable programmable read only memory (EEPROM) and / or an extended display identification data ROM (EDID ROM). The stored test pattern data TPS may be ganged by an electrical signal A1 applied from the outside through a user interface (not shown).

The inspection control signal generator 145 uses the oscillation clock generated by an internal oscillator (not shown) in response to the input of the option information Option, and the second data control signal DDC2 and the second gate control signal. Generate (GDC2).

The inspection pattern & control signal output unit 144 reads the inspection pattern data TPS from the inspection pattern storage unit 143 in response to the pattern change signal PAS from the output path selection unit 142. The second data control signal DDC2 from the inspection control signal generator 145 is supplied to the data driving circuit 120 together with the read inspection pattern data TPS. The test pattern & control signal output unit 144 supplies the second gate control signal GDC2 from the test control signal generator 145 to the gate driving circuit 130. The process of reading the test pattern data TPS by the test pattern & control signal output unit 144 according to the pattern change signal PAS will be described below. The inspection pattern & control signal output unit 144 reads the first inspection pattern data Red designated as a default value while the use determination signal SEL is maintained at the first logic level HIGH as shown in FIG. 9. . When the first pattern change signal Up is input in this state, the test pattern & control signal output unit 144 reads second test pattern data Green adjacent in the first direction from the first test pattern data Red. do. In this manner, each time the first pattern change signal Up is input, the test pattern & control signal output unit 144 reads test pattern data one by one in the first direction. On the other hand, when the third pattern change signal Down is input while the inspection pattern data is read one by one in the first direction, the inspection pattern data adjacent in the second direction is read from the immediately preceding inspection pattern data. In this manner, each time the third pattern change signal Down is input, the test pattern & control signal output unit 144 reads out the test pattern data one by one in the second direction. When the second pattern change signal Reset is input while the inspection pattern data is read one by one in the first direction or the second direction, the inspection pattern & control signal output unit 144 sets the first inspection pattern as a default value. Read the data Red. Accordingly, the order of the inspection pattern data read out according to the logic states of the pattern change signals Up, Reset, and Down in FIG. 9 is as shown in FIG. 10. Data (Green)-> 3rd test pattern data (Blue)-> 4th test pattern data (White)-> 5th test pattern data (Black)-> 6th test pattern data (16 Gray)- -> 7th test pattern data (32 Gray)-> 6th test pattern data (16 Gray)-> 5th test pattern data (Black)-> 4th test pattern data (White)-> 1st The inspection pattern data Red is determined.

The external data & control signal output unit 146 rearranges the digital video data RGB supplied from the system via the output path selector 142 to match the resolution of the liquid crystal display panel 110. To feed. In addition, the external data & control signal output unit 146 receives the first data control signal DDC1 and the first gate control signal GDC1 using timing signals Hsync, Vsync, DE, and DCLK supplied from the system. Is generated and supplied to the data driving circuit 120 and the gate driving circuit 130, respectively.

As described above, the inspection system for a liquid crystal display according to the present invention incorporates the inspection pattern in the liquid crystal display and then displays the inspection pattern in response to the switch operation signal supplied from the switchboard, thereby providing a separate signal generator and interface. Without the board, you can implement a test pattern that matches your intentions.

Furthermore, the inspection system for the liquid crystal display device according to the present invention uses a switch board that can be used in common for all models irrespective of the model of the liquid crystal display device, and thus, the signal generator and the interface board must be replaced for each model to implement the inspection pattern. Compared to the conventional one, it has a very advantageous effect in terms of time, cost, and management.

Furthermore, the inspection system for the liquid crystal display according to the present invention uses some of the terminals for receiving the existing (normal driving state) digital video data in order to receive the pattern change signals supplied from the switchboard. There is no need to assign an additional input pin (terminal) to the connector and the timing controller of the circuit board, which is economically advantageous in the product application.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a block diagram showing a conventional inspection system for a liquid crystal display device.

2 is a diagram illustrating an example of a test pattern displayed on a liquid crystal display;

3 is a block diagram illustrating an inspection system for a liquid crystal display according to an exemplary embodiment of the present invention.

4 is a block diagram illustrating in detail a liquid crystal display of FIG. 3.

5 is a view showing in detail the switchboard of FIG.

FIG. 6 is a detailed block diagram of the timing controller of FIG. 4. FIG.

FIG. 7 is a diagram illustrating input terminals of an output path selector of FIG. 6; FIG.

8A to 8C are views illustrating an internal configuration of the output path selector of FIG. 6.

9 and 10 are views illustrating an example of test pattern data selected according to a logic level of a pattern change signal.

Description of the Related Art

100 liquid crystal display device 110 liquid crystal display panel

120: data driving circuit 130: gate driving circuit

140: timing controller 141: determining whether to use the test pattern

142: output path selection unit 143: test pattern storage unit

144: inspection pattern & control signal output unit 145: inspection control signal generator

146: external data & control signal output unit 180: connection cable

200: switch board 201,202,203: pattern change switch

250 power supply

Claims (9)

A liquid crystal display panel having intersections of gate lines and data lines and having liquid crystal cells formed at respective intersection regions thereof, a data driving circuit for driving the data lines, a gate driving circuit for driving the gate lines, and an operation timing of the driving circuits. A liquid crystal display device having a timing controller for controlling the control unit and embedding a plurality of test pattern data to be displayed on the liquid crystal display panel; A switch board for supplying a pattern change signal to the liquid crystal display device including a plurality of pattern change switches; And A power supply for generating a driving voltage necessary for the operation of the liquid crystal display and the switchboard; The pattern change signal is generated by turning on any one of the pattern change switches to select any one of the inspection pattern data as the inspection pattern data to be displayed on the liquid crystal display panel. Inspection system. The method of claim 1, The switch for pattern change, A first pattern change switch that is turned on every user's operation to generate a first pattern change signal, a second pattern change switch that is turned on every user's operation to generate a second pattern change signal, and a turn at every user's operation And a third pattern change switch that is turned on to generate a third pattern change signal. The method of claim 2, Each time the first pattern change signal is generated, inspection pattern data selected from the inspection pattern data is shifted in the first direction; When the second pattern change signal is generated, inspection pattern data selected from the inspection pattern data is determined as inspection pattern data designated as a default value; And each time the third pattern change signal is generated, inspection pattern data selected from the inspection pattern data is shifted in a second direction opposite to the first direction. The method of claim 2, A connection cable connected to the switch board through a first connector and connected to the liquid crystal display device through a second connector, and electrically connecting the switch board and the liquid crystal display device; The second connector has a plurality of input terminals for receiving digital video data from the outside; And the first to third pattern change signals are supplied to the liquid crystal display through some of the input terminals. The method of claim 4, wherein And the switch board generates option information indicating that the test drive is in a test driving state, and transfers a driving voltage from the power supply to the liquid crystal display. The method of claim 5, The timing controller, An inspection pattern usage determination unit for varying the logic level of the usage determination signal according to whether the option information is input; An output path selector including a plurality of logic gate elements whose output is controlled according to a logic level of the use determination signal, and determining an output path of the first to third pattern change signals input to the logic gate elements; ; An inspection pattern storage unit which stores the inspection pattern data; An inspection control signal generator configured to generate a data control signal and a gate control signal for controlling operation timing of the driving circuits by using an oscillation clock generated in response to the input of the option information; And In response to the pattern change signal from the output path selection unit, corresponding inspection pattern data is read from the inspection pattern storage unit, and the data control signal from the inspection control signal generation unit is read together with the read inspection pattern data. And an inspection pattern & control signal output section for supplying the data driving circuit and supplying a gate control signal from the inspection control signal generator to the gate driving circuit. The method of claim 5, And the output path selector receives the first to third pattern change signals through some of a plurality of input terminals for receiving digital video data from the outside. The method of claim 7, wherein The plurality of logic gate devices, A first logic gate element configured to supply the first pattern change signal to the test pattern & control signal output in response to the use decision signal of a high logic level; A second logic gate element configured to supply the second pattern change signal to the test pattern & control signal output in response to the use decision signal at a high logic level; And And a third logic gate element for supplying the third pattern change signal to the inspection pattern & control signal output in response to the use decision signal at a high logic level. The method of claim 8, And each of the first to third logic gate elements is implemented as a tri-state buffer.

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