KR20100030024A - Stack semiconductor package with through silicon via and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A stack semiconductor package with a through-silicon via and a method for manufacturing the same are provided to protect a semiconductor chip from cracking using a buffer layer which is composed of an oxide layer. CONSTITUTION: A via-hole(103) is formed by etching the pad region of a silicon wafer(101). A bulb pattern is formed by etching the lower part of the via-hole. A buffer layer(104) is formed on the sidewall of the via-hole and the bulb pattern. A through-silicon via(200) including a through part(200A) and a convex part(200B) is formed. The through part is buried in the via-hole and the convex part is buried in the bulb pattern. The rear side of the silicon wafer is removed in order to expose the convex part. The divided semiconductor chips(110) of the silicon wafer are stacked through the through-silicon via.

Description

Stacked semiconductor package using through silicon via and manufacturing method thereof {STACK SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIA AND METHOD FOR MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device package, and more particularly, to a laminated semiconductor package using a through silicon via and a manufacturing method thereof.

Packaging technologies for semiconductor integrated devices have been continuously developed in accordance with the demand for miniaturization and high capacity. Recently, various technologies for multilayer semiconductor packages that can satisfy the miniaturization and high capacity and the mounting efficiency have been developed.

The stacked semiconductor package may be manufactured by stacking individual semiconductor chips, packaging the stacked semiconductor chips at a time, and stacking the packaged individual semiconductor packages, and the individual semiconductor chips of the stacked semiconductor package may be formed of metal wires or It is electrically connected through a through silicon via (TSV).

However, the conventional laminated semiconductor package using the metal wire is slow because the electrical signal exchange is made through the metal wire, a large number of wires are used to cause electrical characteristics deterioration. In addition, an additional area is required in the substrate to form a metal wire, thereby increasing the size of the package, and a height of the package is increased because a gap Gap for wire bonding between semiconductor chips is required.

Thus, recently, a multilayer semiconductor package using through silicon vias (TSVs) has been proposed. The stacked semiconductor package generally forms a via hole penetrating the semiconductor chip in the semiconductor chip, and forms a through electrode called a through silicon via (TSV) by filling a conductive material in the penetrated via hole. In addition, the semiconductor device is implemented by electrically connecting the upper semiconductor chip and the lower semiconductor chip through the through electrode.

1A to 1C illustrate a method of manufacturing a laminated semiconductor package using through silicon vias according to the prior art.

As shown in FIG. 1A, after forming the passivation layer 12 opening the pad region on the silicon wafer 11, the pad region is etched using a via mask to form a via hole. 13).

Subsequently, a through silicon via (TSV) 14 is formed by filling a metal film in the via hole 13.

As shown in FIG. 1B, the backside of the wafer 11 is back ground and after etched (see reference numeral 15) to expose the through silicon vias 14.

As shown in FIG. 1C, the wafer 11A is sawed to separate the individual semiconductor chips C1 and C2, and then the at least two semiconductor chips C1 and C2 are separated from the through silicon vias 14. It is laminated vertically using.

However, the prior art has a problem as follows.

First, as the through-silicon via 14 used to connect the stacked semiconductor chips, a metal film is used to reduce the resistance, and there is a problem that occurs due to a different coefficient of thermal expansion between the metal film and the wafer. . This difference in thermal expansion coefficient causes cracks (see reference numeral 'A') at the interface between the metal film and the wafer in the thermal cycle test, which is a method of reliability evaluation to guarantee the service life of a unit device. Let's go.

In addition, due to the thermal process used when integrating two or more multi-layer stacked packages, the characteristics of the unit device are deteriorated.

Lastly, compared to the existing metal wires, although the structure has the characteristics of stacking a plurality of semiconductor chips, the interface resistance increases (see reference numeral 'B') has a disadvantage of causing a speed delay (speed delay).

The present invention has been proposed to solve the above-mentioned problems of the prior art, and an object thereof is to provide a laminated semiconductor package and a method of manufacturing the same, which can prevent cracking due to a difference in thermal windowing coefficient.

In addition, another object of the present invention is to provide a laminated semiconductor package and a method of manufacturing the same which can improve the speed by lowering the interfacial resistance between the stacked semiconductor chips.

According to another aspect of the present invention, there is provided a method of manufacturing a multilayer semiconductor package, the method comprising: forming a via hole by etching a pad region of a silicon wafer; Etching below the via hole to form a bulb pattern; Forming a buffer layer on sidewalls of the via hole and the bulb pattern; Forming a through silicon via including a through part embedded in the via hole and a convex part embedded in the bulb pattern; Removing a back surface of the silicon wafer to expose the convex portion; Separating the silicon wafer at the semiconductor chip level; And stacking the separated semiconductor chips through the through silicon vias.

In the multilayer semiconductor package of the present invention, in the multilayer package in which a plurality of semiconductor chips are stacked through through silicon vias, the through silicon vias are connected to the through parts penetrating through the semiconductor chips and the through parts. It characterized in that it comprises a convex portion protruding out of the bottom of the. The upper surface of the penetrating portion has a recessed rounded surface, and further includes a buffer film surrounding the sidewall of the penetrating portion, the buffer film including an oxide film.

The present invention described above can prevent cracks from the difference in coefficient of thermal expansion when applied to the through-silicon via structure by using a buffer film, and an oxide buffer film is used as a buffer film to protect cracks in semiconductor chips according to temperature changes. It can be effective.

In addition, the present invention has an effect of improving contact resistance when stacking a plurality of semiconductor chips by using a convex structure using a bulb pattern when forming through silicon vias. This has the effect of improving the speed delay.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

2 is a diagram illustrating a laminated semiconductor package according to a first embodiment of the present invention.

Referring to FIG. 2, two semiconductor chips 110 are vertically stacked, and two semiconductor chips 110 are electrically connected through the through silicon vias 200.

Looking at the semiconductor chip 110 in detail, the passivation layer 102 exposing the pad region is formed on the silicon wafer 101, and the via hole 103 penetrating the pad region of the silicon wafer 101 is provided.

The through-silicon vias 200 are filled in the via holes 103, and the through-silicon vias 200 are formed of a metal film. In particular, the through-silicon via 200 consists of a through part 200A and a convex part 200B. The through part 200A is a form in which the via hole 103 is buried, and the convex part 200B protrudes outward. Form. Therefore, the convex portion 200B of the upper semiconductor chip 110 contacts the surface of the penetrating portion 200A of the lower semiconductor chip 110. The surface of the penetrating portion 200A is recessed to have a rounded surface. Accordingly, since the convex portion 200B is well contacted, the contact area is increased, and thus the contact resistance can be improved.

The buffer film 104 is provided on the sidewall of the via hole 103. The buffer film 104 may have a structure that surrounds the sidewall of the through part 200A embedded in the via hole 103 and also surrounds the sidewall of the convex part 200B. The buffer film 104 is used as a buffer film between the through-silicon vias 200 and the silicon wafer 101 to prevent cracks due to thermal expansion coefficient differences. In addition, the buffer film 104 also serves to prevent cracking of the semiconductor chip due to temperature changes.

3A to 3G illustrate a method of manufacturing a multilayer semiconductor package according to a second embodiment of the present invention.

As shown in FIG. 3A, a protective film 22 is formed on the silicon wafer 21. In this case, the protective film may include a PIQ (Polyimide Isoindro Quindzoline) or an insulating film, and preferably the PIQ and the oxide film may be stacked. Here, the oxide film serves as a buffer for absorbing and mitigating thermal stress and an electrically insulating function.

Subsequently, the passivation layer 22 is etched by using a via mask 23 using a photoresist layer to expose the pad region, and then the via region 24 is formed by anisotropically etching the pad region. In this case, the depth of the via hole 24 may be adjusted by selectively etching considering the target during the subsequent back grinding.

As shown in FIG. 3B, after removing the via mask, a bulb pattern 25 is formed by isotropically etching the bottom surface of the via hole 24 using the protective layer 22 as an etch barrier. In this case, the bulb pattern 25 is a round pattern having a larger line width than the bottom line width of the via hole 24 and having a predetermined curvature. This large line width can be obtained by isotropic etching.

As described above, when the bulb pattern 25 is formed under the via hole 24, the contact resistance of the through silicon via may be increased to improve contact resistance.

Isotropic etching for forming the bulb pattern 25 is performed in a plasma coupled plasma (TCP), inductively coupled plasma (ICP), microwave down stream (MDS), electro cyclone resonance (ECR), and helical plasma type. Etching can be performed.

As shown in FIG. 3C, a buffer layer 26 having a spacer shape is formed on sidewalls of the via hole 24 and the bulb pattern 25 in order to prevent cracking due to a difference in thermal expansion coefficient. Here, the buffer layer 26 may be formed by depositing an oxide layer on the entire surface and blanket etching.

As shown in FIG. 3D, a metal film 27 is formed on the entire surface of the via hole 24 and the bulb pattern 25 to be embedded. The metal film 27 is a connection material between semiconductor chips stacked. Preferably, the metal film 27 includes an aluminum film Al, and a barrier film may be formed in advance as a barrier between the silicon wafer 21 and the buffer film 26 before the metal film 27 is formed. The barrier film may sequentially form titanium (Ti) and titanium nitride film (TiN).

As shown in FIG. 3E, a blanket etch back is performed to etch the metal film. In this case, the blanket etch bag proceeds until the surface of the protective film 22 is exposed, and the surface of the metal film may be recessed to be lower than the surface of the silicon wafer 21 due to the characteristics of the blanket etch bag.

After the blanket etch back as described above, the through-silicon via 100 is formed in the via hole and the bulb pattern, and the through-silicon via 100 is embedded in the through-hole 27A and the bulb pattern 25 embedded in the via hole 24. It consists of the convex part 27B. The through silicon via 100 has a top surface recessed downward, and the recessed top surface has a wider convex portion 27B of the through silicon via 100 when a plurality of semiconductor chips are stacked. The contact resistance is improved by making contact with the contact area.

As shown in FIG. 3F, back grinding and further etching are performed on the silicon wafer 21 (see reference numeral 28).

By the bottom polishing and additional etching, the bottom surface of the silicon wafer is thinned as shown by reference numeral 21A, thereby exposing the convex portion 27B embedded in the bulb pattern.

As shown in FIG. 3G, the silicon wafer 21A is separated into individual semiconductor chips C11 and C12 by a sawing method at the semiconductor chip level, and then at least two or more semiconductor chips C11 and C12. It is stacked vertically using the through-silicon via (100). Another method of stacking semiconductor chips may be sawing at the semiconductor chip level at once, after stacking a plurality of silicon wafers having through silicon vias formed thereon.

According to the above-described embodiment, an oxide is used as the buffer layer 26 to prevent cracks caused by the difference in thermal expansion coefficient, and the side surface is etched in the form of a spacer to increase the interface resistance. To form. In this case, an interface between the metal film (through silicon via), the oxide film (buffer film), and the silicon wafer is formed to prevent cracking.

In addition, the through-silicon via is formed in the form of a bulb to reduce contact resistance, and when the blanket is etched during the etching of the metal film, the through silicon via is formed into a naturally recessed surface structure and is recessed with the convex portion. As the surfaces come into contact, the contact area can be increased, a stable process can be achieved, and the speed delay can be improved.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1C illustrate a method of manufacturing a laminated semiconductor package using through silicon vias according to the prior art.

2 is a diagram illustrating a laminated semiconductor package according to a first embodiment of the present invention.

3A to 3G illustrate a method of manufacturing a laminated semiconductor package according to a second embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

101: silicon wafer 102: protective film

103: via hole 104: buffer film

110: semiconductor chip 200: through silicon via

200A: penetrating portion 200B: convex portion

Claims (11)

Etching the pad region of the silicon wafer to form a via hole; Etching below the via hole to form a bulb pattern; Forming a buffer layer on sidewalls of the via hole and the bulb pattern; Forming a through silicon via including a through part embedded in the via hole and a convex part embedded in the bulb pattern; Removing a back surface of the silicon wafer to expose the convex portion; Separating the silicon wafer at the semiconductor chip level; And Stacking the separated semiconductor chips through the through silicon via Laminated semiconductor package manufacturing method comprising a. The method of claim 1, The buffer layer is a method of manufacturing a laminated semiconductor package formed by blanket etching after the deposition of the oxide film (Blanket etch). The method of claim 1, Forming the through silicon vias, Depositing a metal film on an entire surface of the wafer to fill the via hole and the bulb pattern; And Blanket etching the metal film Laminated semiconductor package manufacturing method comprising a. The method of claim 3, A method of manufacturing a laminated semiconductor package, wherein a barrier film is formed in advance before the metal film is deposited. The method of claim 4, wherein The barrier film is a laminated semiconductor package manufacturing method formed by laminating a titanium film and a titanium nitride film. The method of claim 1, Removing the back side of the wafer, A method of manufacturing a laminated semiconductor package, which proceeds in the order of back grinding and further etching. In a stacked package in which a plurality of semiconductor chips are stacked through through silicon vias, The through silicon vias are penetrating portions penetrating the semiconductor chips and convex portions projecting out of the bottom surface of the semiconductor chip while being connected to the penetrating portions. Laminated semiconductor package comprising a. The method of claim 7, wherein And the upper surface of the through portion has a recessed rounded surface. The method of claim 7, wherein And a buffer film surrounding the sidewalls of the through part. The method of claim 9, The buffer layer is a laminated semiconductor package comprising an oxide film. The method according to any one of claims 7 to 10, The through via is a laminated semiconductor package formed of a metal film.

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