KR20100027784A - Erasing method and soft program method of non volatile memory device - Google Patents

Abstract

PURPOSE: An erase and a soft-programming method of a non-volatile memory device are provided to prevent the cell current of a dummy cell from reducing without performing a soft-program operation to the dummy cell. CONSTITUTION: An erase operation is performed to a dummy cell and memory cells(310). An erase verification operation is performed to the cells(320). A soft-program operation is performed to the memory cells(330). The soft-program verification operation is performed to the memory cells(340). The dummy cell includes a drain side dummy cell connected between the memory cell and a drain selection transistor and a source side dummy cell connected between the memory cell and a source selection transistor.

Description

Erasing method and soft program method of non volatile memory device

The present invention relates to an erase method and a soft program method of a nonvolatile memory device.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals.

The nonvolatile memory cell is an electric program / eraseable device that performs program and erase operations by changing a threshold voltage of a cell while electrons are moved by a strong electric field applied to a thin oxide film. In this case, an operation of filling electrons into the floating gate is a program operation, and an operation of discharging electrons filled in the floating gate is called an erase operation.

The nonvolatile memory device typically includes a memory cell array having cells in which data is stored in a matrix form, and a page buffer for writing a memory to a specific cell of the memory cell array or reading a memory stored in the specific cell. . The page buffer may include a pair of bit lines connected to a specific memory cell, a register for temporarily storing data to be written to the memory cell array, or a register for reading and temporarily storing data of a specific cell from the memory cell array, a voltage of a specific bit line or a specific register. It includes a sensing node for sensing a level, a bit line selection unit for controlling the connection of the specific bit line and the sensing node.

In the memory cell array structure of such a nonvolatile memory device, a cell array structure in which dummy cells are added is recently used. In other words, the memory cell is added to the outside of the source memory cell and the outside of the drain memory cell to be used as a dummy cell. This is to compensate for the occurrence of program disturb in the outermost memory cell and to be vulnerable to cycling characteristics and retention characteristics. According to the operation of the nonvolatile memory device having the cell array structure, the cell current decreases due to the dummy cell as the number of programs / erases increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide an erase method and a soft program method of a nonvolatile memory device that do not perform a soft program operation on a dummy cell.

The erase method of the nonvolatile memory device of the present invention for solving the above-described problems, performing an erase operation on the dummy cell and the memory cells, performing an erase verification operation on the cells, Performing a soft program operation on the memory cells and performing a soft program verify operation on the memory cells.

According to the aforementioned problem solving means of the present invention, the soft program is not performed on the dummy cell, so that the cell current flowing through the cell string by the dummy cell is not reduced. As a result, the over program occurring in the memory cell can be prevented. As the number of programs / erases increases, the problem becomes more severe and can be overcome by the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

1 is a view showing the overall configuration of a nonvolatile memory device to which the present invention is applied.

The nonvolatile memory device 100 includes a memory cell array 102, a page buffer 108, an X / Y-decoder 104 and 106, a high voltage generator 110, a command interface logic unit 112, and a command register ( 114, an address register / counter 116, a data register 118, and an IO buffer unit 120.

An operation of the nonvolatile memory device will be described.

First, when the chip enable signal / CE is disabled and the write enable signal / WE is toggled with respect to the command interface logic unit 112, the command interface logic unit 112 may respond in response thereto. The command signal received through the IO buffer unit 110 and the command register 114 is received, and a program command, an erase command, or a read command is generated according to the command. In this case, the command signal includes a page program setup code for determining an operation mode of the nonvolatile memory device. Meanwhile, the operation state signal / R / B output from the command interface logic unit 112 is disabled for a predetermined time, and an external memory controller (not shown) transmits the operation state signal / R / B. Receives and recognizes that the nonvolatile memory device is in an operating state such as program / erase / read. That is, during the time when the operation state signal / R / B is disabled, program / erase / read of one page of the memory cell array is executed.

In addition, the address register / counter 116 receives an address signal received through the IO buffer unit 120 and generates a row address signal and a column address signal. The address signal corresponds to one of pages included in one of the memory cells.

The data register 118 temporarily stores various data received through the IO buffer unit 120 and transfers the data to the Y-decoder 106.

The high voltage generator 110 generates bias voltages in response to the program command, erase command or read command and supplies them to the page buffer 108, the X-decoder 104, and the like. In the present invention, the control voltage is not applied to the dummy cell during the soft program operation after performing the erase operation.

The X-decoder 104 supplies the bias voltages supplied from the high voltage generator 110 to the memory cell array 102 in one of the blocks of the memory cell array in response to the row address signal.

The Y-decoder 106 supplies a data signal to bit lines (not shown) shared by the blocks of the memory cell array through the page buffer in response to the column address signal.

The page buffer 108 latches a data signal received through the IO buffer unit 110 and the Y-decoder 106 to bit lines (not shown) shared by the blocks of the memory cell array. Output

The memory cell array 102 according to the present invention has a configuration including a general memory cell and a dummy cell. With reference to the drawings will be described in detail.

2 is a detailed diagram illustrating a memory cell array of a nonvolatile memory device according to the present invention.

The nonvolatile memory device 200 includes a memory cell array 210 and a page buffer 220.

The memory cell array 210 includes a cell string 215 including memory cells MC0 to MCn for storing data, drain select transistors 211 and DST for selectively connecting the memory cells to a bit line, and the memory. Source select transistors 219 and SST for selectively connecting cells and the common source line CSL, drain side dummy cells 213 and DDC connected between the memory cell MCn and the drain select transistor 211, and Source side dummy cells 217 and SDC connected between the memory cell MC0 and the source select transistor 219 are included. The memory cell array 210 becomes one unit memory cell block. The memory cells MC0 to MCn are programmed, read, and erased according to various high voltages applied through word lines WL <0: n>. Operation and so on. The drain select transistors DST selectively connect the bit line and the drain side dummy cell 213 (DDC) according to a voltage applied through the drain select line DSL. In addition, the source select transistors SST selectively connect the common source line CSL and the source side dummy cells 217 and SDC according to a voltage applied through the source select line SSL.

 The drain side dummy cells 213 and DDC and the source side dummy cells 217 and SDC are nonvolatile memory cells having the same characteristics as those of the memory cells MC0 to MCn. That is, a program operation, a read operation, and an erase operation may be performed while having the same characteristics as that of the memory cell. In the present invention, the program operation is performed on the dummy cells during the program operation of the memory cells, so that the read voltages of the memory cells are changed based on the charge retention state of the dummy cells. Therefore, the dummy cells 213 and 217 should be configured to have the same characteristics as the memory cells MC0 to MCn. The drain-side dummy cell 213 (DDC) is connected to the drain-side dummy word line DSWL by the drain-side dummy cell 219 and SDC by the source-side dummy word line SSWL. An erase operation or the like is performed.

According to an exemplary embodiment, the memory cell array may be configured to include only the source-side dummy cell or only the drain-side dummy cell.

The dummy cell is not programmed, but the erase operation is performed to prevent disturb. That is, the erase operation is performed on the dummy cell during the erase operation of the general memory cell.

Meanwhile, in order to sufficiently secure read margins according to the application of the MLC program method, it is necessary to minimize the width of each state distribution. To this end, the soft program operation is performed on the cells on which the erase operation has been performed to narrow the distribution of the erase cells. The soft program operation is performed in a similar manner to the general program operation, but the threshold voltage distribution is narrowed by increasing the threshold voltage of the cells in the erased state but lowering it to less than 0V.

However, when a soft program operation is sequentially performed from a memory cell adjacent to a source select transistor to a memory cell adjacent to a drain select transistor, a back pattern dependency (BPD) effect of increasing the threshold voltage of a cell according to channel resistance, FG coupling, and program Disturbing lights will appear. As a result, the read margins of the erase cells are reduced. In particular, when the number of times of program / erase is increased, the BPD and the program disturb are more generated, causing a fail phenomenon in which the threshold voltage of the erase cell is increased to 0 V or more. This phenomenon is particularly likely to occur in the outermost memory cells such as memory cells adjacent to the source select transistor or memory cells adjacent to the drain select transistor. In the memory cell array structure to which the dummy cell structure is applied, the threshold voltage of the dummy cell in the erase state is increased to 0V or more. In this case, the cell current of the cell string including the dummy cell is reduced, resulting in an over program phenomenon in which the threshold voltages of the cells in the cell string are increased as a whole. In order to prevent such a phenomenon, the present invention proposes a method of performing a soft program operation only for a memory cell and not for a dummy cell.

3 is a flowchart illustrating a method of erasing a nonvolatile memory device according to an embodiment of the present invention.

First, an erase operation is performed on the dummy cell and the memory cells (step 310).

The erase operation is performed in units of a memory cell block shown in FIG. 2. That is, erase operations are simultaneously performed on the memory cells MC0 to MCn and the dummy cells DDC and SDC included in the memory cell block 210. A voltage of 0V may be applied to the word lines of the cells, and a high voltage of approximately 20V may be applied to the wells. Alternatively, the operation may be performed according to an incremental step pulse erase (ISPE) erase operation.

Next, a verification operation is performed on the erase operation (step 320).

The verification operation is performed according to a normal erase verification operation, and the verification targets are the memory cells MC0 to MCn and the dummy cells DDC and SDC. If it is determined that all cells have been erased, a soft program operation is performed.

Next, a soft program operation is performed on the memory cells (step 330).

The soft program operation is performed by applying a program voltage to the word lines of the memory cells MC0 to MCn. At this time, a voltage of 0V is applied to the word lines of the dummy cells so that the soft program operation is not performed. The soft program operation is performed according to a typical incremental step pulse program (ISPP) operation. However, since it is not a normal program operation, the level of the program voltage pulse applied to each word line is lower than that of the general program. Soft program operation is performed according to a starting voltage of approximately 10-12V and a step voltage of 0.1-0.3V.

As such, since the soft program operation is blocked on the dummy cells, the threshold voltages of the dummy cells do not increase and maintain the erase state.

Next, a verification operation is performed on the soft program operation (step 340).

The verification operation is performed according to a normal soft program verification operation, and the verification targets are the memory cells MC0 to MCn. When the verify operation is performed on the entire cell string, the verify operation is performed by applying a voltage of approximately 0 V to the word lines of the memory cells, and the verify operation is performed by applying a high level voltage to the word lines of the dummy cells. Do not It is assumed that the verify operation is completed at the time when the cell programmed above 0 V is generated first.

1 is a view showing the overall configuration of a nonvolatile memory device to which the present invention is applied.

2 is a detailed diagram illustrating a memory cell array of a nonvolatile memory device according to the present invention.

3 is a flowchart illustrating a method of erasing a nonvolatile memory device according to an embodiment of the present invention.

Claims (4)

Performing an erase operation on the dummy cell and the memory cells; Performing an erase verify operation on the cells; Performing a soft program operation on the memory cells; And performing a soft program verify operation on the memory cells. 2. The dummy cell of claim 1, wherein the dummy cell comprises: a drain side dummy cell connected between the memory cell and the drain select transistor; And a source side dummy cell connected between the memory cell and the source select transistor. The method of claim 1, wherein the performing of the soft program operation comprises performing an incremental step pulse program (ISPP) programming method according to a start voltage of 10 to 12V and a step voltage of 0.1 to 1V. Method of erasing nonvolatile memory device. The method of claim 1, wherein the performing of the soft program verify operation includes applying a low level voltage to a word line of memory cells to perform a verify operation, and applying a high level voltage to a word line of dummy cells. Method of erasing nonvolatile memory device, characterized in that the operation is blocked.

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