KR20100011799A - Method of manufacturing semiconductor device - Google Patents
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- KR20100011799A KR20100011799A KR1020080073169A KR20080073169A KR20100011799A KR 20100011799 A KR20100011799 A KR 20100011799A KR 1020080073169 A KR1020080073169 A KR 1020080073169A KR 20080073169 A KR20080073169 A KR 20080073169A KR 20100011799 A KR20100011799 A KR 20100011799A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 54
- 239000002184 metal Substances 0.000 claims abstract description 54
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 38
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 38
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000001590 oxidative effect Effects 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 38
- 230000004888 barrier function Effects 0.000 claims description 26
- 239000010949 copper Substances 0.000 claims description 22
- 229910052802 copper Inorganic materials 0.000 claims description 21
- 239000011229 interlayer Substances 0.000 claims description 16
- 239000010410 layer Substances 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 9
- 238000009832 plasma treatment Methods 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 7
- 238000000992 sputter etching Methods 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 3
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 17
- 239000005751 Copper oxide Substances 0.000 description 17
- 229910000431 copper oxide Inorganic materials 0.000 description 17
- JPVYNHNXODAKFH-UHFFFAOYSA-N Cu2+ Chemical compound [Cu+2] JPVYNHNXODAKFH-UHFFFAOYSA-N 0.000 description 4
- 229910001431 copper ion Inorganic materials 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게, 금속배선 간의 브리지를 방지할 수 있는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing bridges between metal wirings.
일반적으로, 반도체 소자에는 소자와 소자 간, 또는, 배선과 배선 간을 전기적으로 연결하기 위해 금속배선이 형성되며, 상부 금속배선과 하부 금속배선 간의 연결을 위해 콘택 플러그가 형성된다.In general, a metal element is formed in the semiconductor element to electrically connect the element and the element, or the interconnection and the interconnection, and a contact plug is formed to connect the upper metal interconnection and the lower metal interconnection.
상기 금속배선의 재료로는 전기 전도도가 우수한 알루미늄(Al) 및 텅스텐(W)이 주로 이용되어 왔으며, 최근에는 상기 알루미늄 및 텅스텐보다 전기 전도도가 월등히 우수하고 저항이 낮아 고집적 고속동작 소자에서 RC 신호 지연 문제를 해결할 수 있는 구리(Cu)를 차세대 금속배선 물질로 사용하고자 하는 연구가 진행되고 있다. 그런데, 상기 구리의 경우 배선 형태로 건식 식각되는 것이 용이하지 않기 때문에, 구리로 금속배선을 형성하기 위해서는 다마신(Damascene)이라는 새로운 공정 기술이 이용된다. Aluminum (Al) and tungsten (W), which have excellent electrical conductivity, have been mainly used as the material for the metallization, and in recent years, the RC signal delay in high-integrated high-speed operation devices has much higher electrical conductivity and lower resistance than the aluminum and tungsten. Research into using copper (Cu) as a next-generation metallization material that can solve the problem is being conducted. However, since the copper is not easily etched in the form of a wiring, a new process technology called damascene is used to form metal wiring with copper.
상기 다마신 금속배선 공정은 반도체 기판 상에 형성된 절연막을 식각해서 배선 형성 영역을 형성하고, 상기 배선 형성 영역을 매립하도록 구리막을 증착한 후에 상기 구리막을 CMP(Chemical Mechanical Polishing)하여 금속배선을 형성하는 기술이다. In the damascene metallization process, an insulating film formed on a semiconductor substrate is etched to form a wiring formation region, and a copper film is deposited to fill the wiring formation region, followed by CMP (Chemical Mechanical Polishing) to form metal wiring. Technology.
이하에서는, 종래 기술에 따른 금속배선의 형성 공정을 포함한 반도체 소자의 제조방법을 간략하게 설명하도록 한다. Hereinafter, a manufacturing method of a semiconductor device including a process of forming a metal wiring according to the prior art will be briefly described.
반도체 기판 상에 절연막을 형성한 다음, 상기 절연막을 식각하여 배선 형성 영역을 형성한다. 상기 배선 형성 영역을 포함한 절연막 상에 확산방지막을 형성한 후, 상기 확산방지막 상에 상기 배선 형성 영역을 매립하도록 구리막을 형성한다. 이어서, 상기 구리막을 상기 절연막이 노출되도록 CMP하여 금속배선을 형성한다. 그리고 나서, 상기 금속배선 및 절연막을 덮도록 베리어막을 형성한다.After forming an insulating film on the semiconductor substrate, the insulating film is etched to form a wiring formation region. After forming the diffusion barrier on the insulating film including the wiring forming region, a copper film is formed on the diffusion barrier to fill the wiring forming region. Subsequently, the copper film is CMP to expose the insulating film to form metal wiring. Then, a barrier film is formed so as to cover the metal wiring and the insulating film.
그러나, 전술한 종래 기술의 경우에는 반도체 소자의 고집적화 추세에 부합하여 배선 간의 간격이 감소함에 따라, 상기 CMP 공정 후에 금속배선 간의 브리지가 발생된다. 자세하게, 배선용 구리막 사이의 절연막 내에서 구리 이온이 이동하여 확산되고, 이러한 구리 이온이 배선 사이의 절연막 상에서 구리 성분으로 성장하여 구리 잔류물이 발생한다. 이 때문에, 상기 절연막 상에 발생된 구리 잔류물로 인해 금속배선 간의 브리지가 유발되는 것이다. However, in the above-described prior art, as the spacing between wirings decreases in accordance with the trend of high integration of semiconductor devices, bridges between metal wirings are generated after the CMP process. In detail, copper ions move and diffuse in the insulating film between the wiring copper films, and these copper ions grow as a copper component on the insulating film between the wirings to generate a copper residue. For this reason, the bridge between metal wirings is caused by the copper residue which generate | occur | produced on the said insulating film.
본 발명은 금속배선 간의 브리지를 방지할 수 있는 반도체 소자의 제조방법을 제공한다.The present invention provides a method for manufacturing a semiconductor device that can prevent the bridge between the metal wiring.
본 발명의 실시예에 따른 반도체 소자의 제조방법은, 반도체 기판 상에 배선 형성 영역을 갖는 절연막을 형성하는 단계, 상기 절연막 상에 상기 배선 형성 영역을 매립하도록 금속막을 형성하는 단계, 상기 금속막을 상기 절연막이 노출되도록 제거하는 단계 및 상기 노출된 절연막 상에 발생된 금속 잔류물 및 상기 금속막의 표면을 산화시켜 금속 산화물 및 금속 산화막을 각각 형성하는 단계를 포함한다.In the method of manufacturing a semiconductor device according to an embodiment of the present invention, forming an insulating film having a wiring forming region on a semiconductor substrate, forming a metal film to fill the wiring forming region on the insulating film, the metal film Removing the insulating film so that the insulating film is exposed, and oxidizing the metal residue generated on the exposed insulating film and the surface of the metal film to form a metal oxide and a metal oxide film, respectively.
상기 절연막을 형성하는 단계 후, 그리고, 상기 금속막을 형성하는 단계 전, 상기 배선 형성 영역의 표면을 포함한 절연막 상에 확산방지막을 형성하는 단계를 더 포함한다.And forming a diffusion barrier on the insulating film including the surface of the wiring forming region after the forming of the insulating film and before the forming of the metal film.
상기 금속막은 구리막을 포함한다.The metal film includes a copper film.
상기 금속막을 상기 절연막이 노출되도록 제거하는 단계는, CMP 공정으로 수행한다.The removing of the metal film to expose the insulating film is performed by a CMP process.
상기 금속 산화물 및 금속 산화막을 형성하는 단계는, O2 플라즈마 처리 또는 열처리 방식으로 수행한다.The forming of the metal oxide and the metal oxide film may be performed by an O 2 plasma treatment or a heat treatment method.
상기 열처리는 RTP 공정으로 수행한다.The heat treatment is performed by the RTP process.
상기 금속 산화물 및 금속 산화막을 형성하는 단계 후, 상기 금속 산화물, 금속 산화막 및 절연막 상에 베리어막을 형성하는 단계, 상기 베리어막 상에 층간 절연막을 형성하는 단계, 상기 층간 절연막 및 베리어막을 식각하여 상기 금속 산화막 부분을 노출시키는 홀을 형성하는 단계, 상기 노출된 금속 산화막 부분을 다 시 금속막으로 환원시키는 단계 및 상기 환원된 금속막 부분을 포함한 층간 절연막 상에 상기 홀을 매립하도록 도전막을 형성하는 단계를 더 포함한다.After forming the metal oxide and the metal oxide film, forming a barrier film on the metal oxide, the metal oxide film, and the insulating film, forming an interlayer insulating film on the barrier film, etching the interlayer insulating film and the barrier film, and etching the metal. Forming a hole exposing the oxide film portion, reducing the exposed metal oxide film portion back to the metal film, and forming a conductive film to fill the hole on the interlayer insulating film including the reduced metal film portion. It includes more.
상기 금속 산화막 부분을 금속막으로 환원시키는 단계는, 플라즈마 처리 방식으로 수행한다.Reducing the metal oxide film portion to the metal film is performed by a plasma treatment method.
상기 플라즈마 처리는 H2 가스와 NH3 가스를 포함하는 환원성 가스 분위기에서 수행한다.The plasma treatment is performed in a reducing gas atmosphere containing H 2 gas and NH 3 gas.
상기 금속 산화물 및 금속 산화막을 형성하는 단계 후, 상기 금속 산화물, 금속 산화막 및 절연막 상에 베리어막을 형성하는 단계, 상기 베리어막 상에 층간 절연막을 형성하는 단계, 상기 층간 절연막 및 베리어막을 식각하여 상기 금속 산화막 부분을 노출시키는 홀을 형성하는 단계, 상기 노출된 금속 산화막 부분을 제거하는 단계 및 상기 금속 산화막 부분이 제거된 후에 상기 홀을 매립하도록 도전막을 형성하는 단계를 더 포함한다.After forming the metal oxide and the metal oxide film, forming a barrier film on the metal oxide, the metal oxide film, and the insulating film, forming an interlayer insulating film on the barrier film, etching the interlayer insulating film and the barrier film, and etching the metal. Forming a hole exposing the oxide film portion, removing the exposed metal oxide film portion, and forming a conductive film to fill the hole after the metal oxide film portion is removed.
상기 금속 산화막 부분을 제거하는 단계는, 스퍼터링 식각 방식으로 수행한다.Removing the metal oxide layer portion is performed by a sputtering etching method.
본 발명은 구리막을 CMP하여 금속배선을 형성한 후에 절연막 상에 발생된 구리 잔류물을 산화시킴으로써, 상기 구리 잔류물로 인해 유발되는 금속배선 간 브리지를 방지할 수 있다.The present invention can prevent the bridge between metal wires caused by the copper residue by oxidizing the copper residue generated on the insulating film after CMP of the copper film to form the metal wiring.
또한, 본 발명은 상기 구리 잔류물의 산화시 함께 산화되어 형성된 구리막 표면의 구리 산화막 부분을 콘택 플러그 예정 영역에서 선택적으로 환원시키거나 제거함으로써, 금속배선과 콘택 플러그 간의 콘택 저항을 개선할 수 있다.In addition, the present invention can improve the contact resistance between the metal wiring and the contact plug by selectively reducing or removing the copper oxide film portion of the surface of the copper film formed by being oxidized together when the copper residue is oxidized.
따라서, 본 발명은 금속배선 특성을 포함한 반도체 소자의 특성 및 신뢰성을 효과적으로 향상시킬 수 있다.Therefore, the present invention can effectively improve the characteristics and reliability of semiconductor devices including metallization characteristics.
이하에서는 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.
도 1a 내지 도 1h는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도이다. 1A to 1H are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
도 1a를 참조하면, 게이트, 비트 라인 등의 하부 구조물(도시안됨)이 형성된 반도체 기판(100) 상에 절연막(102)을 형성한다. 상기 절연막(102)은 산화막을 포함한다. 상기 절연막(102)을 식각하여 배선 형성 영역(D)을 형성한다. 상기 배선 형성 영역(D)은 트렌치, 또는, 콘택홀로 형성하거나, 또는, 도시하지는 않았으나, 트렌치 및 콘택홀로 형성하는 것도 가능하다.Referring to FIG. 1A, an
도 1b를 참조하면, 상기 배선 형성 영역(D)을 포함한 절연막(102) 상에 확산방지막(104)을 형성한다. 이어서, 상기 확산방지막(104) 상에 상기 배선 형성 영역(D)을 매립하도록 배선용 금속막, 예컨대, 구리막(106a)을 형성한다. 상기 구리막(106a)은 PVD(Physical Vapor Deposition), CVD(Chemical Vapor Deposition) 및 전기도금(Electroplating) 등의 방식으로 형성한다.Referring to FIG. 1B, a
도 1c를 참조하면, 상기 구리막 및 베리어막(104)을 상기 절연막(102)이 노 출되도록 제거하여 상기 배선 형성 영역(D) 내에 금속배선(106)을 형성한다. 상기 구리막 및 베리어막(104)의 제거는, 바람직하게, CMP 공정으로 수행한다. Referring to FIG. 1C, the copper film and the
이때, 반도체 소자의 고집적화 추세에 부합하여 금속배선(106) 간의 간격이 감소함에 따라, 구리막 사이의 절연막(102) 내에서 구리 이온이 확산되고, 이러한 구리 이온이 절연막(102) 상에서 구리 성분으로 성장하여, 상기 CMP 공정 후에도 절연막(102) 상에 구리 잔류물(108a)이 발생되어 있다. At this time, in accordance with the trend of higher integration of semiconductor devices, as the gap between the
도 1d를 참조하면, 상기 절연막(102) 상에 발생된 구리 잔류물 및 금속배선(106)의 표면을 산화(110)시킨다. 상기 산화(110)는 플라즈마 처리 또는 열처리 방식으로 수행하며, 상기 열처리는, 예컨대, RTP(Rapid Thermal Process) 공정으로 수행한다.Referring to FIG. 1D, the surface of the copper residue and the
그 결과, 상기 절연막(102)) 상의 구리 잔류물이 구리 산화물(108)으로 변환되고, 상기 금속배선(106)의 표면이 산화되어 구리 산화막(112)이 형성된다. 상기 산화(110)를 통해 산화된 구리 산화물(108)은 절연 물질이므로, 배선 간 브리지를 유발하지 않는다.As a result, the copper residue on the
도 1e를 참조하면, 상기 구리 산화막(112), 구리 산화물(108) 및 절연막(102) 상에 베리어막(114)을 형성한 후, 상기 베리어막(114) 상에 층간 절연막(116)을 형성한다. 상기 층간 절연막(116)은 산화막을 포함한다.Referring to FIG. 1E, after the
도 1f를 참조하면, 상기 층간 절연막(116) 및 베리어막(114)을 식각하여 상기 구리 산화막(112) 부분을 노출시키는 홀(H)을 형성한다. 상기 홀(H)은 금속배선(106)과 전기적인 연결을 이루는 콘택 플러그 예정 영역에 형성된다.Referring to FIG. 1F, the
도 1g를 참조하면, 상기 노출된 구리 산화막(112) 부분을 제거하여 그 아래의 금속배선(106) 부분을 노출시킨다. 상기 구리 산화막(112) 부분의 제거는 Ar 가스 등의 가스를 사용하는 스퍼터링 식각 방식으로 수행한다. Referring to FIG. 1G, the exposed portion of the
한편, 도시하지는 않았으나 상기 노출된 구리 산화막(112) 부분을 환원시켜 다시 구리막으로 변환시키는 것도 가능하다. 상기 노출된 구리 산화막(112) 부분의 환원은 H2 가스와 NH3 가스를 포함하는 환원성 가스 분위기에서 상기 플라즈마 처리로 수행한다. 또한, 상기 플라즈마 처리시 환원성 가스와 Ar 가스를 함께 공급하여 구리 산화막(112) 부분의 스퍼터링 식각과 환원을 동시에 진행하는 것도 가능하다.On the other hand, although not shown, it is also possible to reduce the exposed portion of the
도 1h를 참조하면, 상기 노출된 금속배선(106) 및 층간 절연막(116) 상에 상기 홀(H)을 매립하도록 도전막을 형성한다. 그런 다음, 상기 도전막을 상기 층간 절연막(116)이 노출될 때까지 CMP 또는 에치백하여 상기 홀(H) 내에 상기 금속배선(106)과 콘택하는 콘택 플러그(118)를 형성한다.Referring to FIG. 1H, a conductive film is formed to fill the hole H on the exposed
이후, 도시하지는 않았으나 공지된 일련의 후속 공정들을 차례로 수행하여 본 발명의 실시예에 따른 반도체 소자의 제조를 완성한다. Subsequently, although not shown, a series of subsequent known processes are sequentially performed to complete the manufacture of the semiconductor device according to the embodiment of the present invention.
전술한 바와 같이, 본 발명의 실시예에서는 배선 형성 영역을 매립하도록 형성된 구리막을 CMP하여 상기 배선 형성 영역에 금속배선을 형성한 후에, 절연막 상에 발생된 구리 잔류물을 플라즈마 처리나 열처리 등의 방식을 통해 산화시켜 구리 산화물을 형성한다.As described above, in the embodiment of the present invention, after the CMP of the copper film formed to fill the wiring formation region is formed to form metal wiring in the wiring formation region, the copper residue generated on the insulating film is subjected to plasma treatment or heat treatment. Oxidation through gives copper oxide.
따라서, 본 발명은 상기 절연막 상에 발생된 구리 잔류물이 산화되어 절연성 물질인 구리 산화물로 변환되었으므로, 상기 구리 잔류물로 인해 유발되는 금속배선 간 브리지를 방지할 수 있다.Therefore, in the present invention, since the copper residue generated on the insulating film is oxidized and converted into the copper oxide which is an insulating material, it is possible to prevent the bridge between metal wirings caused by the copper residue.
또한, 본 발명은 상기 금속배선과 콘택 플러그가 접하는 부분의 구리 산화 막 부분을 다시 환원시키거나 제거함으로써, 콘택 저항을 개선할 수 있다.In addition, the present invention can improve the contact resistance by reducing or removing the copper oxide film portion of the portion where the metal wiring and the contact plug are in contact again.
그러므로, 본 발명은 배선 특성을 포함한 반도체 소자의 특성 및 신뢰성을 효과적으로 향상시킬 수 있다.Therefore, the present invention can effectively improve the characteristics and the reliability of the semiconductor element including the wiring characteristics.
이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.
도 1a 내지 도 1h는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정별 단면도.1A to 1H are cross-sectional views illustrating processes for manufacturing a semiconductor device in accordance with an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100 : 반도체 기판 102 : 절연막100
D : 배선 형성 영역 104 : 확산방지막D: wiring formation region 104: diffusion barrier
106a : 구리막 106 : 금속배선106a: copper film 106: metal wiring
108a : 구리 잔류물 108 : 구리 산화물108a: copper residue 108: copper oxide
110 : 산화 112 : 구리 산화막110: oxide 112: copper oxide film
114 : 베리어막 116 : 층간절연막114: barrier film 116: interlayer insulating film
H : 홀 118 : 콘택 플러그H: Hole 118: Contact Plug
Claims (11)
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102222638A (en) * | 2010-04-13 | 2011-10-19 | 中芯国际集成电路制造(上海)有限公司 | Method for removing copper residue between copper lead wires |
| CN105336573A (en) * | 2014-08-01 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Method for removing aluminum residues |
| US20160218036A1 (en) * | 2014-05-16 | 2016-07-28 | Taiwan Semiconductor Manufacturing Company Limited | Method of fabricating a semiconductor device with reduced leak paths |
| CN113097127A (en) * | 2020-01-09 | 2021-07-09 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
-
2008
- 2008-07-25 KR KR1020080073169A patent/KR20100011799A/en not_active Application Discontinuation
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102222638A (en) * | 2010-04-13 | 2011-10-19 | 中芯国际集成电路制造(上海)有限公司 | Method for removing copper residue between copper lead wires |
| US20160218036A1 (en) * | 2014-05-16 | 2016-07-28 | Taiwan Semiconductor Manufacturing Company Limited | Method of fabricating a semiconductor device with reduced leak paths |
| US9978640B2 (en) * | 2014-05-16 | 2018-05-22 | Taiwan Semiconductor Manufacturing Company Limited | Method of fabricating a semiconductor device with reduced leak paths |
| CN105336573A (en) * | 2014-08-01 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | Method for removing aluminum residues |
| CN113097127A (en) * | 2020-01-09 | 2021-07-09 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor structure |
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