KR20090045774A - Digital-to-analog converter - Google Patents

Abstract

The present invention provides an internal configuration and method for increasing the accuracy and reducing the overall area of the digital-to-analog converter that increases with the number of bits of the digital signal input from the digital-to-analog converter. To this end, the digital-to-analog converter according to the present invention receives a digital signal of N bits (N is a natural number) and classifies the M bits into a group of M bits (M is a natural number) in order from the lower bits to the digital signals of each group. The corresponding analog values are generated by applying weights to each of them, and each analog value outputted from M lower to upper groups in order is 2 ^{(N / M) * 0} , 2 ^{(N / M) * 1} , ..., It includes a conversion circuit for output by increasing by 2 ^{(N / M) * (M-1)} times. Accordingly, the present invention can be applied to high resolution electronic devices and systems while having a small area while preventing the exponential increase in the total area of the digital-to-analog converter according to the number of bits of the input digital signal.

Binary weighting technique, digital-to-analog converter, fine tuning, approximation, chip area

Description

DIGITAL-TO-ANALOG CONVERTER}

The present invention relates to a digital-to-analog converter, and more particularly, to an internal configuration and a conversion method for overcoming the disadvantage of increasing the total area as the resolution increases and reducing power consumption and area.

In general, an electronic device such as a semiconductor memory device, a signal processing device, and a system including the same include a circuit for processing an analog or digital signal, and an analog-to-digital converter for converting an analog signal into a digital signal as needed. And optionally a digital-to-analog converter (DAC) for converting an analog-to-digital converter (ADC) and a digital signal into an analog signal.

A digital-to-analog converter (DAC) is a device that outputs an analog signal having an appropriate voltage or current corresponding to a multi-bit digital signal input. The digital-to-analog converter (DAC) generates a voltage or current corresponding to each bit of the digital signal and then reassembles the analog signal. Output the signal. As a type of digital-to-analog converter (DAC), a decoder-based apparatus that first generates 2 ^N reference signals using a decoder for N digital input signals and combines the reference signals into a signal corresponding to the input to output an analog signal 'Decoder Based DAC' is a digital-to-analog converter that applies binary weighting techniques to give binary weights of digital inputs with current, voltage, or charge, and arrange them to obtain desired analog signals. (Binary Weighted Array DAC), Digital-to-Analog Converter (Capacitor-Resistor Array DAC) with resistance and capacitor alignment structure made using the advantages of Digital-to-Analog Converter (DAC) described above, and Thermometer Code Digital-to-analog converter (DAC) using the Thermometer Code technique. Among them, the digital-to-analog converter using the binary weighting technique is most widely used.

The digital-to-analog converter using the binary weighting technique is a digital-to-analog converter design technique that obtains a desired analog signal by assigning an appropriate weight to input digital signals (binary signals), and among them, using a weight current. We look at digital-to-analog converters (DACs).

1 is a circuit diagram illustrating a digital-to-analog converter using a weighted current by applying a binary weighting technique.

As shown in the drawing, the digital-to-analog converter includes a switching unit 140 into which a digital signal is input, a current weighting unit 160 for applying a weighted current to the output of the switching unit 140, and a current to the current weighting unit 160. And a current source 120 for supplying a sum, and an output unit 180 for adding and outputting a weighted current corresponding to each bit of the digital signal.

The digital analog converter receives an 8-bit digital signal and increases the current from the current source 120 by a magnification corresponding to the digital signal through a cascode current mirror. The current weighting unit 160 adjusts the channel width and length (W / L) of transistors of each stage receiving each bit of the digital signal to allow current to flow by a corresponding magnification, and is a binary code digital code. The ratio of the amount of current flowing in each stage depends on the characteristics of. Therefore, each stage corresponding to the total 8-bit digital signal adjusts the channel width and length of the transistor so that currents of X1, X2, X4, X8, X16, X32, X64, and X128 can flow.

In FIG. 1, an example of receiving an 8-bit digital signal has been described. However, as the number of bits of an input digital signal, such as 10 bits or 16 bits, increases, a circuit of a switch role receiving a digital signal and a weight of each bit may be assigned. The size of the weighting circuit increases. Therefore, in the case of a digital-to-analog converter using a commonly used binary weighting technique, as the number of bits of an input digital signal increases, the area of the circuit cannot be prevented from increasing. In addition, when the reference current is generated and weighted to each bit of the digital signal with the reference current, as the number of bits of the digital signal increases, it becomes difficult to maintain the precision of the weight to be applied to each bit.

Recently, systems and various electronic devices are required for more precise and faster operation. Accordingly, the number of bits of digital signals is increasing. However, the existing digital-to-analog converter has a disadvantage in area and accuracy as the number of bits of the input digital signal increases, so a digital-to-analog converter having a new structure is required.

According to the present invention, in order to prevent the total area from increasing exponentially according to the number of bits of the digital signal input from the digital-to-analog converter and to prevent the precision from falling, the digital signals are classified into a predetermined bit unit and grouped, respectively, and then weighted by bit. By adopting the method to obtain the corresponding analog value by compensating and to compensate the weight for each group, it provides the internal configuration and method that can reduce the increase of the total area and maintain the high precision.

The present invention receives a digital signal of N (N is a natural number) bits, classifies the lower bits to the upper bits into M (M is a natural number) groups in order, and then applies a weight to each group of digital signals to correspond to the analog signal. Create a value, and in turn, set each analog value output from the M lower to upper groups in order 2 ^{(N / M) * 0} , 2 ^{(N / M) * 1} , ..., 2 ^{(N / M) * ( It} provides a digital-to-analog converter for outputting the analog signal corresponding to the N-bit digital signal, including a conversion circuit for increasing the ^M-1) times.

In addition, the present invention receives a bias unit for supplying a current, N (N is a natural number) bit received a digital signal is divided into a group of M (M is a natural number) from the lower bit to the upper bit in order to each group A conversion circuit for generating a corresponding analog value by applying a weight to the digital signal, increasing each of the analog values outputted from the M groups by a constant magnification, and summing the currents output from the conversion circuit, N A digital-analog converter including a current adder for outputting an analog signal having a current value corresponding to a digital signal of a bit is provided.

Furthermore, the present invention comprises the steps of receiving a digital signal of N (N is a natural number) bits, classifying the lower bits and the upper bits of the digital signal into M (M is a natural number) in order, each classified Generating an analog value by applying weights to the digital signals of the group, and 2 ^{(N / M) * 0} , 2 ^{(N / M) * 1} in order of each analog value output from the M lower to upper groups in order Provides a conversion method for outputting an analog signal corresponding to a digital signal comprising the step of outputting a current by increasing by 2 ^{(N / M) * (M-1)} times.

In order to reduce the power consumption and the area that increase with the increase of the resolution when designing the digital-to-analog converter, the present invention proposes a digital-to-analog converter using a method of fine scaling and coarse scaling. . As a general method of changing the channel width and length of a transistor to apply a weight corresponding to each bit number of an input digital signal, the size of the digital-to-analog converter increases rapidly as the number of bits of the digital signal increases and a number of weights are applied. In order to overcome the disadvantage that the accuracy is poor due to the application of the present invention, the digital signal is classified into a predetermined bit unit and grouped, and each weight is applied to each bit to obtain a corresponding analog value, and then the weight of each group can be compensated. Make sure

The present invention is advantageous in that the total area of the digital-to-analog converter is exponentially increased according to the number of bits of the input digital signal, thereby being applicable to high resolution electronic devices and systems while having a small area.

In addition, the present invention can further increase the precision than when applying a weight corresponding to the number of bits of the digital signal at a time because the number of bits of the input digital signal is grouped and converted into a predetermined unit and grouped and subsequently weighted for each group. .

The above objects, features, and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, whereby those skilled in the art may easily implement the technical idea of the present invention. There will be. In addition, in describing the present invention, when it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a digital-to-analog converter according to an embodiment of the present invention.

As shown in the drawing, the digital-to-analog converter receives an N-bit digital signal, classifies the lower bits to the higher bits into M groups in order, and applies a weight to each group of digital signals to generate corresponding analog values. And a conversion circuit for increasing the respective analog values output from the M groups by a predetermined magnification. Where N and M are natural numbers. At this time, the conversion circuit converts each current output from the M lower to upper groups in order 2 ^{(N / M) * 0} , 2 ^{(N / M) * 1} , ..., 2 ^{(N / M) * (M -1)} multiply by a factor. As a result, a digital-to-analog converter for converting an N-bit digital signal into an analog signal can overcome the disadvantage that the size increases and the precision decreases corresponding to the number of bits of the input digital signal.

Specifically, referring to FIG. 2, the digital-analog converter includes the above-described conversion circuit, a bias unit 220 for supplying current to the conversion circuit, and a current summing unit 280 for summing the currents output from the conversion circuit. It includes. The conversion circuit includes a first converter 240 and a second converter 260. Furthermore, the digital-analog converter further includes a voltage converter 290 for outputting a voltage corresponding to the amount of current output from the current adder 280. The output of the digital-to-analog converter is an analog signal having a current value or a voltage level corresponding to the input digital signal. An embodiment of the present invention describes a case of outputting an analog signal having a corresponding voltage level.

As an exemplary embodiment of the present invention, an input digital signal is a 10-bit signal, which is classified into two groups and converted into an analog signal. That is, when N is 10 and M is 2, the first converter 240 and the second converter 260 included in the conversion circuit respectively output a current amount corresponding to the input digital signal by 2 ^{(10 / 2) increase by 0} times and by 2 ^{(10/2) * (2-1)} times. The first converter 240 receives only the lower 5 bits of the 10-bit digital signal, generates a voltage corresponding to each bit, converts the signal into a signal having a current amount corresponding to each voltage, and outputs the second voltage. The 260 receives only the upper 5 bits of the 10-bit digital signal and outputs a signal having a current amount corresponding to the analog value in the same manner.

Here, although both the first converter 240 and the second converter 260 distinguish the weights for the 5-bit digital signals, the digital signal input to the second converter 260 is transferred to the first converter 240. Since the bit is higher than the input digital signal, the output of the second converter 260 must be increased by a predetermined amount. Since the number of lower bits inputted to the first converter 240 is 5, the output of the second converter 260 should be increased by 2 ^{5 = (10/2) * (2-1)} (32 times). An analog signal corresponding to the digital signal of the bit can be generated.

In detail, the first converter 240 receives 5 bits from the lower bit of the digital signal and determines the micro conversion cell unit 244 and the initial start voltage to allow a current to flow according to a weight corresponding to each bit. In the fine voltage determination unit 246 for generating a bias of the fine conversion cell unit 244, the fine adjustment unit 242 for outputting a voltage corresponding to the current value of the fine conversion cell unit 244, and the fine adjustment unit 242. It includes a fine current converter 248 for converting into a current value corresponding to the output voltage and output.

Similarly, the second converter 260 receives an input of 5 bits from the upper bits of the digital signal, and estimates the conversion cell unit 264 for flowing a current according to a weight corresponding to each bit. Estimation voltage determiner 266 for generating bias of 264, Estimation adjuster 262 for outputting voltage corresponding to current value of approximation conversion cell unit 264, and voltage output from approximation adjuster 262. Approximate current converter 268 for converting and outputting a current value corresponding to the.

However, in order to increase the output by the second converter 260 by 32 times, the estimator 262 may have a resistance that is four times larger than the resistance included in the fine controller 242 in the first converter 240. And a current output from the approximation conversion cell unit 264 to pass a voltage level four times larger than the same digital signal as the fine adjustment unit 242. In addition, the approximation current converter 268 generating a current corresponding to the voltage level output from the approximation adjuster 262 also outputs a signal having an amount of current eight times larger in the same environment than the fine current converter 248. Through this process, the second converter 260 can generate an analog signal having a current amount of 32 times larger than that of the first converter 240 when the same digital signal is input, and thus, the second converter 260 can generate an analog signal having the upper 5 bits of the 10-bit digital signal. Corresponding weighted analog signals can be generated.

In the present invention shown in FIG. 2, a process of classifying a 10-bit digital signal into two groups and converting each signal into an analog signal and summing them is shown. However, the 12-bit digital signal is divided into two groups, three groups, or M. It is also possible to convert into analog signals by dividing into groups and to modify them according to the system environment in which the digital-to-analog converter is used.

FIG. 2 is a circuit diagram illustrating the fine conversion cell unit 244 illustrated in FIG. 1.

As shown, the fine conversion cell unit 244 includes a plurality of current stages for flowing the current by the weight corresponding to each bit of the digital signal. Specifically, each current stage includes a first transistor turned on in response to each bit signal DACSEL <0: 4> of the digital signal, a second transistor turned on in response to an activation control signal NCAS, and a bias unit. And a third transistor that is turned on corresponding to the output NBAIAS of 220, and all of the first to third transistors are NMOS transistors connected in series between a driving voltage and a ground voltage.

In the digital-to-analog converter according to an embodiment of the present invention, the internal structure of the fine conversion cell unit 244 and the approximation conversion cell unit 264 are identical. That is, five weights are differently assigned according to each bit of the digital signal, and there are only differences in magnification (X1, X2, X4, X8, X16) between internal current stages. ) May be composed of transistors having the same function and structure (especially the width and length of the channel). This is different from the case in which the channel width and length of the transistor are differently adjusted (e.g., 10-bit) in order to vary the weight and to vary the magnification for each bit of the digital signal input from the conventional digital-to-analog converter. In the case of 10 or 20 bits, the channel width and length of the transistor must be changed in order to apply 20 weights.) In the present invention, even if only 5 weights are applied, an analog signal corresponding to a 10-bit digital signal can be generated. Can be.

According to the present invention, it is possible to classify the weights by the number of bits in each group rather than the number of bits of the input digital signal, thereby reducing the overall size of the digital-to-analog converter and increasing the precision. . In particular, a digital-to-analog converter for generating an analog signal corresponding to a 10-bit digital signal is grouped into lower and upper 5 bits to fine scale and coarse scale each corresponding analog value. The method was used to reduce the total area. Furthermore, the fine adjustment and approximation adjustment method according to the present invention can be applied to semiconductor memory devices, signal processing devices, electronic equipment, systems and the like that require high integration circuits and high precision.

The present invention described above is capable of various substitutions, modifications, and changes without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains. It is not limited by the drawings.

1 is a circuit diagram illustrating a digital-to-analog converter using a weighted current by applying a binary weighting technique.

2 is a block diagram illustrating a digital-to-analog converter according to an embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating the micro conversion cell unit illustrated in FIG. 2.

Claims (25)

The digital signal of N (N is natural number) is input and the lower bits are classified into M (M is natural number) groups in order, and the corresponding analog values are generated by applying weights to the digital signals of each group. And each analog value output from M low to high group in order 2 ^{(N / M) * 0} , 2 ^{(N / M) * 1} , ..., 2 ^{(N / M) * (M-1 )} times, and comprises a converter circuit for outputting increased by, digital to output an analog signal corresponding to the digital signals of the N-bit-to-analog converter. The method of claim 1, A bias unit for supplying current to the conversion circuit; And And a current adder for summing the currents output from the conversion circuit. The method of claim 2, And a voltage converter configured to output a voltage corresponding to the amount of current output from the current adder. The method of claim 2, When N is 10 and M is 2, the conversion circuit includes a first converter and a second converter, and the amount of current output from the first converter is increased by 2 ^{(10/2) * 0} times and the And a current amount output from the second converter is increased by 2 ^{(10/2) * (2-1)} times. The method of claim 4, wherein The first conversion unit A fine conversion cell unit configured to receive 5 bits from the lower bits of the digital signal and flow a current according to a weight corresponding to each bit; A fine voltage determination unit for determining an initial start voltage to generate a bias of the fine conversion cell unit; A fine adjustment unit for outputting a voltage corresponding to the current value of the fine conversion cell unit; And And a fine current converter for converting and outputting a current value corresponding to the voltage output from the fine controller. The method of claim 5, The fine conversion cell unit And a plurality of current stages for flowing a weighted current corresponding to each bit of the digital signal. The method of claim 6, wherein Each current stage is A first transistor turned on corresponding to each bit signal of the digital signal; A second transistor turned on in response to an activation control signal; And And a third transistor turned on corresponding to the output of the bias unit, wherein the first to third transistors are connected in series between a driving voltage and a ground voltage. The method of claim 5, The second conversion unit An approximate conversion cell unit configured to receive 5 bits from the upper bits of the digital signal and flow a current according to a weight corresponding to each bit; An approximate voltage determination unit for determining an initial start voltage to generate a bias of the approximation conversion cell unit; An approximation adjusting unit for outputting a voltage corresponding to a current value of the approximating conversion cell unit; And And a rough current converter for converting and outputting a current value corresponding to the voltage output from the roughness adjusting section. The method of claim 8, And the internal structure of the fine conversion cell portion and the approximation conversion cell portion are identical. The method of claim 9, The approximation control unit includes a resistor having a resistance value four times larger than the fine adjustment unit to pass a current output from the approximation conversion cell unit to output a voltage value four times larger than the fine adjustment unit, and the estimation current conversion unit is fine. Digital-to-analog converter, characterized in that for amplifying and outputting the current value eight times than the current converter. A bias unit for supplying a current; The digital signal of N (N is natural number) is input and the lower bits are classified into M (M is natural number) groups in order, and the corresponding analog values are generated by applying weights to the digital signals of each group. And a conversion circuit for increasing each analog value output from the M groups by a predetermined magnification and outputting the same; And And a current summing portion for summing the currents output from the conversion circuit and outputting an analog signal having a current value corresponding to the N-bit digital signal. The method of claim 11, And a voltage converter configured to output an analog signal having a voltage level corresponding to the amount of current of the analog signal output from the current adder. The method of claim 11, wherein The conversion circuit converts each current output from the M lower to upper groups in order 2 ^{(N / M) * 0} , 2 ^{(N / M) * 1} , ..., 2 ^{(N / M) * (M -1)} a digital-to-analog converter characterized by amplifying by a factor of two. The method of claim 13, When N is 10 and M is 2, the conversion circuit includes a first converter and a second converter, and the amount of current output from the first converter is increased by 2 ^{(10/2) * 0} times and the And a current amount output from the second converter is increased by 2 ^{(10/2) * (2-1)} times. The method of claim 14, The first conversion unit A fine conversion cell unit configured to receive 5 bits from the lower bits of the digital signal and flow a current according to a weight corresponding to each bit; A fine voltage determination unit for determining an initial start voltage to generate a bias of the fine conversion cell unit; A fine adjustment unit for outputting a voltage corresponding to the current value of the fine conversion cell unit; And And a fine current converter for converting and outputting a current value corresponding to the voltage output from the fine controller. The method of claim 15, The fine conversion cell unit And a plurality of current stages for flowing a weighted current corresponding to each bit of the digital signal. The method of claim 16, wherein Each current stage is A first transistor turned on corresponding to each bit signal of the digital signal; A second transistor turned on in response to an activation control signal; And And a third transistor turned on corresponding to the output of the bias unit, wherein the first to third transistors are connected in series between a driving voltage and a ground voltage. The method of claim 15, The second conversion unit An approximate conversion cell unit configured to receive 5 bits from the upper bits of the digital signal and flow a current according to a weight corresponding to each bit; An approximate voltage determination unit for determining an initial start voltage to generate a bias of the approximation conversion cell unit; An approximation adjusting unit for outputting a voltage corresponding to a current value of the approximating conversion cell unit; And And a rough current converter for converting and outputting a current value corresponding to the voltage output from the roughness adjusting section. The method of claim 18, And the internal structure of the fine conversion cell portion and the approximation conversion cell portion are identical. The method of claim 19, The approximation control unit includes a resistor having a resistance value four times larger than the fine adjustment unit to pass a current output from the approximation conversion cell unit to output a voltage value four times larger than the fine adjustment unit, and the estimation current conversion unit is fine. Digital-to-analog converter, characterized in that for amplifying and outputting the current value eight times than the current converter. Receiving a digital signal of N (N is a natural number) bits; Classifying the lower bits and the upper bits of the digital signal into M groups in which M is a natural number; Generating an analog value by applying weights to the classified digital signals of each group; And Each analog value output from M low to high group in order 2 ^{(N / M) * 0} , 2 ^{(N / M) * 1} , ..., 2 ^{(N / M) * (M-1)} A conversion method for outputting an analog signal corresponding to a digital signal comprising the step of increasing the current by a multiple. The method of claim 21, wherein Outputting the current is Generating a corresponding current value by applying a weight to each bit of the digital signal; Converting the current value into a corresponding voltage value through a resistor having a predetermined value; And converting the current value corresponding to the voltage value to output the analog signal corresponding to the digital signal. The method of claim 22, Amplifying the voltage value by changing the resistance value of the resistor and converting the voltage value into a current value, thereby amplifying the signal of the analog signal corresponding to the digital signal, characterized in that it can vary the magnification of the current value output from each group. Conversion method for outputting. The method of claim 21, And outputting a current by summing the current values output from the respective groups. The method of claim 24, And outputting a voltage corresponding to the sum of the currents of the summed and outputted currents.

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