KR20090014750A - Manufacturing method of array substrate for liquid crystal display - Google Patents
Manufacturing method of array substrate for liquid crystal display Download PDFInfo
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- KR20090014750A KR20090014750A KR1020070078934A KR20070078934A KR20090014750A KR 20090014750 A KR20090014750 A KR 20090014750A KR 1020070078934 A KR1020070078934 A KR 1020070078934A KR 20070078934 A KR20070078934 A KR 20070078934A KR 20090014750 A KR20090014750 A KR 20090014750A
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- 239000000758 substrate Substances 0.000 title claims abstract description 52
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 26
- 238000005530 etching Methods 0.000 claims abstract description 83
- 239000010949 copper Substances 0.000 claims abstract description 52
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 50
- 229910052802 copper Inorganic materials 0.000 claims abstract description 50
- 229910000881 Cu alloy Inorganic materials 0.000 claims abstract description 43
- 239000000203 mixture Substances 0.000 claims abstract description 42
- 239000004065 semiconductor Substances 0.000 claims abstract description 18
- 239000010408 film Substances 0.000 claims description 97
- 238000000034 method Methods 0.000 claims description 36
- 239000000654 additive Substances 0.000 claims description 29
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 claims description 28
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 24
- 230000000996 additive effect Effects 0.000 claims description 24
- 125000003277 amino group Chemical group 0.000 claims description 14
- 229910001870 ammonium persulfate Inorganic materials 0.000 claims description 14
- 125000003178 carboxy group Chemical group [H]OC(*)=O 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 12
- 229910052757 nitrogen Inorganic materials 0.000 claims description 12
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 12
- 239000008367 deionised water Substances 0.000 claims description 11
- 229910021641 deionized water Inorganic materials 0.000 claims description 11
- 239000007788 liquid Substances 0.000 claims description 11
- FSYKKLYZXJSNPZ-UHFFFAOYSA-N sarcosine Chemical compound C[NH2+]CC([O-])=O FSYKKLYZXJSNPZ-UHFFFAOYSA-N 0.000 claims description 11
- RAXXELZNTBOGNW-UHFFFAOYSA-N imidazole Natural products C1=CNC=N1 RAXXELZNTBOGNW-UHFFFAOYSA-N 0.000 claims description 9
- -1 cyclic amine compound Chemical class 0.000 claims description 7
- NBZBKCUXIYYUSX-UHFFFAOYSA-N iminodiacetic acid Chemical class OC(=O)CNCC(O)=O NBZBKCUXIYYUSX-UHFFFAOYSA-N 0.000 claims description 7
- ULRPISSMEBPJLN-UHFFFAOYSA-N 2h-tetrazol-5-amine Chemical compound NC1=NN=NN1 ULRPISSMEBPJLN-UHFFFAOYSA-N 0.000 claims description 6
- SIKJAQJRHWYJAI-UHFFFAOYSA-N Indole Chemical compound C1=CC=C2NC=CC2=C1 SIKJAQJRHWYJAI-UHFFFAOYSA-N 0.000 claims description 6
- JUJWROOIHBZHMG-UHFFFAOYSA-N Pyridine Chemical compound C1=CC=NC=C1 JUJWROOIHBZHMG-UHFFFAOYSA-N 0.000 claims description 6
- KAESVJOAVNADME-UHFFFAOYSA-N Pyrrole Chemical compound C=1C=CNC=1 KAESVJOAVNADME-UHFFFAOYSA-N 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 108010077895 Sarcosine Proteins 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 5
- 229940043230 sarcosine Drugs 0.000 claims description 5
- WTKZEGDFNFYCGP-UHFFFAOYSA-N Pyrazole Chemical compound C=1C=NNC=1 WTKZEGDFNFYCGP-UHFFFAOYSA-N 0.000 claims description 3
- 125000003295 alanine group Chemical group N[C@@H](C)C(=O)* 0.000 claims description 3
- QWCKQJZIFLGMSD-UHFFFAOYSA-N alpha-aminobutyric acid Chemical class CCC(N)C(O)=O QWCKQJZIFLGMSD-UHFFFAOYSA-N 0.000 claims description 3
- QRUDEWIWKLJBPS-UHFFFAOYSA-N benzotriazole Chemical compound C1=CC=C2N[N][N]C2=C1 QRUDEWIWKLJBPS-UHFFFAOYSA-N 0.000 claims description 3
- 239000012964 benzotriazole Substances 0.000 claims description 3
- 150000002332 glycine derivatives Chemical class 0.000 claims description 3
- PZOUSPYUWWUPPK-UHFFFAOYSA-N indole Natural products CC1=CC=CC2=C1C=CN2 PZOUSPYUWWUPPK-UHFFFAOYSA-N 0.000 claims description 3
- RKJUIXBNRJVNHR-UHFFFAOYSA-N indolenine Natural products C1=CC=C2CC=NC2=C1 RKJUIXBNRJVNHR-UHFFFAOYSA-N 0.000 claims description 3
- UMJSCPRVCHMLSP-UHFFFAOYSA-N pyridine Natural products COC1=CC=CN=C1 UMJSCPRVCHMLSP-UHFFFAOYSA-N 0.000 claims description 3
- 239000010409 thin film Substances 0.000 claims description 2
- GBIBYNIYVUFTIT-UHFFFAOYSA-N 2-[bis(carboxymethyl)amino]acetic acid Chemical class OC(=O)CN(CC(O)=O)CC(O)=O.OC(=O)CN(CC(O)=O)CC(O)=O GBIBYNIYVUFTIT-UHFFFAOYSA-N 0.000 claims 2
- 239000010410 layer Substances 0.000 description 33
- 229910052751 metal Inorganic materials 0.000 description 11
- 239000002184 metal Substances 0.000 description 11
- 230000000052 comparative effect Effects 0.000 description 8
- 238000004544 sputter deposition Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000011651 chromium Substances 0.000 description 3
- IUYOGGFTLHZHEG-UHFFFAOYSA-N copper titanium Chemical compound [Ti].[Cu] IUYOGGFTLHZHEG-UHFFFAOYSA-N 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910003437 indium oxide Inorganic materials 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- MGFYIUFZLHCRTH-UHFFFAOYSA-N nitrilotriacetic acid Chemical compound OC(=O)CN(CC(O)=O)CC(O)=O MGFYIUFZLHCRTH-UHFFFAOYSA-N 0.000 description 2
- 239000007800 oxidant agent Substances 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000001878 scanning electron micrograph Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- WHUUTDBJXJRKMK-VKHMYHEASA-N L-glutamic acid Chemical class OC(=O)[C@@H](N)CCC(O)=O WHUUTDBJXJRKMK-VKHMYHEASA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000004148 unit process Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
- C23F1/10—Etching compositions
- C23F1/14—Aqueous compositions
- C23F1/16—Acidic compositions
- C23F1/18—Acidic compositions for etching copper or alloys thereof
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Nonlinear Science (AREA)
- Optics & Photonics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mathematical Physics (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
본 발명은 과황산암모늄, 아미노기와 카르복시기를 포함하는 첨가제, 질소를 함유하는 첨가제 및 탈이온수를 포함하는 금속 식각액 조성물 및 이를 사용하는 액정표시장치용 어레이 기판의 제조 방법에 관한 것이다.The present invention relates to a metal etchant composition comprising ammonium persulfate, an additive containing an amino group and a carboxyl group, an additive containing nitrogen, and deionized water, and a method of manufacturing an array substrate for a liquid crystal display device using the same.
액정표시장치의 제조 중, 기판 위에 금속 배선을 형성하는 과정은 통상적으로 스퍼터링 등에 의한 금속막 형성공정, 포토레지스트 도포, 노광 및 현상에 의한 선택적인 영역에서의 포토레지스트 형성공정, 및 식각공정에 의한 단계로 구성되고, 개별적인 단위 공정 전후의 세정 공정 등을 포함한다. 이러한 식각공정은 포토레지스트를 마스크로 하여 선택적인 영역에 금속막을 남기는 공정을 의미하며, 통상적으로 플라즈마 등을 이용한 건식식각 또는 식각액을 이용하는 습식식각이 사용된다. During the manufacture of the liquid crystal display, the process of forming the metal wiring on the substrate is usually performed by a metal film forming process by sputtering or the like, a photoresist forming process in a selective region by photoresist coating, exposure and development, and an etching process. It consists of the steps, and the washing process before and after an individual unit process, etc. are included. The etching process refers to a process of leaving a metal film in a selective region using a photoresist as a mask, and typically, dry etching using plasma or wet etching using an etching solution is used.
상기와 같은 액정표시장치에서, 최근 금속배선의 저항이 주요한 관심사로 떠오르고 있다. 저항은 RC 신호지연을 유발하는 주요한 인자이므로, 특히 TFT-LCD(thin film transistor - liquid crystal display)의 경우 패널크기 증가와 고 해상도 실현에 관건이 되고 있기 때문이다. In the liquid crystal display device as described above, the resistance of metal wiring has recently emerged as a major concern. Since resistance is a major factor causing RC signal delay, especially for thin film transistor-liquid crystal display (TFT-LCD), it is a key factor for increasing panel size and realizing high resolution.
따라서, TFT-LCD의 대형화에 필수적으로 요구되는 RC 신호지연의 감소를 실현하기 위해서는, 저저항의 물질개발이 필수적이며 종래에 주로 사용되었던 크롬(Cr 비저항:12.7 ×10-8Ωm), 몰리브덴(Mo 비저항:5×10-8Ωm), 알루미늄(Al 비저항:2.65 ×10-8Ωm) 및 이들의 합금은 대형 TFT-LCD에 사용되는 게이트 및 데이터 배선 등으로 이용하기 어려운 실정이다.Therefore, in order to reduce the RC signal delay, which is essential for the large-sized TFT-LCD, low-resistance material development is essential, and chromium (Cr resistivity: 12.7 × 10 -8 8m) and molybdenum ( Mo resistivity: 5 x 10 -8 mm, aluminum (Al resistivity: 2.65 x 10 -8 mm) and alloys thereof are difficult to use for gate and data wiring used in large-sized TFT-LCDs.
이와 같은 배경하에서, 새로운 저저항 금속막 중 하나인 구리막에 대한 관심이 높다. 구리막은 알루미늄막이나 크롬막 보다 저항이 현저하게 낮고 환경적으로도 큰 문제가 없는 장점이 있는 것으로 알려지고 있기 때문이다. 한편, 구리막을 포함하는 다중 금속막에 대한 연구가 진행되고 있으며, 그 중에서 특히 각광받은 물질이 구리-티타늄막이었다. 이 구리-티타늄 이중막에 대해서는 종래에 알려진 식각액이 존재하고 새롭게 많은 식각액이 발표되고 있으나, 티타늄막의 특수한 화학적 성질로 인하여 플루오르 이온이 존재하지 않으면 식각이 되지 않는 단점을 가지고 있다. 식각액 내에 플루오르 이온이 포함되어 있으면, 유리 기판 및 각종 실리콘 층 (반도체층과 실리콘 질화막으로 이루어진 패시베이션층)도 함께 식각되어 공정상에서 불량이 날 수 있는 요소가 많이 존재한다. Under such a background, there is a high interest in a copper film, which is one of the new low resistance metal films. This is because the copper film is known to have an advantage that the resistance is significantly lower than that of the aluminum film or the chromium film and that there is no big problem in the environment. On the other hand, research on a multi-metal film including a copper film is in progress, and among them, a particularly popular material is copper-titanium film. The copper-titanium double layer has a known etching liquid and many new etching liquids have been published. However, due to the special chemical properties of the titanium film, the etching of the copper-titanium double layer does not occur unless fluorine ions are present. When fluorine ions are included in the etchant, the glass substrate and various silicon layers (passivation layer composed of a semiconductor layer and a silicon nitride film) are also etched and there are many elements that may cause defects in the process.
그러나, 종래의 구리막 또는 구리합금막의 식각액 조성물은 주산화제로서 과산화수소수를 사용하고 있으며, 과산화수소수는 일반적으로 메탈(metal)이 포함되면, 메탈에 의해 하기의 반응식과 같은 분해반응이 야기되어 불안정한 상태가 된 다.However, the etching liquid composition of the conventional copper film or copper alloy film uses hydrogen peroxide water as the main oxidant, and hydrogen peroxide water is generally unstable due to the decomposition reaction caused by the metal, such as the metal (metal) It becomes a state.
Cu + 2H2O2 → Cu2 + + 2H2O + O2↑Cu + 2H 2 O 2 → Cu 2 + + 2H 2 O + O 2 ↑
또한, 구리막 식각액으로 옥손(oxone)을 포함하는 식각액이 제안된 바 있으나, 옥손 자체가 가지는 불안정성과, 에칭 속도가 느리다는 단점이 있었다.In addition, although an etchant including oxone has been proposed as a copper film etchant, there are disadvantages in that inoxone itself has a low etching rate.
이에, 본 발명자들은 상기한 문제점을 해결하고자 예의 노력한 결과, 종래 구리막 또는 구리 합금막 식각액에 사용되어온 과산화수소를 포함하지 않고, 과황산암모늄, 아미노기와 카르복시기를 포함하는 첨가제, 질소를 포함하는 첨가제 및 탈이온수로 이루어진 식각액을 구리막 또는 구리 합금막에 대한 식각에 사용한 결과, 식각 프로파일이 우수하고 또한 식각 잔사가 발생하지 않음을 발견하여 본 발명을 완성하였다.Accordingly, the present inventors have made efforts to solve the above problems, and as a result, additives containing ammonium persulfate, an amino group and a carboxyl group, an additive containing nitrogen, An etching solution made of deionized water was used to etch the copper film or the copper alloy film, and as a result, the present inventors found that the etching profile was excellent and no etching residues occurred.
따라서, 본 발명의 목적은 구리막 또는 구리 합금막의 식각에 사용하였을 때, 식각 잔사가 발생하지 않으며, 우수한 식각 프로파일을 나타내는, 습식 식각에 유용한 식각액 및 이를 사용하는 액정표시장치용 어레이 기판의 제조 방법을 제공하는 것이다. Accordingly, an object of the present invention is that when used in etching a copper film or a copper alloy film, no etching residue occurs, and exhibits an excellent etching profile, and an etchant useful for wet etching and a method of manufacturing an array substrate for a liquid crystal display device using the same. To provide.
상기 목적의 달성을 위하여, 본 발명은,In order to achieve the above object, the present invention,
A) 과황산암모늄(Ammonium persulfate, APS), A) ammonium persulfate (APS),
B) 아미노기와 카르복시기를 포함하는 첨가제, B) an additive comprising an amino group and a carboxyl group,
C) 질소를 포함하는 첨가제 및 C) additives comprising nitrogen and
D) 탈이온수D) deionized water
를 포함하는 구리막 또는 구리 합금막의 식각액 조성물을 제공한다.It provides an etching solution composition of a copper film or a copper alloy film comprising a.
보다 상세하게는, 본 발명은 조성물 총중량에 대하여, More specifically, the present invention relates to the total weight of the composition,
A) 과황산암모늄 1 내지 20 중량%, A) 1 to 20% by weight of ammonium persulfate,
B) 아미노기와 카르복시기를 포함하는 첨가제 0.1 내지 10 중량%, B) 0.1 to 10% by weight of an additive comprising an amino group and a carboxyl group,
C) 질소를 포함하는 첨가제 0.1 내지 5 중량%, 및 C) 0.1 to 5% by weight of an additive comprising nitrogen, and
D) 전체 조성물 총중량인 100 중량%가 되도록 하는 잔량의 탈이온수D) Residual deionized water to reach 100% by weight of the total composition weight
로 구성되는 구리막 또는 구리 합금막의 식각액 조성물을 제공한다.It provides an etching liquid composition of a copper film or a copper alloy film composed of.
또한, 본 발명은,In addition, the present invention,
Ⅰ) 기판 상에 구리막 또는 구리합금막을 형성하는 단계;I) forming a copper film or a copper alloy film on the substrate;
Ⅱ) 상기 구리막 또는 구리합금막 상에 선택적으로 광반응 물질을 남기는 단계; 및II) selectively leaving a photoreactive material on the copper film or copper alloy film; And
Ⅲ) 본 발명의 식각액 조성물을 사용하여 상기 구리막 또는 구리합금막을 식각하는 단계를 포함하는 구리막 또는 구리합금막의 식각방법을 제공한다.III) An etching method of a copper film or a copper alloy film comprising etching the copper film or the copper alloy film using the etching solution composition of the present invention.
또한, 본 발명은, In addition, the present invention,
a) 기판 상에 게이트 전극을 형성하는 단계;a) forming a gate electrode on the substrate;
b) 상기 게이트 전극을 포함한 기판 상에 게이트 절연층을 형성하는 단계;b) forming a gate insulating layer on the substrate including the gate electrode;
c) 상기 게이트 절연층 상에 반도체층을 형성하는 단계;c) forming a semiconductor layer on the gate insulating layer;
d) 상기 반도체층 상에 소스 및 드레인 전극을 형성하는 단계; 및d) forming source and drain electrodes on the semiconductor layer; And
e) 상기 드레인 전극에 연결된 화소 전극을 형성하는 단계e) forming a pixel electrode connected to the drain electrode
를 포함하는 액정표시장치용 어레이 기판의 제조 방법에 있어서, 상기 (a) 단계에서는 기판 상에 구리막 또는 구리 합금막을 형성한 후, 본 발명의 식각액 조성물로 식각하여 게이트 전극을 형성하고, 상기 (d) 단계에서는 반도체층 상에 구리막 또는 구리 합금막을 형성한 후, 본 발명의 식각액 조성물로 식각하여 소스 및 드레인 전극을 형성하는 것을 특징으로 하는 액정표시장치용 어레이 기판의 제조 방법을 제공한다.In the method of manufacturing an array substrate for a liquid crystal display device comprising a, in the step (a) after forming a copper film or a copper alloy film on the substrate, by etching with the etchant composition of the present invention to form a gate electrode, the ( In the step d), a copper film or a copper alloy film is formed on the semiconductor layer, and then the source and drain electrodes are formed by etching with the etchant composition of the present invention, thereby providing a method of manufacturing an array substrate for a liquid crystal display device.
이하에서는 본 발명에 대해 상세히 설명한다.Hereinafter, the present invention will be described in detail.
본 발명은 조성물 총중량에 대하여, 과황산암모늄 1 내지 20 중량%, 아미노 기와 카르복시기를 포함하는 첨가제 0.1 내지 10 중량%, 질소를 포함하는 첨가제 0.1 내지 5 중량% 및 전체 조성물 총중량인 100 중량%가 되도록 하는 잔량의 탈이온수로 구성되는 구리막 또는 구리 합금막의 식각액 조성물을 제공한다.The present invention is 1 to 20% by weight of ammonium persulfate, 0.1 to 10% by weight of additives containing amino groups and carboxyl groups, 0.1 to 5% by weight of additives containing nitrogen and 100% by weight of the total composition. Of copper film or copper alloy film It provides an etchant composition.
본 발명의 식각액에 포함되는 과황산암모늄((NH4)2S2O8)은 구리막 또는 구리 합금막을 식각하는 주성분으로서, 본 발명의 식각액 조성물 총중량에 대하여 1 내지 20 중량%로 포함되는 것이 바람직하며, 1 중량% 미만이 포함되는 경우에는 식각 속도가 너무 느려져 언에치(unetch)가 발생될 수 있고, 20 중량%를 초과하여 포함되는 경우에는 식각속도가 너무 빠르기 때문에 공정에서 제어하기 어려운 단점이 있다.Ammonium persulfate ((NH 4 ) 2 S 2 O 8 ) included in the etchant of the present invention is a main component for etching the copper film or the copper alloy film, which is included in an amount of 1 to 20% by weight based on the total weight of the etchant composition of the present invention. Preferably, when less than 1% by weight of the etching rate is too slow unetch (unetch) may occur, when contained in more than 20% by weight is difficult to control in the process because the etching rate is too fast There are disadvantages.
본 발명의 식각액에 포함되는 아미노기와 카르복시기를 포함하는 첨가제는 구리막 또는 구리 합금막을 식각하는 주성분으로서, 구리막 또는 구리 합금막이 식각될 수 있는 적절한 pH 환경을 만들어 주는 역할을 하며, 조성물 중 0.1 내지 10 중량%로 포함되는 것이 바람직하다. 만약 아미노기와 카르복시기를 포함하는 첨가제의 함량이 0.1 중량% 미만이면 구리막 또는 구리 합금막은 식각되지 않으며, 10 중량%를 초과하면 pH가 낮아져서 식각 속도가 제어하기 힘들 정도로 빨라지게 되어 사이드 에칭(side etch)이 많아지게 되기 때문에 공정에 적용하기 어렵게 된다. 구리막 또는 구리 합금막이 식각될 수 있는 적절한 pH는 0.5~4.5이다.The additive including the amino group and the carboxyl group included in the etchant of the present invention serves as a main component for etching the copper film or the copper alloy film, and serves to create an appropriate pH environment in which the copper film or the copper alloy film can be etched. It is preferably included in 10% by weight. If the content of the additive containing the amino group and the carboxyl group is less than 0.1 wt%, the copper film or the copper alloy film is not etched. If the content of the additive exceeds 10 wt%, the pH is lowered, so that the etching rate is uncontrollably fast and side etch. ), It becomes difficult to apply to the process. The suitable pH at which the copper film or copper alloy film can be etched is 0.5 to 4.5.
본 발명의 아미노기와 카르복시기를 포함하는 첨가제는, 반도체 공정용의 순도를 가져 금속 불순물이 ppb 수준 이하인 것이면 특별히 한정되지 않고 사용될 수 있다. The additive containing the amino group and the carboxyl group of the present invention can be used without particular limitation as long as it has purity for the semiconductor process and the metal impurity is below the ppb level.
여기서, 상기 아미노기 및 카르복시기를 가지는 수용성 화합물은 알라닌(alanine) 계열, 아미노부티르산(aminobutyric acid) 계열, 글루탐산(glutamic acid) 계열, 글리신(glycine) 계열, 이미노디아세트산(iminodiacetic acid) 계열, 니트릴로트리아세트산(nitrilotriacetic acid) 계열 및 사르코신(sarcosine) 계열의 화합물을 포함하는 군으로부터 선택되는 어느 하나, 바람직하게는 이미노디아세트산 계열의 화합물인 것이 바람직하다.Here, the water-soluble compound having an amino group and a carboxyl group may be alanine series, aminobutyric acid series, glutamic acid series, glycine series, iminodiacetic acid series, nitrilotriacetic acid, or the like. (nitrilotriacetic acid) and sarcosine (sarcosine) is preferably any one selected from the group comprising a compound, preferably imino diacetic acid-based compound.
본 발명의 식각액에 포함되는, 질소를 포함하는 첨가제는 구리막 또는 구리 합금막의 식각 속도를 조절하며 패턴의 시디 로스를 줄여주어 공정상의 마진을 높이는 역할을 한다. 이 성분의 역할은 매우 중요하며, 본 발명의 조성물에 0.1 내지 5 중량%로 포함되는 것이 바람직하다. 0.1 중량% 미만으로 포함되는 경우 구리막 또는 구리 합금막의 식각 속도가 매우 빨라져서 사이드에칭이 많아지는 단점이 있고, 5 중량%를 초과하여 포함되는 경우 식각 속도가 매우 느려져서 언에치가 발생할 가능성이 있다. 따라서, 상기 첨가제 1의 함량이 0.1 내지 5 중량% 범위를 벗어나는 경우, 식각 속도의 조절도 어려울 뿐만 아니라, 원하는 패턴의 폭을 얻을 수 없어 불량이 발생할 확률이 크고 공정 마진이 적어 양산 시 문제점이 생길 소지가 다분하다.The additive containing nitrogen, included in the etchant of the present invention, controls the etching rate of the copper film or the copper alloy film, and serves to increase the process margin by reducing the side loss of the pattern. The role of this component is very important and is preferably included in the composition of the present invention in 0.1 to 5% by weight. When included in less than 0.1% by weight, the etching speed of the copper film or copper alloy film is very fast, there is a disadvantage that the side etching is increased, and when included in more than 5% by weight, the etching rate is very slow, there is a possibility that the unetched. Therefore, when the content of the
상기 질소를 포함하는 첨가제는 특별히 한정되지 않고 다양한 종류가 사용될 수 있으며, 아미노테트라졸(aminotetrazole), 이미다졸 (imidazole), 인돌 (indole), 피라졸 (pyrazole), 피리딘(pyridine), 피롤 (pyrrole), 벤조트리아졸 및 그 외 수용성 시클릭 아민 화합물 (cyclicamine compound)을 포함하는 군으로부터 선택되는 어느 하나인 것이 바람직하다.The nitrogen-containing additive is not particularly limited and may be used in a variety of types, aminotetrazole, imidazole, indole, pyrazole, pyridine, pyrrole ), Benzotriazole, and other water-soluble cyclic amine compounds.
탈이온수는 반도체 공정용을 사용하고, 바람직하게는 18MΩ/㎝ 이상의 물을 사용한다. Deionized water is used for a semiconductor process, Preferably water of 18 MPa / cm or more is used.
상기의 과황산암모늄, 아미노기와 카르복시기를 포함하는 첨가제 및 질소를 포함하는 첨가제는 통상적으로 공지된 방법에 의해서 제조 가능하고, 반도체 공정용의 순도를 가지는 것이 바람직하다. The above-mentioned ammonium persulfate, the additive containing an amino group and a carboxyl group, and the additive containing nitrogen can be manufactured by a well-known method normally, and it is preferable to have the purity for a semiconductor process.
또한, 본 발명의 식각액 조성물에는 통상적으로 들어가는 다른 첨가제를 사용할 수 있다.In addition, it is possible to use other additives usually used in the etching solution composition of the present invention.
또한, 본 발명은,In addition, the present invention,
Ⅰ) 기판 상에 구리막 또는 구리합금막을 형성하는 단계;I) forming a copper film or a copper alloy film on the substrate;
Ⅱ) 상기 구리막 또는 구리합금막 상에 선택적으로 광반응 물질을 남기는 단계; 및II) selectively leaving a photoreactive material on the copper film or copper alloy film; And
Ⅲ) 본 발명의 식각액 조성물을 사용하여 상기 구리막 또는 구리합금막을 식각하는 단계를 포함하는 구리막 또는 구리합금막의 식각방법을 제공한다.III) An etching method of a copper film or a copper alloy film comprising etching the copper film or the copper alloy film using the etching solution composition of the present invention.
여기서, 상기 광반응 물질은 통상적인 포토레지스트 물질인 것이 바람직하며, 통상적인 노광 및 현상 공정에 의해 선택적으로 남겨질 수 있다.Here, the photoreactive material is preferably a conventional photoresist material, which can be selectively left by conventional exposure and development processes.
또한, 본 발명은, In addition, the present invention,
a) 기판 상에 게이트 전극을 형성하는 단계; a) forming a gate electrode on the substrate;
b) 상기 게이트 전극을 포함한 기판 상에 게이트 절연층을 형성하는 단계; b) forming a gate insulating layer on the substrate including the gate electrode;
c) 상기 게이트 절연층 상에 반도체층을 형성하는 단계; c) forming a semiconductor layer on the gate insulating layer;
d) 상기 반도체층 상에 소스 및 드레인 전극을 형성하는 단계; 및 d) forming source and drain electrodes on the semiconductor layer; And
e) 상기 드레인 전극에 연결된 화소 전극을 형성하는 단계를 포함하는 액정표시장치용 어레이 기판의 제조 방법에 있어서, 상기 (a) 단계에서는 기판 상에 구리막 또는 구리 합금막을 형성한 후, 본 발명의 식각액 조성물로 식각하여 게이트 전극을 형성하고, 상기 (d) 단계에서는 반도체층 상에 구리막 또는 구리 합금막을 형성한 후, 본 발명의 식각액 조성물로 식각하여 소스 및 드레인 전극을 형성하는 것을 특징으로 하는 액정표시장치용 어레이 기판의 제조 방법을 제공한다.e) a method of manufacturing an array substrate for a liquid crystal display device, the method comprising: forming a pixel electrode connected to the drain electrode, wherein in step (a), after forming a copper film or a copper alloy film on the substrate, Forming a gate electrode by etching with an etchant composition, and in the step (d), after forming a copper film or a copper alloy film on the semiconductor layer, the source and drain electrodes are formed by etching with the etchant composition of the present invention. A method of manufacturing an array substrate for a liquid crystal display device is provided.
본 발명에 따른 액정표시장치용 어레이 기판의 제조방법에 있어서, 상기 a) 단계는 a1) 기상증착법이나 스퍼터링(sputtering)법을 이용하여 기판 상에 구리막 또는 구리합금막을 증착시키는 단계; 및 a2) 상기 구리막 또는 구리합금막을 본 발명의 식각액으로 식각하여 패터닝하여 게이트 전극을 형성하는 단계를 포함한다. 여기서, 구리막 또는 구리합금막을 기판 상에 형성하는 방법은 상기 예시된 것으로만 한정되는 것은 아니다.In the method of manufacturing an array substrate for a liquid crystal display device according to the present invention, the step a) comprises the steps of: a1) depositing a copper film or a copper alloy film on the substrate by using a vapor deposition method or a sputtering method; And a2) etching and patterning the copper film or the copper alloy film with the etchant of the present invention to form a gate electrode. Here, the method of forming a copper film or a copper alloy film on a board | substrate is not limited only to what was illustrated above.
본 발명에 따른 액정표시장치용 어레이 기판의 제조방법에 있어서, 상기 b) 단계에서는 기판 상에 형성된 게이트 전극 상부에 질화실리콘(SiNX)을 증착하여 게이트 절연층을 형성한다. 여기서, 게이트 절연층의 형성시 사용되는 물질은 질화실리콘(SiNx)에만 한정되는 것은 아니고, 산화실리콘(SiO2)을 포함하는 각종 무기 절연물질 중에서 선택된 물질을 사용하여 게이트 절연층을 형성할 수도 있다.In the method of manufacturing an array substrate for a liquid crystal display device according to the present invention, in step b), silicon nitride (SiN X ) is deposited on the gate electrode formed on the substrate to form a gate insulating layer. Here, the material used for forming the gate insulating layer is not limited to silicon nitride (SiN x ), and the gate insulating layer may be formed using a material selected from various inorganic insulating materials including silicon oxide (SiO 2 ). have.
본 발명에 따른 액정표시장치용 어레이 기판의 제조방법에 있어서, 상기 c) 단계에서는 게이트 절연층 상에 화학기상증착법(CVD)을 이용하여 반도체층을 형성한다. 즉, 순차적으로 엑티브층(active layer)과 오믹콘택층(ohmic contact layer)을 형성한 후, 건식 식각을 통해 패터닝한다. 여기서, 엑티브층은 일반적으로 순수한 비정질 실리콘(a-Si:H)으로 형성하고, 오믹콘텍층은 불순물이 포함된 비정질 실리콘(n+a-Si:H)으로 형성한다. 이러한 엑티브층과 오믹콘텍층을 형성할 때 화학기상증착법(CVD)을 이용할 수 있지만, 이에만 한정되는 것은 아니다.In the method of manufacturing an array substrate for a liquid crystal display device according to the present invention, in the step c), a semiconductor layer is formed on the gate insulating layer by chemical vapor deposition (CVD). In other words, the active layer and the ohmic contact layer are sequentially formed and then patterned by dry etching. Here, the active layer is generally formed of pure amorphous silicon (a-Si: H), and the ohmic contact layer is formed of amorphous silicon (n + a-Si: H) containing impurities. Chemical vapor deposition (CVD) may be used to form the active layer and the ohmic contact layer, but is not limited thereto.
본 발명에 따른 액정표시장치용 어레이 기판의 제조방법에 있어서, 상기 d) 단계는 d1) 상기 반도체층 상에 소스 및 드레인 전극을 형성하는 단계; 및 d2) 상기 소스 및 드레인 전극 상에 절연층을 형성하는 단계를 포함한다. 상기 d1) 단계에서는 오믹콘텍층 위에 스퍼터링법을 통해 구리 및 구리합금막을 증착하고 본 발명의 식각액으로 식각하여 소스 전극과 드레인 전극을 형성한다. 여기서, 구리막 또는 구리합금막을 기판 상에 형성하는 방법은 상기 예시된 것으로만 한정되는 것은 아니다. 상기 d2) 단계에서는 소스 전극과 드레인 전극 상에 질화 실리콘(SiNx)과 산화실리콘(SiO2)을 포함하는 무기절연그룹 또는 벤조사이클로부텐(BCB)과 아크릴(acryl)계 수지(resin)를 포함한 유기절연물질 그룹 중 선택하여 단층 또는 이중층으로 절연층을 형성한다. 절연층의 재료는 상기 예시된 것으로만 한정되는 것은 아니다.In the method of manufacturing an array substrate for a liquid crystal display device according to the present invention, the step d) comprises: d1) forming source and drain electrodes on the semiconductor layer; And d2) forming an insulating layer on the source and drain electrodes. In step d1), a copper and a copper alloy film are deposited on the ohmic contact layer by sputtering, and then etched with an etchant of the present invention to form a source electrode and a drain electrode. Here, the method of forming a copper film or a copper alloy film on a board | substrate is not limited only to what was illustrated above. In step d2), an inorganic insulating group including silicon nitride (SiN x ) and silicon oxide (SiO 2 ) or a benzocyclobutene (BCB) and an acrylic resin are included on the source electrode and the drain electrode. The insulating layer may be formed of a single layer or a double layer by selecting from a group of organic insulating materials. The material of the insulating layer is not limited to only those exemplified above.
본 발명에 따른 액정표시장치용 어레이 기판의 제조방법에 있어서, 상기 e) 단계에서는 상기 드레인 전극에 연결된 화소 전극을 형성한다. 예컨대, 스퍼터링법을 통해 인듐산화막[ITO(indium tin oxide) 또는 IZO(indium zinc oxide)]과 같은 투명한 도전물질을 증착하고, 인듐산화막 전용 식각액 조성물로 식각하여, 화소 전극을 형성한다. 상기 인듐 산화막을 증착하는 방법은 스퍼터링법으로만 한정되는 것은 아니다.In the method of manufacturing an array substrate for a liquid crystal display device according to the present invention, in step e), a pixel electrode connected to the drain electrode is formed. For example, a transparent conductive material such as an indium tin oxide (ITO) or an indium zinc oxide (IZO) is deposited through a sputtering method, and the pixel electrode is formed by etching with an etchant composition dedicated to the indium oxide film. The method of depositing the indium oxide film is not limited only to the sputtering method.
이와 같은, 액정표시장치용 어레이 기판의 제조방법에 있어서, 본 발명에 의한 식각액 조성물을 사용하여 상기 게이트 전극을 형성하는 a) 단계를 진행하게 되면, 다량의 게이트 기판을 식각할 수 있어 공정 비용이 크게 절감되며, 식각액 교체 회수를 줄여 공정을 단순화할 수 있다.In such a method of manufacturing an array substrate for a liquid crystal display device, when the a) step of forming the gate electrode using the etchant composition according to the present invention is performed, a large amount of the gate substrate can be etched, thereby increasing the process cost. Significant savings can be achieved and the process can be simplified by reducing the number of etchant changes.
또한, 액정표시장치용 어레이 기판의 제조방법에 있어서, 본 발명에 의한 식각액 조성물을 사용한 d) 단계 식각공정시, 식각 속도가 빠르면서도 소스 및 드레인 전극 하측에 위치하는 오믹콘텍층에 대한 어택을 최소화시킬 수 있음에 따라, TFT-LCD의 구동 특성을 향상시킬 수 있는 우수한 액정표시장치용 어레이 기판을 제조할 수 있고, 액정표시장치용 어레이 기판의 생산성을 향상시킬 수 있게 된다. In addition, in the method of manufacturing an array substrate for a liquid crystal display device, during the d) step etching process using the etchant composition according to the present invention, the etching rate is high and the attack on the ohmic contact layer under the source and drain electrodes is minimized. As a result, it is possible to manufacture an excellent array substrate for a liquid crystal display device capable of improving the driving characteristics of the TFT-LCD, and to improve the productivity of the array substrate for a liquid crystal display device.
상기 구리막 또는 구리 합금막은 TFT-LCD의 게이트 전극의 배선 및 데이터라인을 구성하는 소스/드레인 전극의 배선을 형성하는 것을 특징으로 한다. TFT-LCD의 소스/드레인 배선은 특히 그 저항이 문제되는 배선이므로, 구리막 또는 구리 합금막을 사용하고, 본 발명에 따른 식각액으로 용이하게 식각하여 TFT-LCD의 대형화를 이룰 수 있다.The copper film or copper alloy film is characterized in that the wiring of the gate electrode of the TFT-LCD and the wiring of the source / drain electrodes constituting the data line are formed. Since the source / drain wiring of the TFT-LCD is particularly a wiring whose resistance is a problem, a large size of the TFT-LCD can be achieved by easily etching with an etchant according to the present invention by using a copper film or a copper alloy film.
본 발명의 식각액 조성물을 사용하여 구리막 또는 구리 합금막을 식각하는 경우, 종래에 과산화수소수를 주산화제로 사용하는 조성물과 달리 불안정성 문제가 없으며, 식각 잔사가 발생하지 아니하여 전기적인 쇼트나 배선의 불량, 휘도의 감소 등의 문제가 발생하지 않으며, 게이트 전극 및 게이트 배선, 데이터 전극 및 데이터 배선을 일괄 식각하는 것이 가능하게 되어 공정이 매우 단순화되고 공정수율이 극대화 되는 효과를 얻을 수 있다.When etching the copper film or the copper alloy film using the etchant composition of the present invention, there is no instability problem, unlike the composition using a conventional hydrogen peroxide solution as the main oxidant, and no electrical residue or wiring defect due to the etching residue does not occur It is possible to etch the gate electrode, the gate wiring, the data electrode, and the data wiring in a batch, thereby reducing the luminance and the like, and thus, the process may be greatly simplified and the process yield may be maximized.
이하, 본 발명을 실시예 및 비교예를 이용하여 더욱 상세하게 설명한다. 그러나 하기 실시예 및 비교예는 본 발명을 예시하기 위한 것으로서 본 발명은 하기 실시예 및 비교예에 의해 한정되지 않고 다양하게 수정 및 변경될 수 있다. Hereinafter, the present invention will be described in more detail using examples and comparative examples. However, the following Examples and Comparative Examples are intended to illustrate the present invention, the present invention is not limited to the following Examples and Comparative Examples can be variously modified and changed.
실시예Example 1 내지 3 1 to 3
하기 표 1 에 기재된 전체 조성물의 총중량에 대한 조성비와 같이, 과황산암모늄, 이미노디아세트산, 아미노테트라졸 및 탈이온수를 포함하는 식각액을 각각 10 kg이 되도록 제조하였다. 시험편은 스퍼터링법으로 유리 기판 상에 구리막을 증착한 것을 사용하였다. Like the composition ratio with respect to the total weight of the total composition described in Table 1, an etching solution containing ammonium persulfate, imino diacetic acid, aminotetrazole and deionized water was prepared to be 10 kg each. The test piece used what deposited the copper film on the glass substrate by the sputtering method.
분사식 식각 방식의 실험장비 (모델명: ETCHER(TFT), K.C.Tech사) 내에 제조된 식각액을 넣고 온도를 40 ℃ 로 설정하여 가온한 후, 온도가 40±0.1℃에 도달하였을 때 식각 공정을 수행하였다. 총 식각 시간은 엔드포인트 검출(End Point Detection, EPD)을 기준으로 하여 오버 에치(Over Etch) 50%를 주어 실시하였다. 기판을 넣고 분사를 시작하여 식각이 다 되면 꺼내어 탈이온수로 세정한 후, 열풍건조장치를 이용하여 건조하고, 포토레지스트 박리기(PR stripper)를 이용하여 포토레지스트를 제거하였다. 세정 및 건조 후 전자주사현미경 (SEM; 모델명: S-4700, HITACHI사 제조)을 이용하여 사이드에칭 (Side Etch) 및 식각 잔류물의 발생 정도의 식각 특성을 평가하여 하기 표 1에 나타내었으며, 실시예 1의 식각액 조성물을 이용한 구리막의 식각 후 기판 도면 (도 1) 및 스트립 후 기판 표면(도 2)을 각각 주사전자현미경을 이용해 사진을 찍었다.Etching solution prepared in a spray etching test equipment (model name: ETCHER (TFT), KCTech Co., Ltd.) was added to warm the temperature set to 40 ℃, the etching process was performed when the temperature reached 40 ± 0.1 ℃ . The total etching time was performed by giving 50% of the over etch based on End Point Detection (EPD). The substrate was sprayed, and when the etching was completed, the substrate was ejected, removed, washed with deionized water, dried using a hot air dryer, and removed using a photoresist stripper. After washing and drying, the etching characteristics of the side etching (Side Etch) and the degree of etching residues were evaluated by using an electron scanning microscope (SEM; model name: S-4700, manufactured by HITACHI), and are shown in Table 1 below. After the etching of the copper film using the etchant composition of Figure 1 (Fig. 1) and the strip substrate after the substrate surface (Fig. 2) were photographed using a scanning electron microscope, respectively.
표 1, 도 1 및 도 2에 나타난 바와 같이, 본 발명에 따른 실시예의 식각액 조성물은 식각 프로파일이 우수하고(도 1 참조), 식각 잔사가 없는(도 2 참조) 양호한 식각특성을 갖는 것을 확인할 수 있었다.As shown in Table 1, Figure 1 and Figure 2, the etching liquid composition of the embodiment according to the present invention can be confirmed that the etching profile has a good etching characteristics (see Figure 1), there is no etching residue (see Figure 2) there was.
비교예Comparative example 1 및 2 1 and 2
조성비를 하기 표 2에 기재한 바와 같이 하는 것을 제외하고는, 실시예와 동일한 방식으로 식각액을 제조하였으며, 동일한 방식으로 식각 공정을 수행하여 하기 표 2에 각각의 식각 특성을 평가하여 나타내었다.An etching solution was prepared in the same manner as in Example, except that the composition ratio was set forth in Table 2 below, and the etching process was performed in the same manner to evaluate each etching characteristic in Table 2 below.
표 2에 나타난 바와 같이, 질소를 포함하는 첨가제를 함유하지 않는 비교예 1은, 실시예에 비해 사이드에칭이 많아져, 식각 속도의 조절이 곤란한 단점이 있는 것으로 나타났다. 또한, 비교예 2와 같이 APS를 포함하지 않는 식각액을 사용하는 경우, 식각을 수행할 수 없음을 확인할 수 있었다. As shown in Table 2, Comparative Example 1, which does not contain an additive containing nitrogen, was found to have a disadvantage in that side etching was increased compared to Examples, and it was difficult to control the etching rate. In addition, when using an etchant containing no APS as in Comparative Example 2, it was confirmed that the etching can not be performed.
도 1은 본 발명의 실시예 1에 따른 식각액 조성물을 이용하여 구리막을 식각한 결과를 나타낸 주사전자현미경 사진이고,1 is a scanning electron micrograph showing a result of etching a copper film using the etchant composition according to Example 1 of the present invention,
도 2는 본 발명의 상기 도 1의 기판의 식각 후 스트립한 기판의 표면을 나타내는 주사전자현미경 사진이다.FIG. 2 is a scanning electron micrograph showing a surface of a substrate stripped after etching the substrate of FIG.
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| KR20110031796A (en) * | 2009-09-21 | 2011-03-29 | 동우 화인켐 주식회사 | Manufacturing method of an array substrate for liquid crystal display |
| KR20110032156A (en) * | 2009-09-22 | 2011-03-30 | 동우 화인켐 주식회사 | Manufacturing method of an array substrate for liquid crystal display |
| KR20110128032A (en) * | 2010-05-20 | 2011-11-28 | 동우 화인켐 주식회사 | Manufacturing method of an array substrate for liquid crystal display |
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