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KR20080095602A - Method of forming a contact hole in a semiconductor device - Google Patents

Method of forming a contact hole in a semiconductor device Download PDF

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Publication number
KR20080095602A
KR20080095602A KR1020070040326A KR20070040326A KR20080095602A KR 20080095602 A KR20080095602 A KR 20080095602A KR 1020070040326 A KR1020070040326 A KR 1020070040326A KR 20070040326 A KR20070040326 A KR 20070040326A KR 20080095602 A KR20080095602 A KR 20080095602A
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KR
South Korea
Prior art keywords
forming
photoresist pattern
contact hole
hard mask
pattern
Prior art date
Application number
KR1020070040326A
Other languages
Korean (ko)
Inventor
심귀황
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070040326A priority Critical patent/KR20080095602A/en
Publication of KR20080095602A publication Critical patent/KR20080095602A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, wherein after forming a spacer on a sidewall of a photoresist pattern, a photoresist pattern is removed to form a hard mask pattern using the spacer, thereby providing a mask having a pitch less than or equal to the resolution of exposure equipment Disclosed is a method for forming a contact hole using.

Description

Method of forming a contact hole in a semiconductor device

1 to 5 are cross-sectional views and plan views of devices for describing a method for forming contact holes in a semiconductor device according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100 semiconductor substrate 101 gate pattern

102 insulating film 103 hard mask film

104: photoresist pattern 105: spacer insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a contact hole in a semiconductor device, and more particularly to a method of forming a contact hole having a fine pattern size.

In general, a semiconductor device includes a plurality of unit devices therein. As semiconductor devices become highly integrated, semiconductor devices must be formed at a high density on a predetermined cell area, thereby decreasing the size of unit devices, for example, transistors and capacitors. In particular, in semiconductor memory devices such as DRAM (Dynamic Random Access Memory), as the design rule is reduced, the size of semiconductor devices formed inside the cell is gradually decreasing. In fact, in recent years, the minimum line width of the semiconductor DRAM device is formed to 0.1㎛ or less, even up to 60nm is required. Therefore, many difficulties have arisen in the manufacturing process of the semiconductor devices forming the cell.

In the case of applying a photolithography process using ArF (argon fluoride) exposure having a wavelength of 193 nm in a semiconductor device having a line width of 60 nm or less, the etching process is performed in accordance with the conventional etching process concept (exact pattern formation and vertical etching profile, etc.). There is a need for additional requirements of suppression of deformation of the resulting photoresist. Accordingly, when manufacturing a semiconductor device having a thickness of 60 nm or less, the development of process conditions for simultaneously satisfying existing requirements and new requirements of pattern deformation prevention has become a major problem in terms of etching.

In order to form a fine contact hole of 100 nm or less beyond the limit resolution of the exposure equipment, a conventional method is to form a contact hole photoresist pattern and then heat it above the glass transition temperature of the photoresist material to cause flow. A method of forming a small contact hole pattern and a method of reducing the size of a contact hole by a process using a Resist Enhancement Lithography Assisted by Chemical Shrink (RELACS) material are known (Laura J. Peters, "Resist Join the Sub-λ Revolution). ", Semiconductor International, Sep. 1999; Toshiyuki Toyoshima," 0.1 μm Level contact hole pattern formation with KrF lithography by Resist Enhancement Lithography Assisted by Chemical Shrink ", IEEE, 1998).

In addition to the above methods, the development of a method for forming a fine contact hole beyond the limit resolution of the exposure equipment is required.

The technical problem to be achieved by the present invention is to form a hard mask pattern using a spacer by forming a spacer on the photoresist pattern sidewalls and then removing the photoresist pattern, thereby forming a contact hole using a mask having a pitch of less than the resolution of the exposure equipment To provide.

A method of forming a contact hole in a semiconductor device according to an embodiment of the present invention includes forming an insulating film, a hard mask film, and a photoresist pattern on a semiconductor substrate on which gate patterns are formed, and forming spacers on sidewalls of the photoresist pattern. Removing the photoresist pattern, performing an etching process using the spacers to pattern the hard mask layer, and etching the insulating layer using the patterned hard mask layer to form the gate pattern of the semiconductor substrate. Forming a contact hole through which the junction region between the exposed portions is exposed.

After the patterning of the hard mask layer, forming a photoresist pattern exposing a region including a region where the contact hole is to be formed in a bit line direction on the entire structure including the hard mask layer patterned before the contact hole forming step It further comprises a step.

The spacer may include forming an insulating film on a surface of the photoresist pattern, and performing an anisotropic etching process to remove the insulating film on the photoresist pattern.

The insulating film is formed of an SiO 2 film, and has a space ratio of 3: 1 between the width of the insulating film and the adjacent insulating film.

The insulating layer is formed by reacting oligomeric aminosiloxane with the photoresist pattern.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

1 to 5 are cross-sectional views and plan views of devices for describing a method for forming contact holes in a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, predetermined gate patterns 101 are formed on a semiconductor substrate 100, and then an insulating film is formed on the gate sidewalls. Thereafter, an insulating film 102 is formed over the entire structure including the gate patterns 101.

Thereafter, the hard mask film 103 is formed on the entire structure including the insulating film 102, the photoresist material is coated on the hard mask film 103, and then the photoresist pattern 105 is subjected to an exposure and development process. ). At this time, the photoresist pattern 105 preferably forms a ratio of lines and spaces under a condition of 1: 3.

2A and 2B, a spacer insulating layer 105 is formed on the sidewalls and the upper portion of the photoresist pattern 105. The spacer insulating film 105 is preferably formed of an SiO 2 film. The spacer insulating layer 105 is preferably formed by reacting an oligomeric aminosiloxane with the photoresist pattern 105.

3A and 3B, an anisotropic etching process is performed to remove the spacer insulating layer 105 formed on the photoresist pattern. That is, the spacer insulating film 105 is left on the photoresist pattern sidewalls. Thereafter, the photoresist pattern is removed. As a result, the spacer insulating layer 105 is formed in a fine pattern in which the ratio of lines and spaces is 1: 1.

Referring to FIG. 4A, an etching process using the spacer insulating layer 105 as an etching mask is performed to etch and pattern the hard mask layer 103.

As described above, when the hard mask pattern 103 is formed using the spacer insulating layer 105, for example, the hard mask pattern 103 having a pitch of 30 nm using an ASML 1400 ArF DRY device having a resolution capability of 60 nm may be used. Can be formed. That is, up to 2 times the pitch reduction effect can be obtained using the existing exposure equipment without the investment of exposure equipment.

Referring to FIG. 4B, after the photoresist material is coated on the entire structure, an exposure and etching process may be performed to include an area in which a subsequent contact hole is to be formed, and the insulating layer may be formed in the bit line direction (the horizontal direction in the drawing). 102 forms a photoresist pattern PR exposed.

Referring to FIG. 5, the exposed insulating layer 102 is etched to form contact holes to expose the junction regions of adjacent semiconductor substrates of the gate patterns 101.

In the above description, the present invention has been described taking the case of applying the gate etching process of the flash memory device as an example, but the present invention is a gate etching process and device isolation trench etching process of all semiconductor devices such as DRAM and SRAM. And it can be found that it can be applied to all the etching process required for semiconductor device manufacturing, such as contact etching process.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to an embodiment of the present invention, by forming a spacer on the sidewall of the photoresist pattern and then removing the photoresist pattern to form a hard mask pattern using the spacer, to form a hard mask pattern having a pitch of less than the exposure equipment resolution Can be.

Claims (6)

Forming an insulating film, a hard mask film, and a photoresist pattern on the semiconductor substrate on which the gate patterns are formed; Forming a spacer on sidewalls of the photoresist pattern; After removing the photoresist pattern, performing an etching process using the spacers to pattern the hard mask layer; And And forming a contact hole through which the junction region between the gate patterns of the semiconductor substrate is exposed by performing the insulating layer by an etching process using the patterned hard mask layer. The method of claim 1, After the hard mask layer is patterned, before the contact hole forming step. And forming a photoresist pattern exposing a region including a region where the contact hole is to be formed in a bit line direction on the entire structure including the patterned hard mask layer. The method of claim 1, Forming an insulating layer on a surface of the photoresist pattern; And And removing the insulating layer on the photoresist pattern by performing an anisotropic etching process. The method of claim 3, wherein And the insulating film is formed of a SiO 2 film. The method of claim 3, wherein And forming a 3: 1 space ratio between the width of the insulating film and the adjacent insulating film. The method of claim 3, wherein And the insulating layer is formed by reacting an oligomeric aminosiloxane with the photoresist pattern.
KR1020070040326A 2007-04-25 2007-04-25 Method of forming a contact hole in a semiconductor device KR20080095602A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070040326A KR20080095602A (en) 2007-04-25 2007-04-25 Method of forming a contact hole in a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070040326A KR20080095602A (en) 2007-04-25 2007-04-25 Method of forming a contact hole in a semiconductor device

Publications (1)

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KR20080095602A true KR20080095602A (en) 2008-10-29

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8309463B2 (en) 2009-11-20 2012-11-13 Hynix Semiconductor Inc. Method for forming fine pattern in semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8309463B2 (en) 2009-11-20 2012-11-13 Hynix Semiconductor Inc. Method for forming fine pattern in semiconductor device

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