KR20080040847A - Display device - Google Patents

Abstract

A display apparatus is provided to suppress the damage of transistors even when a gate-on voltage is applied for a long time by controlling the amplitude of clock signals supplied to the transistors. A display apparatus includes a substrate, plural gate lines(G1-Gn), and a gate driver(400). The gate lines which are formed on the substrate, deliver gate signals formed by gate on and off voltages to pixels. The gate driver, which is connected to the gate lines, generates the gate signals. The gate driver generates the gate signals based on first, second, third, and fourth clock signals. The amplitudes of the first and second clock signals are larger than the amplitudes of the third and fourth clock signals.

Description

Display device {DISPLAY DEVICE}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram of a gate driver according to another exemplary embodiment of the present invention.

FIG. 4 is an example of a circuit diagram of the j-th stage of the shift register for gate driver shown in FIG. 3; FIG.

5 is a waveform diagram showing a drive signal of a gate driver according to an embodiment of the present invention;

6 is a schematic layout view of first and second stages of a gate driver according to an embodiment of the present invention.

The present invention relates to a liquid crystal display device.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which field generating electrodes such as a pixel electrode and a common electrode are formed, and a liquid crystal layer interposed therebetween. Is applied to generate an electric field in the liquid crystal layer, thereby determining the orientation of the liquid crystal molecules of the liquid crystal layer and controlling the polarization of incident light to display an image.

The liquid crystal display also includes a switching element connected to each pixel electrode and a plurality of signal lines such as a gate line and a data line for controlling the switching element and applying a voltage to the pixel electrode. The gate line generates a gate signal generated by the gate driving circuit, the data line transfers the data voltage generated by the data driving circuit, and the switching element transfers the data voltage to the pixel electrode according to the gate signal.

The gate driving circuit and the data driving circuit are directly attached to the display panel in the form of a plurality of integrated circuit chips or attached to the display panel by being mounted on a flexible circuit film or the like, and such integrated circuit chips have a high ratio to the manufacturing cost of the liquid crystal display device. do.

As a result, the gate driving circuit is integrated with the substrate, thereby reducing the cost of the gate driving circuit. Such a gate driving circuit is susceptible to deterioration of transistors constituting the gate driving circuit due to the characteristics of the driving signal, thereby making it possible to perform unstable driving operation.

The technical problem to be achieved by the present invention is to prevent the deterioration of the transistor constituting the gate driving circuit.

A display device according to an embodiment of the present invention is a display device including a plurality of pixels arranged in a matrix, the substrate being formed on a substrate and transferring the gate signals formed of a gate on voltage and a gate off voltage to the pixels. A plurality of gate lines and a gate driver connected to the gate lines to generate the gate signals, wherein the gate drivers are connected to the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal. Generate the gate signal based on the amplitude of the first and second clock signals less than the amplitude of the third and fourth clock signals;

The phase difference between the first clock signal and the second clock signal may be 180 °, and the phase difference between the third clock signal and the fourth clock signal may be 180 °.

The phase of the first clock signal and the third clock signal may be substantially the same, and the phase of the second clock signal and the fourth clock signal may be substantially the same.

The amplitude of the first and second clock signals may be -7V to 30V.

The minimum value of the third and fourth clock signals may be substantially the same as the minimum value of the first and second clock signals.

The maximum value of the third and fourth clock signals may be lower than 30V.

The maximum value of the third and fourth clock signals may be in the range of 5V to 10V.

The gate driver may be integrated on the substrate.

The gate driver includes a plurality of stages, wherein the stage includes an input unit, a pull-up driver, a pull-down driver, and an output unit, and the input unit includes first to third transistors connected in series and the first to third transistors. The third or fourth clock signal may be applied to the control terminal of the transistor.

The pull-up driving unit may include fourth and fifth transistors connected in parallel to each other, and the third or fourth clock signal may be applied to control terminals of the fourth and fifth transistors.

The output unit may alternately output the gate on voltage and the gate on off voltage, and the first to fifth transistors may maintain the gate on off voltage.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

1 and 2, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver connected thereto. The gray voltage generator 800 connected to the 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 may include a plurality of signal lines G ₁ -G _{n and} D ₁ -D _m and a plurality of pixels PX connected to the plurality of signal lines G ₁ -G _{n and} D ₁ -D _m , which are arranged in a substantially matrix form. Include. On the other hand, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal line includes a plurality of gate lines G ₁ -G _n transmitting a gate signal (also referred to as a “scan signal”) and a plurality of data lines D ₁ -D _m transmitting a data signal. The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX includes a switching element Q connected to a signal line, a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. Holding capacitor Cst can be omitted as needed.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line G _i , and the input terminal of which is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor Cst, which serves as an auxiliary part of the liquid crystal capacitor Clc, is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the separate signal line. However, the storage capacitor Cst may be formed such that the pixel electrode 191 overlaps the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. 2 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. . Unlike FIG. 2, the color filter 230 may be formed above or below the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of the liquid crystal panel assembly 300.

Referring back to FIG. 1, the gray voltage generator 800 generates two sets of gray voltage sets (or reference gray voltage sets) related to the transmittance of the pixel PX. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

A gate driver 400, a gate line (G ₁ -G _n) and is connected to the gate turn-on voltage (Von), and a gate signal consisting of a combination of a gate-off voltage (Voff), a gate line (G ₁ of the liquid crystal panel assembly 300 -G _n ). The gate driver 400 includes a plurality of stages substantially arranged in a row as a shift register, and together with the signal lines G ₁ -G _n , D ₁ -D _m , and the thin film transistor switching element Q. In the same process, the liquid crystal panel assembly 300 is formed and integrated.

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 and selects a gray voltage from the gray voltage generator 800 and uses the data line D ₁ as a data signal. -D _m ). However, when the gray voltage generator 800 provides only a predetermined number of reference gray voltages instead of providing all of the voltages for all grays, the data driver 500 divides the reference gray voltages to divide the gray voltages for all grays. Generate and select the data signal from it.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or mounted on a flexible printed circuit film (not shown). And attached to the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 500, 600, and 800 may be integrated in the liquid crystal panel assembly 300 together with the signal lines G ₁ -G _n , D ₁ -D _m , and the thin film transistor switching element Q. . In addition, the driving apparatuses 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

Next, the operation of the liquid crystal display will be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B based on the input image signals R, G, and B and the input control signal, according to the operating conditions of the liquid crystal panel assembly 300, and gates them. After generating the control signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500).

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to).

The data control signal CONT2 is a load for applying a data signal to the horizontal synchronization start signal STH and the data lines D ₁ -D _m indicating the start of image data transmission for the pixels PX in one row [bundling]. Signal LOAD and data clock signal HCLK. The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the data signal relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " by reducing the " voltage polarity of the data signal for the common voltage ") RVS) may be further included.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for the pixels PX in one row (bundling), and each digital image signal DAT. By converting the digital image signal DAT into an analog data signal by selecting a gray scale voltage corresponding to), it is applied to the corresponding data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage Von to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n . Turn on the switching element (Q) connected to. Then, the data signal applied to the data lines D ₁ -D _m is applied to the pixel PX through the switching element Q turned on.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer attached to the display panel assembly 300.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), thereby all the gate lines G ₁ -G _n. ), The gate-on voltage Von is sequentially applied to the data signal to all the pixels PX, thereby displaying an image of one frame.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame. "Invert frame"). In this case, the polarity of the data signal flowing through one data line is changed (eg, row inversion and point inversion) or the polarity of the data signal applied to one pixel row is different depending on the characteristics of the inversion signal RVS within one frame. (E.g. column inversion, point inversion).

Next, an example of a gate driver according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 to 6.

3 is a block diagram of a gate driver according to an embodiment of the present invention, and FIG. 4 is a circuit diagram of the j th stage of a shift register for a gate driver according to an embodiment of the present invention, and FIG. 5 is an embodiment of the present invention. FIG. 6 is a waveform diagram illustrating driving signals of a gate driver according to an example, and FIG. 6 is a layout view of first and second stages of the gate driver according to an exemplary embodiment of the present invention.

3 to 6, the shift register 400, which is the gate driver 400, includes a plurality of stages ST1, STj-1, STj, STj + 1, and STn + 1 connected to gate lines, respectively. do. The plurality of stages ST1, STj-1, STj, STj + 1, and STn + 1 are connected to each other dependently, and the scan start signal STV, the first, second, third, and fourth clock signals CLK1. , CLK2, CLKD1, CLKD2) are input.

The first clock signal CLK1 and the second clock signal CLK2 have a phase difference of 180 degrees, and the third clock signal CLKD1 and the fourth clock signal CLKD2 have a phase difference of 180 degrees. The phases of the first clock signal CLK1 and the third clock signal CLKD1 are substantially the same, and the phases of the second clock signal CLK2 and the fourth clock signal CLKD2 are substantially the same.

The first and second clock signals CLK1 and CLK2 are larger than the amplitudes of the third and fourth clock signals CLKD1 and CLKD2. In more detail, it is preferable that the amplitude ranges of the first and second clock signals CLK1 and CLK2 range from -7V to 30V. The minimum value of the third and fourth clock signals CLKD1 and CLKD2 is preferably -7V and the maximum value is between 5 and 10V.

The high period of the scan start signal STV is positioned in the low period of the first and third clock signals CLK1 and CLKD1 and the high period of the second and fourth clock signals CLK2 and CLKD2 and the first and third clocks. While the signals CLK1 and CLKD1 go high and the second and fourth clock signals CLK2 and CLKD2 go low, the scan start signal STV goes low.

Each clock signal CLK1, CLK2, CLKD1, CLKD2 is a gate on voltage V _on capable of driving the switching element Q of the pixel when high, and a gate off voltage V _off when low. desirable.

Each stage ST1, STj-1, STj, STj + 1, STn + 1 has a set terminal S, a gate voltage terminal GV, a pair of clock terminals CK1, CK2, CKD1, CKD2, and a reset. It has a terminal R, a frame reset terminal FR, a gate output terminal OUT1 and a carry output terminal OUT2.

In each stage, for example, the set terminal S of the j-th stage STj, the carry output of the front stage ST (j-1), that is, the front carry output Cout (j-1), is a reset terminal. The gate output of the rear stage [ST (j + 2)], that is, the rear gate output Gout (j + 1), is input to (R), and the clock signal CLK1 is supplied to the clock terminals CK1, CK2, CKD1, and CKD2. , CLK2, CLKD1, and CLKD2 are input, and a gate off voltage V _off is input to the gate voltage terminal GV. The gate output terminal OUT1 outputs the gate output Gout (j) and the carry output terminal OUT2 outputs the carry output Cout (j).

However, the scan start signal STV is input to the first stage of each shift register 400 instead of the front carry output. In addition, the first clock signal CLK1 is connected to the first clock terminal CK1 of the j-th stage STj, the second clock signal CLK2 is connected to the second clock terminal CK2, and the third clock terminal CKD1 is used. When the third clock signal CLKD1 is input to the fourth clock terminal CKD2 and the fourth clock signal CLKD2 is input, the (j-1) th and (j + 1) th stages (ST (j) -1), ST (j + 1)], the second clock signal CLK2 is connected to the first clock terminal CK1, the first clock signal CLK1 is connected to the second clock terminal CK2, and the third clock terminal is connected to the second clock terminal CK2. The fourth clock signal CKLD2 is input to the CKD1, and the third clock signal CLKD1 is input to the fourth clock terminal CKD2.

Referring to FIG. 4, each stage of the gate driver 400 according to an embodiment of the present invention, for example, the j stage, includes an input unit 420, a pull-up driver 430, a pull-down driver 440, and an output unit ( 450). These include at least one NMOS transistor T1-T14, and the pull-up driver 430 and the output unit 450 further include capacitors C1-C3. However, PMOS transistors may be used instead of NMOS transistors. In addition, the capacitors C1-C3 may actually be parasitic capacitances between the gate and the drain / source formed during the process.

The input unit 420 includes three transistors T11, T10, and T5 connected in series to the set terminal S and the gate voltage terminal GV. Gates of the transistors T11 and T5 are connected to the fourth clock terminal CKD2, and gates of the transistor T10 are connected to the third clock terminal CKD1. The contact between the transistor T11 and the transistor T10 is connected to the contact J1, and the contact between the transistor T10 and the transistor T5 is connected to the contact J2.

The pull-up driving unit 430 includes a transistor T4 connected between the set terminal S and the contact J1, a transistor T12 connected between the clock terminal CK1 and the contact J3, and a third clock. And a transistor T7 connected between the terminal CKD1 and the contact J4. The gate and the drain of the transistor T4 are commonly connected to the set terminal S, the source is connected to the contact J1, and the gate and the drain of the transistor T12 are commonly connected to the third clock terminal CKD1. Connected and the source is connected to contact J3. The gate of the transistor T7 is connected to the contact J3 and is connected to the third clock terminal CKD1 through the capacitor C1, the drain is connected to the third clock terminal CKD1, and the source is the contact J4. The capacitor C2 is connected between the contact J3 and the contact J4.

The pull-down driver 440 receives the gate-off voltage V _off through a source and outputs a plurality of transistors T6, T9, T13, T8, T3, and T2 through a drain to the contacts J1, J2, J3, and J4. ). The gate of the transistor T6 is connected to the frame reset terminal FR, the drain is connected to the contact J1, the gate of the transistor T9 is connected to the reset terminal R, and the drain is connected to the contact J1. The gates of the transistors T13 and T8 are commonly connected to the contact J2, and the drains are connected to the contacts J3 and J4, respectively. The gate of the transistor T3 is connected to the contact J4, the gate of the transistor T2 is connected to the reset terminal R, and the drains of the two transistors T3 and T2 are connected to the contact J2. .

The output unit 450 has a pair of transistors T1 and T14 having a drain and a source connected between the first clock terminal CK1 and the output terminals OUT1 and OUT2 and a gate connected to the contact J1, respectively. And a capacitor C3 connected between the gate and the drain of the transistor T1, that is, between the contact J1 and the contact J2. The source of transistor T1 is also connected to contact J2.

The operation of such a stage will now be described.

For convenience of explanation, the voltage corresponding to the high level of the clock signals CLK1, CLK2, CLKD1, and CLKD2 is called a high voltage, and the magnitude of the voltage corresponding to the low level of the clock signals CLK1, CLK2, CLKD1, and CLKD2 is a gate. It is equal to the off voltage V _off and is called low voltage.

First, when the fourth clock signal CLKD2 and the front carry output Cout (j-1) (or the scan start signal STV) become high, the transistors T11 and T5 and the transistor T4 are turned on. The two transistors T11 and T4 transfer a high voltage to the contact J1, and the transistor T5 transfers a low voltage to the contact J2. As a result, the transistors T1 and T14 are turned on so that the first clock signal ( CLK1 is output to the output terminals OUT1 and OUT2. At this time, since the voltage of the contact J2 and the first clock signal CLK1 are both low voltages, the output voltages Gout (j) and Cout (j) are low voltages. At the same time, the capacitor C3 charges a voltage having a magnitude corresponding to the difference between the high voltage and the low voltage.

At this time, since the first and third clock signals CLK1 and CLKD1 and the rear gate output Gout (j + 1) are low and the contact J2 is also low, the transistors T10, T9, T12, T13, T8, and T2) are all off.

Subsequently, when the fourth clock signal CLKD2 becomes low, the transistors T11 and T5 are turned off. At the same time, when the first and third clock signals CLK1 and CLKD1 become high, the output voltage of the transistor T1 and The voltage at the contact J2 becomes a high voltage. At this time, a high voltage is applied to the gate of the transistor T10, but since the potential of the source connected to the contact J2 is also the same high voltage, the potential difference between the gate sources becomes zero, so that the transistor T10 remains turned off. . Accordingly, the contact J1 is in a floating state, whereby the potential is further increased by the high voltage by the capacitor C3.

On the other hand, since the potentials of the first clock signal CLK1 and the contact J2 are high voltage, the transistors T12, T13, and T8 are turned on. In this state, the transistor T12 and the transistor T13 are connected in series between the high voltage and the low voltage, so that the potential of the contact J3 is divided by the resistance value of the resistance state at the turn-on of the two transistors T12 and T13. Voltage value. However, assuming that the resistance value of the resistance state at the turn-on of the two transistors T13 is set to be very large compared to the resistance value of the resistance state at the turn-on of the transistor T12, for example, about 10,000 times, the voltage of the contact J3 is a high voltage. Is almost the same as Accordingly, the transistor T7 is turned on and connected in series with the transistor T8, so that the potential of the contact J4 is divided by the resistance value of the resistance state at the turn-on of the two transistors T7 and T8. Have At this time, if the resistance values of the resistance states of the two transistors T7 and T8 are set to be almost the same, the potential of the contact J4 has an intermediate value between the high voltage and the low voltage, and thus the transistor T3 is turned off. Keep it. At this time, since the rear gate output Gout (j + 1) is still low, the transistors T9 and T2 also remain turned off. Therefore, the output terminals OUT1 and OUT2 are connected only to the first clock signal CLK1 and cut off from the low voltage to emit a high voltage.

On the other hand, the capacitor C1 and the capacitor C2 charge voltages corresponding to the potential difference between both ends, respectively, and the voltage of the contact J3 is lower than the voltage of the contact J5.

Subsequently, when the rear gate output Gout (j + 1) and the first and third clock signals CLK1 and CLKD1 go high and the fourth clock signal CLKD2 goes low, the transistors T9 and T2 turn on. The low voltage is transmitted to the contacts J1 and J2. At this time, the voltage of the contact J1 falls to the low voltage while the capacitor C3 discharges, but it takes some time to completely lower to the low voltage due to the discharge time of the capacitor C3. Therefore, the two transistors T1 and T14 remain turned on for a while even after the rear gate output Gout (j + 1) becomes high, so that the output terminals OUT1 and OUT2 are connected to the clock signal CLK1. To emit low voltage. Subsequently, when the capacitor C3 is completely discharged and the potential of the contact J1 reaches a low voltage, the transistor T14 is turned off so that the output terminal OUT2 is cut off from the first and third clock signals CLK1 and CLKD1. The output Cout (j) is suspended and maintains a low voltage. At the same time, the output terminal OUT1 is continuously connected to the low voltage through the transistor T2 even when the transistor T1 is turned off, thereby continuously outputting the low voltage.

On the other hand, since the transistors T12 and T13 are turned off, the contact J3 is in a floating state. In addition, the voltage of the contact J5 is lower than the voltage of the contact J4. The transistor T7 is turned off because the voltage of the contact J3 is kept lower than the voltage of the contact J5 by the capacitor C1. . At the same time, since the transistor T8 is also turned off, the voltage at the contact J4 is lowered by that amount, so that the transistor T3 also remains turned off. In addition, the transistor T10 maintains the turn-off state because the gate is connected to the low voltages of the first and third clock signals CLK1 and CLKD1 and the voltage of the contact J2 is low.

Next, when the fourth clock signal CLKD2 becomes high, the transistors T12 and T7 are turned on, the voltage of the contact J4 is increased, and the transistor T3 is turned on to transmit a low voltage to the contact J2. OUT1 continues to emit a low voltage. That is, even if the rear gate output Gout (j + 1) has a low output, the voltage of the contact J2 can be made low.

Meanwhile, since the gate of the transistor T10 is connected to the high voltage of the third clock terminal CKD1 and the voltage of the contact J2 is a low voltage, the gate of the transistor T10 is turned on to transfer the low voltage of the contact J2 to the contact J1. Meanwhile, the first clock terminal CK1 is connected to the drains of the two transistors T1 and T14 so that the first clock signal CLK1 is continuously applied. In particular, the transistor T1 is made relatively larger than the rest of the transistors, so that the parasitic capacitance between gate drains is large, so that the voltage change of the drain may affect the gate voltage. Therefore, when the first clock terminal CK1 becomes high, the gate voltage may increase due to the parasitic capacitance between the gate drains, thereby turning on the transistor T1. Therefore, the low voltage of the contact J2 is transferred to the contact J1 to maintain the gate voltage of the transistor T1 at a low voltage, thereby preventing the transistor T1 from turning on.

Thereafter, the voltage at the contact J1 maintains a low voltage until the front carry output Cout (j-1) becomes high, and the voltage at the contact J2 is the first clock signal CLK1 and is high. When the clock signal CLKD2 is low, the low voltage is maintained through the transistor T3, and vice versa, the low voltage is maintained through the transistor T5.

On the other hand, the transistor T6 receives the initialization signal INT generated in the last dummy stage (not shown) and transfers the gate-off voltage V _off to the contact J1 to transfer the voltage of the contact J1 once more. Set to low voltage.

In this manner, the stage 400 is based on the front carry signal Cout (j-1) (scan start signal STV) and the rear gate signal Gout (j + 1) and the clock signals CLK1, CLK2, The carry signal Cout (j) and the gate signal Gout (j) are generated in synchronization with CLKD1 and CLKD2.

Here, the gate terminals of the transistors T7, T10, and T12 are connected to the third clock terminal CLKD1, and the third clock signal CKD3 is applied, and the gate terminals of the transistors T5 and T11 are the fourth clock terminal ( The fourth clock signal CLKD2 is applied to the CKD2. The duty ratio of the transistors T5, T7, T10, T11, and T12, which maintains the gate-off voltage, is 0.5, and if the duration of the gate-on voltage is 20us at 60 Hz, the duty ratio of the transistor T4 is 0.0012. It is enough. The gate-on voltage is applied to the transistors T5, T7, T10, T11, and T12 for a long time, which may cause degradation of the transistor. When the third and fourth clock signals CKD1 and CLKD2 applied to the transistors T5, T7, T10, T11 and T12 are smaller than the amplitude of the first clock signal CLK1 as in the present invention, for a relatively long time Even when the gate-on voltage is applied, damage to the transistor can be reduced.

According to the present invention, the transistors constituting the gate driving circuit can be prevented from deteriorating, thereby realizing more stable operation of the gate driver and increasing its lifespan.

Claims (11)

A display device including a plurality of pixels arranged in a matrix, Board, A plurality of gate lines formed on the substrate and transferring a gate signal including a gate on voltage and a gate off voltage to the pixel; A gate driver connected to the gate line and generating the gate signal Including, The gate driver generates the gate signal based on a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal, and amplitudes of the first and second clock signals are the third and fourth signals. Less than the amplitude of the clock signal Display device. In claim 1, And a phase difference between the first clock signal and the second clock signal is 180 degrees, and a phase difference between the third clock signal and the fourth clock signal is 180 degrees. In claim 2, A display device of which the phases of the first clock signal and the third clock signal are substantially the same, and the phases of the second clock signal and the fourth clock signal are substantially the same. In claim 3, The first and second clock signals have amplitudes of -7V to 30V. In claim 2, The minimum value of the third and fourth clock signals is substantially the same as the minimum value of the first and second clock signals. In claim 5, The maximum value of the third and fourth clock signals is lower than 30V. In claim 6, The maximum value of the third and fourth clock signals is within a range of 5V to 10V. In claim 1, And the gate driver is integrated on the substrate. In claim 8, The gate driver includes a plurality of stages, The stage includes an input unit, a pull-up driving unit, a pull-down driving unit and an output unit, The input unit includes first to third transistors connected in series, and the third or fourth clock signal is applied to a control terminal of the first to third transistors. In claim 9, The pull-up driving unit includes fourth and fifth transistors connected in parallel to each other, and the third or fourth clock signal is applied to control terminals of the fourth and fifth transistors. In claim 10, The output unit alternately outputs the gate on voltage and the gate on off voltage, The first to fifth transistors maintain the gate on off voltage.

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