KR20080019386A - Power sequence circuit for liquid crystal display and liquid crystal display having this - Google Patents

Abstract

A power sequence circuit of an LCD device and an LCD device having the same are provided to reduce the number of elements by implementing the power sequence circuit using an extra OP(Operational) amplifier. A power sequence circuit of an LCD(Liquid Crystal Display) device includes an amplifier(821), a delaying unit(822), and a switching unit(825). The amplifier receives a source voltage through an input terminal and outputs an amplified source voltage. The delaying unit delays the amplified source voltage outputted from the amplifier. The switching unit includes a first switching circuit(823) which is turned on by the delayed source voltage, and a second switching circuit(824) for switching the output of the first switching circuit based on the turning on of the first switching circuit.

Description

Power sequence circuit of a liquid crystal display device and a liquid crystal display device having the same {POWER SEQUENCE CIRCUIT FOR LIQUID CRYSTAL DISPLAY AND LIQUID CRYSTAL DISPLAY HAVING THIS}

1 is a block diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram illustrating a unit pixel according to an exemplary embodiment of the present invention.

3 is a convex diagram schematically illustrating a driving voltage generator according to an exemplary embodiment of the present invention.

4 is a partial circuit diagram illustrating a power sequence circuit of a gate-on voltage generator according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: lower substrate 200: upper substrate

300: liquid crystal display panel 400: gate driver

500: data driver 600: signal controller

700: DC / DC converter 800: drive voltage generator

900: gray voltage generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply sequence circuit of a liquid crystal display device and a liquid crystal display device having the same, and more particularly, to a liquid crystal display configured by utilizing an extra repair op-amp provided in a driving chip of a data driver. A power supply sequence circuit of a device and a liquid crystal display device having the same.

Liquid crystal display is a display device that realizes an image by controlling the amount of light incident from a light source using the optical anisotropy of liquid crystal molecules and the polarization characteristics of a polarizing film. In recent years, its power consumption is small, and its application range is rapidly expanding.

The liquid crystal display includes a liquid crystal display panel, a gate driver, a data driver, a driving voltage generator, a gray voltage generator, a DC / DC converter, and a signal controller for controlling them.

The DC / DC converter receives a predetermined voltage, generates a liquid crystal driving voltage AVDD, and outputs the generated liquid crystal driving voltage AVDD to the driving voltage generating unit. The driving voltage generating unit uses the liquid crystal driving voltage AVDD to generate a gate-on voltage Von. The gate off voltage Voff, the reference voltage VDD, and the common voltage Vcom are generated and output.

Among them, the gate-on voltage (Von), gate-off voltage (Voff) and reference voltage (VDD) are output to the gate driver, each voltage is timed to prevent the latch up phenomenon of the driving chip It is output at the correct timing.

In general, when the power is turned on, the power is output in the order of the reference voltage VDD, the gate off voltage Voff / liquid crystal driving voltage AVDD, and the gate on voltage Von. Therefore, the driving voltage generation unit is provided with a circuit for controlling the output timing of the output power, that is, a power sequence circuit. The power sequence circuit according to the prior art is composed of many electrical elements, so that the manufacturing cost There was a problem that goes up.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a new liquid crystal display device which can reduce manufacturing costs by constructing a power supply sequence circuit using a repair OP-AMP provided in a driving chip of a data driver. An object of the present invention is to provide a power supply sequence circuit and a liquid crystal display device having the same.

In order to achieve the above object, a power supply sequence circuit of a liquid crystal display according to the present invention includes an amplifier for receiving a power supply voltage AVDD through an input terminal and amplifying and outputting a current thereof, and a power supply output from the amplifier. A delay unit for outputting the voltage AVDD by a predetermined time delay, a first switching circuit turned on by the power supply voltage AVDD output from the delay unit, and a first switching circuit turned on by the first switching circuit and input through the input terminal; And a switching unit including a second switching circuit configured to output the received power voltage AVDD.

Preferably, the amplification unit includes an OP-AMP, and the op amp may be configured in a voltage follower manner to have an amplification degree of '1'.

The delay unit preferably includes an RC delay circuit composed of a first resistor and a capacitor, and a second resistor for preventing bypass to the ground terminal.

Preferably, the first switching circuit includes a first transistor, and the second switching circuit includes a second transistor.

Preferably, the first transistor is an npn type transistor, and the second transistor is a pnp type transistor.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a liquid crystal display panel, a gate driver and a data driver for driving the liquid crystal display panel, a common voltage generator, a gate on voltage generator, and a gate off voltage. A driving voltage generator including a generator, wherein at least one of the common voltage generator, the gate-on voltage generator, and the gate-off voltage generator receives a power supply voltage AVDD through an input terminal and amplifies its current; A first switching circuit and the first switching circuit which are turned on by the amplifying unit for outputting, a delay unit for delaying the output voltage AVDD output from the amplifying unit for a predetermined time, and a power supply voltage AVDD output from the delay unit. A second switching circuit which is turned on by the first switching circuit and outputs a power voltage AVDD received through the input terminal; Compared is characterized in that it comprises a switching

Preferably, the amplification unit includes an OP-AMP, and the op amp may be configured in a voltage follower manner to have an amplification degree of '1'.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like reference numerals in the drawings refer to like elements.

1 is a block diagram schematically illustrating a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram illustrating a unit pixel according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the liquid crystal display includes a liquid crystal display panel 300, a gate driver 400, a data driver 500, a DC / DC converter 700, a driving voltage generator 800, and a gray voltage generator. 900 and a signal controller 600 for controlling them.

The liquid crystal display panel 300 includes a plurality of unit pixels arranged in a matrix form. The unit pixel is defined by a cross region of a plurality of gate lines G1 to Gn and a plurality of data lines D1 to Dm formed in a horizontal and vertical direction, and includes a switching element Q and a liquid crystal capacitor connected thereto. Clc) and a storage capacitor (Cst).

Referring to FIG. 2, the liquid crystal display panel 300 includes a lower substrate 100 on which a switching element Q, a gate line G, a data line D, and a pixel electrode 190 are arranged, and a black matrix ( The upper substrate 200 having the color filter 230 and the common electrode 270 arranged thereon and a liquid crystal layer (not shown) filled between the two substrates 100 and 200.

The switching element Q includes amorphous silicon, polysilicon, or the like as a channel layer, and includes a thin film transistor (TFT) including a gate electrode, a source electrode, and a drain electrode. It is effective to use Here, the gate electrode is connected to the gate lines G1 to Gn, the source electrode is connected to the data lines D1 to Dm, and the drain electrode is the pixel electrode 190, the liquid crystal capacitor Clc, and the storage capacitor Cst. Connected with

The liquid crystal capacitor Clc is configured to have a constant capacitance by using a pixel electrode 190 connected to the switching element Q and a common electrode 270 opposite to each other, and a liquid crystal layer between the two terminals as a dielectric. do.

The sustain capacitor Cst is configured such that a gate line G or a separate sustain line (not shown) and the pixel electrode 190 overlap with an insulator interposed therebetween. The sustain capacitor Cst includes a voltage corresponding to a difference between a gate voltage applied through the gate line G and a gray voltage applied to the pixel electrode 190, or a common voltage and a pixel electrode applied through a separate sustain line. The voltage corresponding to the difference of the gray scale voltage applied to the battery 190 is charged to maintain the image signal transmitted to the specific pixel for a predetermined frame (usually one frame). Of course, the sustain capacitor Cst, which plays an auxiliary role of the liquid crystal capacitor Clc, may be omitted.

The DC / DC converter 700 receives a predetermined voltage and generates a liquid crystal driving voltage AVDD obtained by rectifying the predetermined switching voltage PWM_SW and the switching voltage PWM_SW.

The driving voltage generator 800 may include a gate-on voltage Von for turning on the switching element Q, a gate-off voltage Voff for turning off the switching element Q, and driving. A liquid crystal driving voltage AVDD and a common electrode for generating a reference voltage VDD (not shown) for operating a chip and outputting the same to the gate driver 400 and generating a gray voltage applied to the pixel electrode 190. The common voltage Vcom applied to the data source 270 is generated and output to the data driver 500.

The gray voltage generator 900 generates a gray voltage (or gamma voltage) using the liquid crystal driving voltage AVDD applied from the driving voltage generator 800, and outputs the gray voltage (or gamma voltage) to the data driver 500.

The gate driver 400 is connected to each gate line G1 to Gn of the liquid crystal display panel 300 to include a gate on voltage Von and a gate off voltage Voff from the driving voltage generator 800. Analog signals are sequentially applied to the gate lines G1 to Gn as gate signals. The gate driver 400 includes a plurality of stages in which shift resistors are arranged in a line.

Data driver 500 is connected to each of the data lines (D1 ~ Dm) of the liquid crystal display panel 300, a gray voltage is applied from the gradation voltage generation section 900 as the data signal each of the data lines (D ₁ ~ D _m ) Are applied sequentially.

The signal controller 600 may include image signals R, G, and B and control signals thereof input from an external graphic controller (not shown), for example, a vertical sync signal Vsync, a horizontal sync signal Hsync, and a main signal. In response to the clock signal MCLK and the data enable signal DE, the image signal and the control signal are processed in accordance with the operating conditions of the liquid crystal display panel 300, and then the gate control signal CONT1 and the data control signal ( Create and output CONT2).

The gate control signal CONT1 includes a vertical synchronization start signal STV for indicating the start of output of the gate-on pulse (high period of the gate signal GS), and a gate clock signal CPV for controlling the output timing of the gate-on pulse. And an output enable signal OE which defines the width of the gate on pulse.

The data control signal CONT2 is a horizontal synchronization start signal STH indicating the start of input of the image data R ', G', and B ', and a load signal for applying a corresponding data voltage to the data lines D1 to Dm. (LOAD or TP), inversion signal (RVS) and data that inverts the polarity of the data voltage with respect to the common voltage (Vcom) (hereinafter referred to as "polarity of the data voltage" by reducing the "polarity of the data voltage with respect to the common voltage"). Clock signal HCLK and the like.

Next, the driving voltage generator provided in the liquid crystal display according to the present embodiment will be described in detail as follows.

3 is a convex diagram schematically illustrating a driving voltage generator according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the driving voltage generator 800 includes a common voltage generator 810, a gate on voltage generator 820, and a gate off voltage generator 830.

The common voltage generator 810 generates a common voltage Vcom using the liquid crystal driving voltage AVDD and the switching voltage PWM_SW.

The gate-on voltage generator 820 receives the liquid crystal driving voltage AVDD, adjusts its power sequence, charge-pumps the liquid crystal driving voltage AVDD whose power sequence is adjusted, and gate-on voltage Von. )

4 is a circuit diagram illustrating a power sequence circuit of a gate-on voltage generator according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the power sequence circuit includes an amplifier 821 which receives a power supply voltage AVDD through an input terminal and amplifies and outputs a current thereof, and a power supply voltage output from the amplifier 821. A delay unit 822 for outputting the AVDD with a predetermined time delay, a first switching circuit 823 and the first switching circuit 823 turned on by a power supply voltage AVDD output from the delay unit 822. And a switching unit 825 including a second switching circuit 824 that is turned on and outputs a power voltage AVDD received through the input terminal.

The amplifier 821 includes an operational amplifier, that is, an OP-AMP (A).

The op amp (A) preferably utilizes an extra repair op amp provided in the data driver 500. That is, the liquid crystal display panel 300 includes a plurality of data lines D1 to Dm for applying a gray voltage to each unit pixel, and when some of the data lines D are disconnected, the data is repaired for the purpose of repairing them. Each of the driving chips constituting the driver 500 is provided with a repair op amp. These op amps are usually provided two per drive chip, but due to the development of process technology, only a part of them are used and most of them are not used. The present invention utilizes the spare op amp for repair provided in the data driver without using a separate power supply stabilization circuit such as a zener diode.

This op amp (A) is preferably configured in a voltage follower (voltage follower) method to have an amplification degree of '1'. Accordingly, the input voltage and the output voltage are the same, but the output current is amplified above the current capable of turning on the first switching circuit 823, that is, the saturation current.

The delay unit 822 includes a RC delay circuit (Resistance-Capacitance Delay Circuit) composed of a first resistor R1 and a capacitor C1, and prevents bypass to the ground terminal Vss. It further comprises a second resistor (R2) for.

The switching unit 825 includes a first switching circuit 823 including the first transistor T1 and a second switching circuit 824 including the second transistor T2. Here, the first transistor T1 is an npn type transistor, and the second transistor T2 is an npn type transistor. The switching circuit 825 has a dual switching structure in which the second transistor T2 is turned on when the first transistor T1 is turned on.

First, the connection relationship of the power supply sequence circuit will be described in detail as follows.

The operational amplifier A is connected between the input terminal of the liquid crystal driving power source AVDD and the first node N11. The first resistor R1 is connected between the first node N11 and the second node N12, and the second resistor R2 is connected between the first node N11 and the ground terminal Vss. The capacitor C1 is connected between the two nodes N12 and the ground terminal Vss. Meanwhile, a third resistor R3 is connected between the input terminal and the third node N13, and a fourth resistor R4 and the first transistor T1 are connected between the third node N13 and the ground terminal Vss. ) Is connected in series. The first transistor T1 is an npn type transistor driven according to the potential of the second node N12. In addition, the second transistor T2 is connected between the input terminal AVDD and the output terminal Von. The second transistor T2 is a pnp type transistor driven according to the potential of the third node N13.

Next, the operation relationship of the power supply sequence circuit will be described in detail.

When the liquid crystal driving voltage, that is, the power supply voltage AVDD is applied, the amplifier 821 compares the potential of the power supply voltage AVDD and the output voltage, and determines the output accordingly. The output from the amplifying unit 821 is delayed by the delay unit 822 composed of the first resistor R1, the second resistor R2, and the capacitor C1, and thus the base terminal B of the first transistor T1. Is applied. Accordingly, the first transistor T1 is turned on, thereby forming a current path between the third node N13 and the ground terminal Vss. Accordingly, the power supply voltage AVDD is distributed by the third resistor R3 and the fourth resistor R4, and the divided voltage is applied to the base terminal B of the second transistor T2 to supply the second transistor T2. ) Is turned on. Therefore, the power supply voltage AVDD is output as the gate-on voltage Von.

Since the output voltage, that is, the gate-on voltage Von is delayed for a predetermined time while passing through the RC delay circuit 822, the output voltage, that is, the gate-on voltage Von has a predetermined time delayed sequence compared to the power supply voltage, that is, the liquid crystal driving voltage AVDD.

In the present embodiment, the power sequence circuit is configured as simply as possible for convenience of description, but in actual application, various circuits may be further included for the purpose of improving performance and adding functions. For example, the voltage boosted at the output terminal C of the second transistor T ₂ such that the final output gate on voltage Von has a higher or lower voltage than the original liquid crystal driving voltage AVDD. Circuitry can be added.

In addition, in the present exemplary embodiment, the power sequence circuit is applied to the gate-on voltage generator 820, but the present invention is not limited thereto, and the common voltage generator 810, the gate-on voltage generator 820, and the like may be used. Only one of the gate-off voltage generators 830 may be applied, all may be applied, or may be selectively applied. In this case, the technical configuration and effects are the same as described above.

As mentioned above, although this invention was demonstrated with reference to the above-mentioned Example and an accompanying drawing, this invention is not limited to this, It is limited by the following claims. Therefore, it will be apparent to those skilled in the art that the present invention may be variously modified and modified without departing from the technical spirit of the following claims.

As described above, the present invention configures a stable power supply sequence circuit utilizing the spare op amp for repair provided in the driving chip of the data driver. Therefore, the number of components of the power sequence circuit can be reduced, and the manufacturing cost can be reduced.

Claims (12)

An amplifier for receiving a power supply voltage (AVDD) through an input terminal and amplifying and outputting a current thereof; A delay unit configured to delay and output a power voltage AVDD output from the amplifier for a predetermined time; A first switching circuit turned on by the power supply voltage AVDD output from the delay unit, and a second switching circuit turned on by the first switching circuit and outputting a power supply voltage AVDD received through the input terminal. A power supply sequence circuit of a liquid crystal display device comprising a switching unit. The method according to claim 1, And the amplifier comprises an OP-AMP. The method according to claim 2, And the op amp is configured in a voltage follower manner to have an amplification degree of '1'. The method according to claim 1, The delay unit RC delay circuit consisting of a first resistor and a capacitor; And a second resistor for preventing bypass to the ground terminal. The method according to claim 1, And said first switching circuit comprises a first transistor and said second switching circuit comprises a second transistor. The method according to claim 5, Wherein the first transistor is an npn type transistor, and the second transistor is a pnp type transistor. A liquid crystal display panel, A gate driver and a data driver for driving the liquid crystal display panel; A driving voltage generator including a common voltage generator, a gate on voltage generator, and a gate off voltage generator; At least one of the common voltage generator, the gate on voltage generator, and the gate off voltage generator, An amplifier which receives the power supply voltage AVDD through an input terminal and amplifies its current, and outputs the delayed output by delaying the power supply voltage AVDD outputted from the amplifier for a predetermined time; And a switching unit including a first switching circuit turned on by the output power voltage AVDD and a second switching circuit turned on by the first switching circuit and outputting a power voltage AVDD received through the input terminal. A liquid crystal display device characterized in that. The method according to claim 7, The amplification unit includes an OP-AMP, And the op amp comprises a spare op amp for repair provided in the data driver. The method according to claim 8, And the op amp is configured in a voltage follower manner to have an amplification degree of '1'. The method according to claim 7, The delay unit RC delay circuit consisting of a first resistor and a capacitor; And a second resistor for preventing bypass to the ground terminal. The method according to claim 7, And the first switching circuit comprises a first transistor and the second switching circuit comprises a second transistor. The method according to claim 11, Wherein the first transistor is an npn type transistor, and the second transistor is a pnp type transistor.

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