KR20080008909A - Double gate 1-transistor dram cell using bulk silicon and dram device having the same and method of manufacturing thereof - Google Patents

Abstract

A double gate 1-transistor DRAM cell using bulk silicon, a DRAM device having the same, and a manufacturing method thereof are provided to enhance the characteristic of elements by implementing floating body type DRAM cell using a silicon substrate. A DRAM(Dynamic Random Access Memory) cell includes a silicon substrate(41), a gate(50), first and second junction regions(51a,51b), a bottom gate(46), and source and bit lines(55,59). The gate is formed on the silicon substrate. The first and second junction regions are formed on the silicon substrate at one and the other sides of the gate. The bottom gate is overlapped with the gate in the silicon substrate under the first and second junction regions. The source and bit lines are contacted to the first and second junction regions.

Description

Double gate 1-transistor DRAM cell using bulk silicon and DRAM device having same and method for manufacturing the same {Double gate 1-transistor DRAM cell using bulk silicon and DRAM device having the same and method of manufacturing application}

1 is a cross-sectional view showing a DRAM cell implemented in a conventional SOI wafer.

2A and 2B illustrate cell data storage states in DRAM cells implemented in conventional SOI wafers.

3 is a graph showing the cell read current in a DRAM cell implemented in a conventional SOI wafer.

4 is a cross-sectional view showing a DRAM device according to the present invention.

5A to 5K are cross-sectional views of processes for explaining a method of manufacturing a DRAM device according to the present invention.

6 is a circuit diagram of a DRAM device according to the present invention.

Explanation of symbols on the main parts of the drawings

41: silicon substrate 42: etching mask

43: T-type silicon region 44: Reverse-T type first groove

45: first insulating film 46: bottom gate

47: second insulating film 48: second groove

49 silicon 50 gate

51a: source region 51b: drain region

52: first interlayer insulating film 53: first contact hole

54: first contact plug 55: source line

56: second interlayer insulating film 57: second contact hole

58: second contact plug 59: bit line

60 silicon connection 61 substrate body

62: substrate bulk C: unit cell

The present invention relates to a semiconductor device, and more particularly, to a double gate 1-transistor DRAM cell implemented using bulk silicon, a DRAM device having the same, and a manufacturing method thereof.

BACKGROUND Semiconductor devices, including DRAMs, are generally based on integration on silicon wafers. However, silicon wafers currently used in semiconductor devices are not used in the operation of the device, but only a limited area of several micrometers is involved in the device operation. With the exception of some thicknesses, the remaining parts use extra power unnecessarily to increase power consumption and, in particular, reduce the driving speed of the device.

Accordingly, there is a need for a silicon on insulator (SOI) wafer formed by forming a silicon single crystal layer having a thickness of several μm through an insulating layer on a silicon substrate. This is because semiconductor devices integrated on SOI wafers have been reported to realize both high speeds and low voltages due to higher speeds due to smaller junction capacities and lower voltages due to lower threshold voltages compared to semiconductor devices integrated on conventional silicon wafers. to be.

1 is a cross-sectional view illustrating a DRAM cell implemented in a conventional SOI wafer. As shown in FIG. 1, the SOI wafer 10 has a stacked structure of a silicon substrate 1, an buried oxide film 2, and a silicon layer 3. In the silicon layer 3 of the SOI wafer 10, an isolation layer 11 defining an active region is formed to contact the buried oxide film 2, and a gate is formed on the active region of the silicon layer 3. 12 is formed, and source / drain regions 13a and 13b are formed in the silicon layer 3 on both sides of the gate 12 so as to be in contact with the buried oxide film 2.

In the DRAM cell implemented in the SOI wafer, a substrate body corresponding to a channel region is floated from a substrate bulk, that is, a silicon substrate 1, and a hole in the floating body. ) And the electrons are captured to store data.

For example, as shown in FIG. 2A, the storage "1" state may be understood as a hole having a lot of holes in the floating body. As shown in FIG. 2B, the storage "0" state is a state where there are few holes in the floating body. Or, it can be understood that the electrons are many states.

FIG. 3 shows the cell read current when the cell gate voltage is sweeped while the cell drain voltage Vd is 0.2V and the cell source voltage is ground GND for a DRAM cell implemented in a conventional SOI wafer. It is a graph.

As shown, it can be seen that the current is the largest in the storage "1" state, the smallest in the storage "0" state, and the reference current is located in the middle.

However, in implementing the semiconductor device by applying the SOI wafer, despite the device characteristic advantages described above, the SOI wafer is expensive compared to the conventional silicon wafer, which is not preferable in terms of productivity.

In particular, when manufacturing a semiconductor device by applying an SOI wafer, since existing equipment and processes are designed to be suitable for applying a silicon wafer, all manufacturing equipment and processes must be changed or developed. The manufacture of a semiconductor device to which is applied is practically difficult to use.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and provides a DRAM cell, a DRAM device having the same, and a method of manufacturing the same, which can reduce productivity by using a silicon substrate made of bulk silicon. Has its purpose.

In addition, the present invention provides a DRAM cell, a DRAM device having the same, and a method of manufacturing the same, which can be easily and reliably manufactured by applying all of the equipment and processes designed to be suitable for applying a conventional silicon substrate. There is another purpose for that.

In order to achieve the above object, the present invention, a silicon substrate; A gate formed on the silicon substrate; A first junction region formed in the silicon substrate on one side of the gate; A second junction region formed in the silicon substrate on the other side of the gate; A bottom gate formed to overlap the gate in the silicon substrate under the first and second junction regions; A source line formed to contact the first junction region; And a bit line formed to contact the second junction region.

The bottom gate may be surrounded by an insulating film.

The bottom gate is formed to have a larger width than the gate.

The substrate body on which the gate is formed is characterized in that it is floated.

The first bonding region is connected to the substrate bulk.

A first interlayer insulating film is interposed between the gate and the source line, and the source line is in contact with the first junction region through a first contact plug.

A second interlayer insulating layer is interposed between the source line and the bit line, and the bit line is in contact with the second junction region through a second contact plug.

In addition, to achieve the above object, the present invention, a silicon substrate; A plurality of gates formed at equal intervals on the silicon substrate; A plurality of first and second junction regions formed in the silicon substrate between the gates; A plurality of bottom gates formed to overlap respective gates in the silicon substrate under the first and second junction regions; A plurality of source lines formed to contact the first junction regions, respectively; And a bit line formed to contact the second junction regions.

The second gate may be surrounded by an insulating film.

The bottom gate is formed to have a larger width than the gate.

The substrate body on which the gate is formed is floated.

The first bonding region is connected to the substrate bulk.

A first interlayer insulating layer is interposed between the gate and the source line, and the source line is in contact with the first junction region through a first contact plug, so that the source line including the first contact plug is adjacent to the DRAM. It is characterized by shared between cells.

A second interlayer insulating layer is interposed between the source line and the bit line, wherein the bit line is in contact with the second junction region through a second contact plug, and the second contact plug is shared between adjacent DRAM cells. It is characterized by.

In addition, in order to achieve the above object, the present invention comprises the steps of etching the silicon substrate to form inverse-T-type first grooves defining the T-type silicon regions; Forming a first insulating film on a surface of the silicon substrate on which the reverse-T type first grooves are formed; Forming bottom gates on both sides of a "-" shaped portion of the inverted-T type first groove in which the first insulating film is formed; Filling a second insulating film in an inverted-T type first groove portion in which the bottom gate is not formed; Removing the first insulating layer on the surface of the T-type silicon region and removing the first and second insulating layers buried between the T-type silicon regions to form a second groove; Embedding silicon in the second groove; Forming a plurality of gates on the T-type silicon regions, the gates overlapping each bottom gate; Forming first and second junction regions in the T-type silicon region on both sides of the gate, including silicon embedded in the second groove; Forming a plurality of source lines in contact with the first junction regions, respectively; And forming a bit line in contact with the second junction regions.

The first and second junction regions may be formed by performing high concentration ion implantation of impurities in the T-type silicon region including silicon embedded in the second groove.

The forming of the bottom gate may include filling a conductive film in the inverted-T type first groove; And etching a portion of the buried conductive film.

The first junction region is formed to be connected to the substrate bulk.

The removal of the first and second insulating layers buried between the T-type silicon region surface and the T-type silicon regions may be performed by etch back.

The source line and the bit line may be formed to be shared between adjacent DRAM cells.

Forming a source line in contact with the junction region may include forming a first interlayer insulating film on a silicon substrate to cover the gates; Etching the first interlayer insulating layer to form a first contact hole exposing a first junction region; Forming a first contact plug in the first contact hole; And forming a source line on the first interlayer insulating layer, wherein the source line including the first contact plug is formed to be shared between adjacent DRAM cells.

The forming of the bit line in contact with the first junction region may include forming a first interlayer insulating film on a silicon substrate to cover the gates; Forming a second interlayer insulating film on the first interlayer insulating film; Etching the second and first interlayer insulating layers to form a second contact hole exposing a second junction region; Forming a second contact plug in the second contact hole; And forming a bit line on the second interlayer insulating layer, wherein the second contact plug is formed to be shared between adjacent DRAM cells.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a cross-sectional view showing a DRAM device according to the present invention. As shown, a plurality of gates 50 are formed on a silicon substrate 41 made of bulk silicon, and the first / second junction regions, that is, the source, are formed in the substrate surface on both sides of each gate 50. A plurality of bottom gates 46 are formed in the drain / drain regions 51a and 51b and are surrounded by the first insulating layer 45 in the portion of the silicon substrate 41 under the source / drain regions 51a and 51b. Is formed to overlap each gate 50. In this case, the bottom gate 46 is formed to have a larger width than the gate 50. The gate 50 may be understood as having a laminated structure of a gate insulating film and a gate conductive film.

Subsequently, a first interlayer insulating film 52 is formed on the silicon substrate 41 to cover the gate 50, and a plurality of first interlayer insulating films 52 are in contact with each of the source regions 51a. A source line 55 (or a sensing line) is formed, a second interlayer insulating film 56 is formed on the first interlayer insulating film 52 including the source lines 55, and the second interlayer insulating film is formed. The bit line 59 is formed on the 56 to contact the drain regions 51b. In this case, each of the source line 55 and the bit line 59 is contacted with the corresponding source region 51a and the drain region 51b by the first contact plug 54 and the second contact plug 58. In addition, one source line 55 and one bit line 59 are shared between adjacent cells.

In the DRAM device of the present invention, the unit cell C is composed of a double gate 1-transistor having a gate 50 and a bottom gate 46. In the double gate structure transistor, the substrate body 61 corresponding to the channel region is floated like a semiconductor device implemented in a conventional SOI wafer, and the source region 51a is formed of a substrate by a silicon connection 60. It is connected with the bulk 62.

Therefore, the DRAM device of the present invention is implemented using a silicon substrate made of bulk silicon, and also implements a floating body type DRAM cell by making the substrate body corresponding to the channel region have a floated SOI structure, thereby implementing on a SOI wafer. With the advantages of the device, it is possible to overcome the problems of conventional SOI wafer application.

In addition, the DRAM device of the present invention is different from the conventional DRAM device in which the unit cell is composed of 1-transistor & 1-capacitor, and thus the unit cell is composed of a double gate 1-transistor having a bottom gate. Size can be significantly reduced.

In addition, in the DRAM device of the present invention, the 1-transistor floating body type DRAM cell is not destroyed when the data is read by the NDRO (Non Destructive Read Out) method, thereby improving reliability and increasing the read speed. You have the advantage.

As a result, the present invention implements a DRAM cell having an SOI structure using a silicon substrate made of bulk silicon, and also, by forming a unit cell with a 1-transistor having a double gate structure, thereby improving device characteristics as well as an SOI wafer. Difficulties in application can be overcome, and in particular, the cell size can be significantly reduced to realize a more integrated DRAM device.

In FIG. 4, reference numeral 47 denotes a second insulating film, 53 denotes a first contact hole, and 57 denotes a second contact hole.

Hereinafter, a method of manufacturing a DRAM device according to the present invention as described above will be described with reference to FIGS. 5A to 5K.

Referring to FIG. 5A, after preparing a silicon substrate 41 made of bulk silicon, an etching mask 42 exposing a part of the silicon substrate 41 is formed on the silicon substrate 41. Here, the silicon substrate 41 may be understood to be a p-type substrate, and the etching mask 42 may be formed of a nitride film including a photosensitive film or an oxide film.

Referring to FIG. 5B, an isotropic etching of a portion of the exposed silicon substrate using an etching mask is performed, and thereby, first grooves of the inverse-T type defining the T-type silicon regions 43 on the silicon substrate 41 are formed. 44). Then, the etching mask is removed.

Referring to FIG. 5C, the first insulating layer 45 is formed on the entire surface of the silicon substrate 41 including the surface of the inverted-T first groove 44. Here, the first insulating layer 45 is formed by, for example, a thermal oxidation process.

Referring to FIG. 5D, a conductive film, for example, a silicon film is deposited to fill the first groove 44 of the inverted-T type on the entire surface of the silicon substrate 41 on which the first insulating film 45 is formed. Subsequently, a portion of the buried silicon film is etched to form bottom gates 46 on both sides of the “-” portion of the first T-groove. The etching of the silicon film may be performed by etch back, or may be performed by combining a dry etching process using an etch back and an etching mask.

Referring to FIG. 5E, a second insulating layer 47 is buried in a space between the bottom gates 46, that is, an inverse-T type first groove portion in which the bottom gate 46 is not formed. The bottom gate 46 is surrounded by an insulating film composed of the first and second insulating films 45 and 47.

Referring to FIG. 5F, the first and second insulating layers 43 and 47 buried between the first insulating layer 45 on the surface of the T-type silicon region 43 and the T-type silicon regions 43 are etched back. As a result, a second groove 48 is formed between the T-type silicon regions 43.

Referring to FIG. 5G, silicon 49 is embedded in the second groove to the same thickness as the T-type silicon region in order to interconnect the T-type silicon regions 43.

Referring to FIG. 5H, a plurality of gates 50 having a stacked structure of a gate insulating film and a gate conductive film are formed on the T-type silicon regions 43 according to a known process. In this case, each gate 50 is formed at a position overlapping with the corresponding bottom gate 47, and formed with a width such that the bottom gate 47 has a large width.

Referring to FIG. 5I, an impurity of a predetermined conductivity type, for example, arsenic (As) in the case where the silicon substrate 41 is p-type, is contained in the T-type silicon region on both sides of each gate 50 including silicon embedded in the second groove. And ion implantation of an N-type impurity such as phosphorus (P) at high concentration to form first and second junction regions, that is, source / drain regions 51a and 51b, thereby forming a 1-transistor having a double gate structure. The cell structure is formed. Here, the substrate body 61 corresponding to the lower region of the gate 50, that is, the channel region, is in a floating state by the first insulating layer 45, so that the floated substrate body 61 is always excellent. It exhibits silicon properties.

On the other hand, the source region 51a is electrically connected to the substrate bulk 62, which is a region below the bottom gate 47, by a silicon connection portion corresponding to the “│” portion of the T-type silicon region. The region 51a may be easily applied with a substrate bias like a conventional semiconductor device implemented on a silicon substrate.

Referring to FIG. 5J, a first interlayer insulating film 52 is formed on the silicon substrate 41 on which the cell structure of the double gate 1-transistor is formed to cover the gates. Then, the first interlayer insulating layer 52 is etched to form a plurality of first contact holes 53 exposing the source regions 51a, respectively, and then a conductive film is embedded in each of the first contact holes 53. Thus, a plurality of first contact plugs 54 are formed. Then, after depositing a wiring film on the first interlayer insulating film 52, it is patterned through the first contact plug 54 on each of the first contact plug 54 and the portion of the first interlayer insulating film adjacent thereto. A source line 55 (or a sensing line) in electrical contact with the corresponding source region 51a is formed. Here, the source line 55 including the first contact plug 54 is formed to be shared by adjacent unit cells.

Referring to FIG. 5K, a second interlayer insulating layer 56 is formed on the first interlayer insulating layer 52 on which the source line 55 is formed. Then, the second and first interlayer insulating layers 56 and 52 are etched to form a plurality of second contact holes 57 exposing the drain regions 51b, respectively, and then each second contact hole 57 is formed. ) A plurality of second contact plugs 58 are formed by embedding the conductive film. Then, a wiring film is deposited on the second interlayer insulating film 56, and then patterned to form a wiring film on the second contact plug 58 and a portion of the second interlayer insulating film adjacent thereto through the second contact plug 58. A bit line 59 is formed in electrical contact with the drain regions 51b. Here, the second contact plug 58 is formed to be shared by adjacent unit cells.

Subsequently, although not shown, a series of subsequent known processes are sequentially performed to complete fabrication of a DRAM device including DRAM cells having a double gate 1-transistor structure according to the present invention.

Meanwhile, in the method of manufacturing a DRAM device according to the present invention described above, the present invention provides a bit line including a source line including a first contact hole and a first contact plug and a second contact hole and a second contact plug. Although the first and second contact holes are formed together, the first contact hole and the first contact plug are also formed at the portion of the first interlayer insulating layer on the drain region when the first contact hole and the first contact plug are formed. In addition, when the source line is formed, a wiring film pattern is formed on the first contact plug formed on the drain region, and then, when the bit line is formed, a second contact contacting the wiring film pattern in the second interlayer insulating film. It is also possible to make contact between the drain region and the bit line by forming a hole and a second contact plug.

6 is a circuit diagram of a DRAM device according to the present invention. As shown, the DRAM device of the present invention has a structure in which two adjacent cells share a source line contact and a bit line contact, for example, a gate (= word line) and a bottom gate (= bottom word line) are low ( Blocks are arranged in a row direction, and bit lines are arranged in a column direction, and each bit line includes a block including a sense amplifier (S / A), a write driver (W / D), and a register (REG). ) Is connected, and a reference voltage Ref is applied.

Here, the sense amplifier senses cell data and performs a circuit operation for distinguishing data "1" from data "0", and the register serves as a temporary storage circuit for temporarily storing data of the sense amplifier, The write driver serves as a circuit for generating a driving voltage according to the write data on the bit line when writing data to the cell.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described above, the present invention can improve device characteristics such as high speed and low voltage by implementing a floating body type DRAM cell having an SOI structure using a silicon substrate made of bulk silicon.

In addition, since the present invention implements a DRAM cell having an SOI structure by applying a conventional silicon substrate, it is possible to overcome problems such as productivity degradation and difficulty in equipment and process development that may be caused when the SOI wafer is applied.

In addition, the present invention can significantly reduce the cell size compared to a conventional DRAM cell by configuring a unit cell with a 1-transistor having a double gate structure, thereby realizing a more integrated DRAM device.

In addition, although not described in detail, the present invention implements a 1-transistor floating body type DRAM cell, so that the data of the cell is not destroyed when read by the NDRO (Non Destructive Read Out) method, thereby improving reliability. In addition, it can speed up the reading.

Claims (30)

Silicon substrate; A gate formed on the silicon substrate; A first junction region formed in the silicon substrate on one side of the gate; A second junction region formed in the silicon substrate on the other side of the gate; A bottom gate formed to overlap the gate in the silicon substrate under the first and second junction regions; A source line formed to contact the first junction region; And A bit line formed to contact the second junction region; DRAM cell comprising a. The DRAM cell of claim 1, wherein the bottom gate is surrounded by an insulating layer. The DRAM cell of claim 1, wherein the bottom gate has a width greater than that of the gate. The DRAM cell of claim 1, wherein the gated substrate body is floated. The DRAM cell of claim 1, wherein the first junction region is connected to a substrate bulk. The DRAM cell of claim 1, wherein a first interlayer dielectric is interposed between the gate and the source line. The DRAM cell of claim 1, wherein the source line is in contact with the first junction region through a first contact plug. The DRAM cell of claim 1, wherein a second interlayer insulating layer is interposed between the source line and the bit line. The DRAM cell of claim 1, wherein the bit line is in contact with the second junction region through a second contact plug. Silicon substrate; A plurality of gates formed at equal intervals on the silicon substrate; A plurality of first and second junction regions formed in the silicon substrate between the gates; A plurality of bottom gates formed to overlap each gate in the silicon substrate under the first and second junction regions, respectively; A plurality of source lines formed to contact the first junction regions, respectively; And A bit line formed to contact the second junction regions; DRAM device comprising a. The DRAM device of claim 10, wherein the second gate is surrounded by an insulating layer. The DRAM device of claim 10, wherein the bottom gate has a width greater than that of the gate. The DRAM device of claim 10, wherein the substrate body on which the gate is formed is floated. The DRAM device of claim 10, wherein the first junction region is connected to a substrate bulk. The DRAM device according to claim 10, wherein a first interlayer insulating film is interposed between the gate and the source line. The DRAM device of claim 10, wherein the source line is in contact with the first junction region through a first contact plug. The DRAM device of claim 16, wherein a source line including the first contact plug is shared between adjacent unit cells. The DRAM device of claim 10, wherein a second interlayer insulating film is interposed between the source line and the bit line. The DRAM device of claim 10, wherein the bit line is in contact with the second junction region through a second contact plug. The DRAM device of claim 19, wherein the second contact plug is shared between adjacent unit cells. Etching the silicon substrate to form inverted-T first grooves defining the T-type silicon regions; Forming a first insulating film on a surface of the silicon substrate on which the reverse-T type first grooves are formed; Forming bottom gates on both sides of the “-” character portion of the first T-shaped first groove having the first insulating layer formed thereon; Filling a second insulating film in an inverted-T type first groove portion in which the bottom gate is not formed; Removing the first insulating layer on the surface of the T-type silicon region and removing the first and second insulating layers buried between the T-type silicon regions to form a second groove; Embedding silicon in the second groove; Forming a plurality of gates on the T-type silicon regions, the gates overlapping each bottom gate; Forming first and second junction regions in the T-type silicon region on both sides of the gate, including silicon embedded in the second groove; Forming a plurality of source lines in contact with the first junction regions, respectively; And Forming a bit line in contact with the second junction regions; Method of manufacturing a DRAM device comprising a. 22. The DRAM device of claim 21, wherein the first and second junction regions are formed by performing high concentration ion implantation of impurities in the T-type silicon region including silicon embedded in the second groove. Way. The method of claim 21, wherein forming the bottom gate, Filling a conductive film in the inverted-T first groove; And A portion of the buried conductive film is etched; a method of manufacturing a DRAM device, characterized in that consisting of. 22. The method of claim 21, wherein the first junction region is formed to be connected to the substrate bulk. 22. The method of claim 21, wherein the removal of the first and second insulating films buried between the surface of the T-type silicon region and the T-type silicon regions is performed by etch back. 22. The method of claim 21, wherein the source line and the bit line are formed to be shared between adjacent DRAM cells. 22. The method of claim 21, wherein forming a source line in contact with the junction region, Forming a first interlayer insulating film on a silicon substrate to cover the gates; Etching the first interlayer insulating layer to form a first contact hole exposing a first junction region; Forming a first contact plug in the first contact hole; And Forming a source line on the first interlayer insulating film; Method of manufacturing a DRAM device comprising a. 28. The method of claim 27, wherein the source line including the first contact plug is formed to be shared between adjacent DRAM cells. The method of claim 21, wherein the forming of the bit line in contact with the first junction region comprises: Forming a first interlayer insulating film on a silicon substrate to cover the gates; Forming a second interlayer insulating film on the first interlayer insulating film; Etching the second and first interlayer insulating layers to form a second contact hole exposing a second junction region; Forming a second contact plug in the second contact hole; And Forming a bit line on the second interlayer insulating film; Method of manufacturing a DRAM device comprising a. 30. The method of claim 29, wherein the second contact plug is formed to be shared between adjacent unit cells.

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