KR20070092352A - Transforming method for test circuit - Google Patents

Abstract

A method for transforming a test circuit is provided to shorten a test circuit composition time by transforming automatically latches into transparent latches. A test circuit includes a flipflop and non-transparent latches in order to perform a trouble detection test for a synthesized circuit. A method for transforming the test circuit includes a process for searching the non-transparent latch. The method further includes a process for transforming the non-transparent latch into a transparent latch by forming a predetermined gate logic in the searched latch(S507). The latch search process further includes a process for inputting a net list of the composed circuit, a process for setting a test mode signal, and a process for performing a grouping process by searching the non-transparent latch from the net list.

Description

How to convert test circuit {TRANSFORMING METHOD FOR TEST CIRCUIT}

1 illustrates an exemplary circuit configuration having a flip-flop and a latch

FIG. 2 is a circuit diagram illustrating a structure in which flip-flops of the circuit of FIG. 1 are connected in a scan chain. FIG.

3 is an exemplary circuit diagram of a test circuit converted to a transparent latch.

4 is a flowchart showing a method of converting to a circuit in a conventional test mode.

5 is a flowchart illustrating an embodiment of a test circuit conversion method according to the present invention.

6 is a flow chart illustrating an algorithm for automatically changing a nontransparent latch to a transparent latch.

7 is a circuit diagram illustrating an example of a circuit changed using an automatic change algorithm.

8 is a circuit diagram remodeling a transparently changed latch into a combination circuit;

9 is a schematic circuit diagram showing a test circuit completed through the test circuit conversion method according to the present invention.

The present invention relates to a method for testing a semiconductor chip, and more particularly, to provide a circuit conversion method for converting a test circuit using a full scan chain.

The most common method for testing non-memory semiconductors is the full scan method. The full scan method converts all flip-flops present in a circuit into scannable flip-flops to form a flip-flop chain, thereby facilitating fault detection in the circuit. That is, according to the full scan method, any value can be stored in all flip-flops, and the value stored in the flip-flop can be checked from the outside to detect failures in the circuit.

At this time, generating a value to be set to the flip-flop is called ATPG (automatic test pattern generation), it is largely divided into sequential ATPG and combination ATPG. Sequential ATPG refers to the generation of vectors through several clock cycles sequentially if not all flip-flops in the circuit are connected to the scan chain. A combination ATPG is a circuit where all flip-flops are connected to the scan chain. It is to generate a vector with only one clock cycle without having to sequentially access the flip-flops. In general, by connecting all flip-flops in a circuit to a scan chain and performing a combination ATPG, high fault coverage can be achieved with a minimum of test vectors.

1 shows an exemplary diagram of a general circuit configuration. The example circuit above comprises three flip-flops, one latch and other configuration logic. As a test method for determining whether the circuit configured as described above is operating normally, the above-described full scan circuit can be configured and tested. FIG. 2 is a diagram illustrating a structure in which flip-flops are connected to a scan chain in order to form a full scan chain of the circuit of FIG. 1. To form a scan chain, SI (Signal In) and SE (Signal Enable) inputs are added to an existing flip-flop. The flip-flop thus formed is generally referred to as scan-flip-flop. The SE inputs a signal that selects one of the two inputs D of the scan-flipflop and the input of the SI. That is, if the SE input is 0, the D signal is output in Q in synchronization with the clock. If the SE input is 1, the SI signal is output in Q in synchronization with the clock. The SI signal of the scan-flip-flop thus output is input to an input signal of another scan-flip-flop to form a chain. In this configuration, however, the latch L1 cannot be configured as a flip-flop and thus cannot be connected to the scan chain. When ATPG is performed with the configuration in which the latch L1 is not connected as described above, the response of the input and output of the latch L1 cannot be confirmed, so the failure detection rate is inevitably reduced.

 Accordingly, in order to solve such a problem, it is necessary to make the latch transparent by connecting a test mode to the enable terminal of the latch using a gate logic as shown in FIG. 3. Since the test mode signal is normally input 1, the enable input of the latch connected to the test mode becomes 1. When the enable input of the latch is 1, the latch is in a transparent state. When the latch is in a transparent state, the latch merely serves to connect other configuration logic except flip-flop, so the combination of other configuration logic can be regarded as one logic. Therefore, the entire circuit is in a state of being bundled in a scan chain, thereby increasing the failure detection rate through the combination ATPG. Therefore, it is important to make the latch transparent to test the failure of the circuit through the combination ATPG.

As a tool for converting circuits into test mode for these tests, synopsys test compiler is commonly used.

4 is a flowchart illustrating a method of configuring a circuit of a test mode in which a scan chain is formed using a conventional test mode switching tool. Referring to FIG. 4, conventionally, a circuit configured through a Resister Transfer Level (RTL) compiler or the like is synthesized (S403), and the flipped flop is converted into a scan-flop flop by searching for the configured circuit (S405). At this time, the chain is not yet formed. In the test rule fixing step, information about latches, clocks, resets, and the like was examined by the test rule (s407), thereby solving the problems of latches, clocks, resets, and the like. In particular, conventionally, the nontransparent latches retrieved according to the test rule had to be manually converted to the transparent latches by the user. The scan chain was formed on the circuit thus set up to form a circuit that is entirely connected (s411) to perform a combination ATPG or to perform a sequential ATPG without changing the latch to perform a failure test.

The conventional test circuit conversion method as described above has not been able to make all the latches transparent and has the inconvenience of having to manually insert such a gate.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a test circuit conversion method for converting all latches to a transparent state and automatically converting the latches in a test circuit conversion process in order to solve the conventional problems. .

In order to achieve the above object, the test circuit conversion method according to the present invention is a circuit comprising a flip-flop and nontransparent latches for detecting abnormality of a synthesized circuit, the method comprising: (a) transparent Searching for a latch that has not been performed; and (b) forming predetermined gate logic in the found latch and changing the latch to a transparent latch.

In addition, the step (a) includes (a-1) inputting a netlist of the configured circuit, (a-2) setting a test mode signal, and (a-3) a transparent in the netlist. And searching for and grouping latches that do not.

In addition, an XOR gate is added to an input of a latch having a low level enable among the grouped latches, and an OR gate is added to an input of a latch having a high level enable. It is characterized by converting into a transparent latch.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 5 is a flowchart illustrating an embodiment of a test circuit conversion method according to the present invention. FIG. 6 is a flowchart illustrating an algorithm for automatically changing a non-transferred latch to a transparent latch in the test circuit conversion method. 7 is a circuit diagram illustrating an example of a circuit changed by using the automatic change algorithm, and FIG. 8 is a circuit diagram of a remodeled latch that is changed into a combination circuit.

This operation is performed during the test mode switching process, and is generally performed using the switching tool. This test mode switch tool is synopsys test compiler is the most widely used.

Referring to FIG. 5, when the test mode is selected, the test circuit converting method searches for a combined circuit and converts a flip-flop into a scan-flip-flop when the test mode is selected (s505), automatic latch conversion (s507), It comprises a test rule fixing step (s507) and a test chain insertion step (s511).

The step of converting the flip-flop into a scan-flip-flop (s505) searches for all the flip-flops by searching the combined circuit, and then adds a signal in (SI) and signal enable (SE) input to the flip-flop to scan- Form a flip flop. The SE inputs a signal that selects one of the two inputs D of the scan-flipflop and the input of the SI. That is, if the SE input is 0, the D signal is output in Q in synchronization with the clock. If the SE input is 1, the SI signal is output in Q in synchronization with the clock. However, at this stage, the entire scan chain is not formed yet.

The latch automatic conversion step (s507) searches for the latches in the combined circuit and converts the nontransparent latches into the transparent circuit. In order to perform the conversion, a process as shown in FIG. 6 is performed. That is, the automatic conversion of the latch (s507) includes the step of inputting a netlist (netlist) of the configured circuit (s603), setting a test mode signal (s605), and searching for a nontransparent latch in the netlist. Step s607, grouping the retrieved latches (s609), forming gate logic on the grouped latches (s611), configuring a gate output as an input of enable (s613), and And forming a new netlist (s615). Searching for the non-transparent latches in the netlist and grouping the latches (s607, s609) may detect the non-transparent latches with a low active enable and a latch with a low active enable. group into latches with active enable). A latch with low signal activity enable becomes transparent while 0 is input, and a high active signal constitutes a transparent latch while 1 is input. Therefore, after the above-described step (s609), the XOR gate is added to the input terminal of the latch having the low signal activity enable among the grouped latches, and the OR gate is added to the input terminal of the latch having the high signal activity enable, respectively. Among the grouped latches, the latches of which the input signal is connected to the clock may add one OR gate or XOR gate to each group to allow the latches of all groups to be transparent when the test mode signal is 1 input. . The output of the gate added after the above-described step (s613) is connected to the input of the latch (s615). After the above-described step s613, a newly formed netlist is formed.

FIG. 7 is a circuit diagram showing an example of a circuit configuration that has undergone the above-described latch automatic conversion step (s507). There are four non-transparent latches (L1, L2, L3, L4) in the circuit, and the latches L1, L2 having a high signal activity enable and a latch having a low signal activity enable are found by searching for these latches. Group by (L3, L4). OR gates are respectively inserted into the latches L1 and L2 having the high signal activity enable and XOR gates are respectively inserted into the latches L3 and L4 having the low signal activity enable, respectively. Since all clocks are input, as shown in FIG. 7, only one gate can be inserted in each group to configure a transparent circuit. That is, one OR gate is inserted into the group tying L1 and L2, and the XOR gate is inserted into the group tying L3 and L4. The output of this inserted gate is connected to the enable of each latch. In addition, one of the inputs of the inserted gate is connected with the test mode signal and the other is input with the enable of the original latch. If there are many latches in the circuit, many latches can be connected to the output of the gate, causing timing and wiring problems, but current EDA tools can automatically perform a high fanout net, so this is not a problem.

In this configuration, when the test mode signal is 1, all the latches are transparent and can be represented by one combination circuit model as shown in FIG. Referring to FIG. 8, when a signal having a test mode signal of 1 is input to enable, the latch input signal is in a conductive state in which the input signal is output as it is.

In the test rule application step (s509), the information of the circuit is checked according to a preset test rule. Preset rules include a clock rule for searching for a flip-flop or a latch directly connected to a clock, and a reset rule for searching only a device directly connected to a reset when a reset is connected. can do.

In the test chain insertion step (s511), the converted scan-flip flop is connected to the scan chain, and the changed latches are also formed as one chain to complete the test circuit.

9 is a schematic circuit diagram showing a test circuit completed through the test circuit conversion method according to the present invention. 9, the flip-flops F1, F2, F3, and F4 in the circuit are all changed to scan flip-flops so that the output of F1 enters the input of F2, the output of F2 enters the input of F3, and the output of F3 It forms one full scan chain that goes back to the input of F4 and outputs in response. In addition, all the latches in the circuit, when the TM signal is applied to 1, latches L1, L2, L3, and L4 simply connect the logics therebetween, so that logics except flip-flops can be represented as one large logic. To be. Therefore, in the state where the TM signal and the SE signal are 1, the vector signal generated by the ATPG is input at the SI terminal and thus the signal output from the SO terminal can be analyzed to detect a failure in the circuit.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

As described above, according to the present invention, a latch that is automatically transparent using a predetermined tool can be searched for all non-transparent latches in configuring a full scan chain circuit to perform a combination ATPG. Can be changed to This not only shortens the time to construct the test circuit and reduces the size of the test vector, but also significantly increases the failure detection rate through circuit testing.

Claims (4)

A circuit comprising flip-flops and non-transparent latches for testing fault detection of a synthesized circuit, (a) retrieving a non-transparent latch; And and (b) forming a predetermined gate logic in the found latch and converting the gate logic into a transparent latch. The method of claim 1, wherein step (a) (a-1) inputting a netlist of the configured circuit; (a-2) setting a test mode signal; And and (a-3) searching for and grouping latches that are not transparent in the netlist. The method of claim 2, wherein step (b) And forming predetermined gate logic at an input portion of the grouped latches and converting the predetermined gate logics into a transparent latch. The method of claim 3, Among the grouped latches, an XOR gate is added to the input terminal of the latch having low level enable, and an OR gate is added to the input terminal of the latch having high level enable. A test circuit converting method, characterized in that for converting to a latch.

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