KR20070079804A - Method for manufacturing of semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device is provided to prevent fuse failure due to a laser blowing effect and to improve device yield by adjusting a thickness of a residual insulating layer on an upper surface of a fuse. A cell region, a fuse region, and a pad region are defined on a semiconductor substrate(111) having a lower structure. An interlayer dielectric(119) including a first metal line and a fuse is formed on the semiconductor substrate. A second metal line(145a,145c) is formed on the interlayer dielectric of the cell region and the pad region. The second metal line for etch-stop layer is formed on the fuse region. A passivation layer(147) is formed on the entire surface of the semiconductor substrate. The second metal line of a pad opening region and the second metal line for etch stop layer of a fuse opening region are simultaneously exposed by etching the passivation layer. The fuse opening region for exposing the interlayer dielectric is formed by etching the second metal layer for etch-stop layer of the fuse region.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of easily adjusting the thickness of a residual insulating film on an upper portion of a fuse used in repairing a semiconductor device.

In general, as semiconductor devices become more integrated, DRAM devices have increased memory capacities and chip sizes. In the manufacturing of such semiconductor devices, when a defect occurs in one cell among a large number of fine cells, The device yield is low because the whole device is disposed of as defective.

Therefore, the current yield of the chip is improved by replacing an extra redundancy cell previously formed in the memory with a cell in which a defect has occurred during the manufacturing process to restore the entire memory.

In the repair operation using the redundancy cell, when a defective memory cell is selected through a test after wafer processing is completed, a program for converting the corresponding address into an address signal of the spare cell is executed in the internal circuit. Therefore, when an address signal corresponding to a defective line is input in actual use, the selection is changed to a spare line instead of the defective cell.

In order to perform the repair operation as described above, after completing the semiconductor device, the fuse box is opened by removing an oxide layer on the top of the fuse line in order to repair the circuit in which the failure occurs, and the corresponding fuse line is lasered. It must be cut through. In this case, the wiring broken by the laser irradiation is called a fuse line, and the broken portion and the area surrounding the wiring are called a fuse box.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1A, a second metal wiring 43 is formed on a semiconductor substrate 11 defined by a cell region, a fuse region, and a pad region, and on which a predetermined lower structure is formed.

In this case, the lower structure may include a device isolation layer 13, a gate 15, a first interlayer insulating layer 17, a bit line contact plug 19, a bit line 21, a second interlayer insulating layer 23, and a storage electrode contact plug. 25, the storage electrode 27, the plate electrode layer 29, the third interlayer insulating film 31, the first metal wiring contact plug 33, the first metal wiring 35, the fuse 37, and the fourth interlayer An insulating film 39 and a second metal wiring contact plug 41 are included.

Next, a passivation film 45 is formed on the second metal wire 43.

Referring to FIG. 1B, the passivation layer 45 of the fuse region is etched with a mask defining a fuse open region to form a fuse open region 47. At this time, a portion of the fourth interlayer insulating layer 39 is etched away.

Referring to FIG. 1C, the passivation layer 45 is etched to form the pad open region 49 until the second metal wiring 43 of the pad region is exposed.

The above-described method of manufacturing a semiconductor device according to the related art is based on the fourth interlayer insulating film 39 on the fuse 37 as compared to the method of simultaneously forming the fuse open region 47 and the pad open region 49. It is easy to etch away some.

However, since the thicknesses of the passivation film 45 and the fourth interlayer insulating film 39 to be removed are considerable, the thickness of the fourth interlayer insulating film 39 to be left on the fuse 37 can be controlled. There is a problem in that the yield is reduced by causing defects during laser blowing.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and by forming a second metal wiring for the etch stop layer in the fuse region, the semiconductor device that can control the thickness of the insulating film left on the fuse during the etching process for opening the fuse The purpose is to provide a method.

The semiconductor device manufacturing method of the present invention for achieving the above object. (a) forming an interlayer insulating film including a first metal wiring and a fuse on the semiconductor substrate having a cell region, a fuse region, and a pad region defined thereon, and having a predetermined substructure; (b) forming a second metal interconnection on the interlayer insulating layer in the cell region and the pad region, and simultaneously forming a second metal interconnection for the etch stop layer in the fuse region; (c) forming a passivation film over the entire surface, and then etching the passivation film to expose the second metal wiring of the pad open region and to expose the second metal wiring for the etch stop layer of the fuse open region; And (d) etching the second metal wiring for the etch stop layer in the fuse region to form a fuse open region for exposing the interlayer insulating layer.

In addition, in the method of manufacturing a semiconductor device of the present invention, (a) an interlayer insulating film including a first metal wiring and a fuse is formed on a semiconductor substrate having a cell region, a fuse region, and a pad region defined thereon and having a predetermined substructure. Doing; (b) forming a second metal interconnection on the interlayer insulating layer in the cell region and the pad region, and simultaneously forming a second metal interconnection for the etch stop layer in the fuse region; (c) forming a passivation film over the entire surface, and then etching the passivation film of the pad area to expose the second metal wiring of the pad open area; (d) etching the passivation film of the fuse region to expose the second metal wiring for the etch stop layer of the fuse open region; And (e) etching the second metal wiring for the etch stop layer in the fuse open region to form a fuse open region for exposing the interlayer insulating layer.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

Referring to FIG. 2A, an isolation layer 113 defining an active region is formed on a semiconductor substrate 111 on which a cell region, a fuse region, and a pad region are defined.

Next, a first interlayer insulating layer 119 including a gate 115 and a bit line contact plug 117 is formed on the semiconductor substrate 111.

Next, a second interlayer insulating layer 127 including a bit line 121a, a storage electrode contact plug 123, and a storage electrode 125 connected to the bit line contact plug 117 is formed.

At this time, when the bit line 121a is formed in the cell region, the bit lines 121b and 121c are also formed in the fuse region and the pad region.

Next, a dielectric layer (not shown) and a plate electrode layer 129 are formed on the second interlayer insulating layer 127, and a third interlayer insulating layer 133 is formed on the plate electrode layer 131.

Next, the third interlayer insulating film 133 of the cell region is etched to form a first metal wiring contact plug 135a, and at the same time, the third interlayer insulating film 133 and the second interlayer of the fuse region and the pad region are formed. The insulating layer 127 is etched to form first metal wire contact plugs 135b and 135c.

 Next, the first metal wiring 137 connected to the first metal wiring contact plugs 135a, 135b, and 135c is formed, and a plurality of fuses 139 are formed at the same time. Here, the fuse 139 is preferably formed of a first metal wiring material.

In this case, the first metal wiring contact plug 135a is formed to electrically connect the first metal wiring 137 and the plate electrode layer 131, and the first metal wiring contact plug 135b is formed of the first metal wiring contact plug 135b. And a first metal wiring 137 and the bit line 121b of the fuse region, wherein the first metal wiring contact plug 135c is electrically connected to the first metal wiring 137 and the pad region. It is preferable to form the line 121c to electrically connect it.

Next, a fourth interlayer dielectric layer 141 is formed on the first metal interconnection layer 137, and the fourth interlayer dielectric layer 141 is etched to form a second metal interconnection contact plug 143.

Next, second metal interconnections 145a and 145c are formed on the fourth interlayer insulating layer 141 in the cell region and the pad region, and at the same time, the second metal interconnection 145b for the etch stop layer is formed in the fuse region.

Next, a passivation film 147 is formed on the second metal wires 145a, 145b, and 145c.

Referring to FIG. 2B, a first photoresist layer (not shown) is formed on the passivation layer 147, and the first photoresist layer is etched using a mask defining a fuse open region and a pad open region to form a first photoresist layer pattern 149. ).

Next, the passivation layer 147 is etched using the first photoresist pattern 149 as a mask until the second metal wirings 145b and 145c are exposed, and then the fuse open region 151 and the pad open region 153 are exposed. ). Next, the first photoresist pattern 149 is removed.

Referring to FIG. 2C, a second photoresist layer (not shown) is formed on the entire surface, and the second photoresist layer is etched using a mask defining a fuse open region to form a second photoresist pattern 155.

Referring to FIG. 2D, the second metal wiring 145b is etched using the second photoresist pattern 155 as a mask until the fourth interlayer insulating layer 141 is exposed, and the second photoresist pattern 155 is exposed. Remove it.

In this case, the fourth interlayer insulating layer 141 may be etched such that the fourth interlayer insulating layer 141 remains as much as a predetermined thickness on the fuse 139, thereby preventing the occurrence of defects during laser blowing.

3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention. The same reference numerals are used for the same components as those of FIG. 2A, and descriptions of the related processes are omitted. .

Referring to FIG. 3A, a third photoresist layer (not shown) is formed on the passivation layer 147, and the third photoresist layer is etched using a mask defining a pad open area to form a third photoresist layer pattern 157. .

Next, the passivation layer 147 is etched using the third photoresist pattern 157 as a mask until the second metal wiring 145c is exposed to form a pad open region 159. Next, the third photoresist pattern 157 is removed.

Referring to FIG. 3B, a fourth photoresist layer (not shown) is formed over the entire surface, and the fourth photoresist layer is etched using a mask defining a fuse open region to form a fourth photoresist pattern 159.

Next, the passivation layer 147 is etched using the fourth photoresist pattern 159 as a mask until the second metal wiring 145b is exposed to form a fuse open region 161.

Referring to FIG. 3C, the second metal wiring 145b is etched using the fourth photoresist pattern 159 as a mask until the fourth interlayer insulating layer 141 is exposed, and the fourth photoresist pattern 159 is etched. Remove it.

As described above, in the method of manufacturing the semiconductor device according to the present invention, when the second metal wirings 143a and 143c are formed in the same manner as in the related art, the second metal wiring 143b is also formed in the fuse region. The thickness of the fourth interlayer insulating layer 139 that is left on the fuse 137 may be adjusted without additional processing.

As described above, in the method of manufacturing a semiconductor device according to the present invention, the second metal wiring for the etch stop layer is formed in the fuse region so that the thickness of the insulating film left on the fuse during the etching process for opening the fuse may be adjusted to laser blowing ( It prevents fuse failing by blowing and improves the yield.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (6)

(a) forming an interlayer insulating film including a first metal wiring and a fuse on the semiconductor substrate having a cell region, a fuse region, and a pad region defined thereon, and having a predetermined substructure; (b) forming a second metal interconnection on the interlayer insulating layer in the cell region and the pad region and simultaneously forming a second metal interconnection for an etch stop layer in the fuse region; (c) forming a passivation film over the entire surface, and then etching the passivation film to expose the second metal wiring of the pad open region and to expose the second metal wiring for the etch stop layer of the fuse open region; And (d) etching the second metal wiring for the etch stop layer in the fuse region to form the fuse open region exposing the interlayer dielectric layer; Method of manufacturing a semiconductor device comprising a. The method of claim 1, wherein the fuse is formed of the first metal wiring material. The method of claim 1, further comprising an etching process leaving the predetermined thickness on the fuse after the step (d). (a) forming an interlayer insulating film including a first metal wiring and a fuse on the semiconductor substrate having a cell region, a fuse region, and a pad region defined thereon, and having a predetermined substructure; (b) forming a second metal interconnection on the interlayer insulating layer in the cell region and the pad region and simultaneously forming a second metal interconnection for an etch stop layer in the fuse region; (c) forming a passivation film over the entire surface, and then etching the passivation film of the pad area to expose the second metal wiring of the pad open area; (d) etching the passivation film of the fuse region to expose the second metal wiring for the etch stop layer of the fuse open region; And (e) forming the fuse open region to expose the interlayer insulating layer by etching the second metal wiring for the etch stop layer in the fuse open region; Method of manufacturing a semiconductor device comprising a. The method of claim 4, wherein the fuse is formed of the first metal wiring material. The method of claim 4, further comprising an etching process leaving a predetermined thickness on the fuse after the step (e).

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