KR20070074841A - Liquid crystal display - Google Patents

Abstract

An LCD device is provided to prevent null data from being displayed on a screen by preventing source voltages for driving a source driver from being generated before a timing controller is reset. An LCD(Liquid Crystal Display) device includes a liquid crystal panel having plural gate and data lines and plural pixels, a timing controller for outputting control signals and pixel data signals, a data driver for driving data lines, and a voltage converter(130). The voltage converter includes a voltage generator(310) and a delay circuit(320). The voltage generator generates second operating voltages(DVDD,AVDD). The delay circuit is connected to a reset terminal of the timing controller and delays the second operating voltages until a source voltage supplied to the reset terminal reaches a predetermined level, and outputs first operating voltages(DVDD_D,AVDD_D).

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

1 is a block diagram showing the configuration of a liquid crystal display device which is a flat panel display device;

2 is a view showing a specific configuration of the source driver shown in FIG. 1;

3 shows a circuit configuration of the DC / DC converter shown in FIG. 1;

4 is a view showing an example of the output of the analog power supply voltage delayed by the delay circuit according to the embodiment of the present invention shown in FIG.

* Description of the main parts of the drawing

100: liquid crystal display 110: timing controller

120: source driver 130: DC / DC converter

140: gate driver 150: liquid crystal panel

210: shift register 220: data register

230: Latch 240: Level Shifter

250: digital-to-analog converter 260: output buffer

310: voltage generator 320: delay circuit

The present invention relates to a liquid crystal display device.

The liquid crystal panel of the liquid crystal display device is formed in a plurality of gate lines, a plurality of data lines arranged to cross the plurality of gate lines, and regions defined by the gate lines and the data lines, respectively. It includes a plurality of pixels. The liquid crystal display also includes a gate driver for applying a gate-on voltage to the gate lines, a source driver for applying a pixel data signal to the data lines, and a signal control circuit for controlling them.

At power-on, the signal control circuit transfers the pixel data signal input from the outside to the source driver when the power supply voltage supplied from the outside is stabilized to a predetermined level and is ready for normal operation. That is, a predetermined time is required for the signal control circuit to output a valid pixel data signal from the power-on time.

When the power supply voltage is started from the outside, the source driver drives the data lines with a null data signal until a valid pixel data signal is input from the timing controller. As a result, an unwanted image is displayed on the liquid crystal panel. The source driver is generally composed of a plurality of integrated circuits (ICs). If the value of a null data signal is different for each integrated circuit, an error image displayed on the liquid crystal panel becomes more prominent. Such an error image is continuously displayed on the liquid crystal panel until a valid pixel data signal is output from the signal control circuit (for example, after 60 ms).

Accordingly, an object of the present invention is to provide a liquid crystal display device which can prevent the display of unwanted images at power on.

According to a feature of the present invention for achieving the above object, the liquid crystal display device includes a liquid crystal panel, a timing controller data driver, and a voltage converter. The liquid crystal panel includes a plurality of pixels formed in a plurality of gate lines, a plurality of data lines arranged to intersect the plurality of gate lines, and regions defined by the gate lines and the data lines. Include. The timing controller outputs control signals and pixel data signals, and a data driver drives the plurality of data lines in response to the control signals and the pixel data signal. The voltage converter receives a power supply voltage from an external source to generate first operating voltages required for the operation of the data driver, and delays generation of the first operating voltages until the timing controller is reset at power on.

The voltage converter is connected to a voltage generator for generating second operating voltages, and a reset terminal of the timing controller, and the second operation is performed until the power supply voltage provided to the reset terminal of the timing controller reaches a predetermined level. And a delay circuit for outputting the first operating voltages after delaying the voltages.

The delay circuit includes a first switching signal generation circuit, a first switch, a second switching signal generation circuit, and a second switch. The first switching signal generation circuit is connected to the reset terminal of the timing controller and generates a first switching signal when the power supply voltage input to the reset terminal reaches a predetermined level. The first switch outputs the digital power supply voltage as the delayed digital power supply voltage in response to the first switching signal. The second switching signal generation circuit is connected to the reset terminal of the timing controller and generates a second switching signal when the power supply voltage input to the reset terminal reaches a predetermined level. The second switch includes a second switch outputting the analog power supply voltage to the delayed analog power supply voltage in response to the second switching signal.

In the liquid crystal display of the present invention having the above-described configuration, since power supply voltages for operating the source driver do not occur before the timing controller is reset at power-on, an error image corresponding to null data is not displayed on the liquid crystal panel.

Preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing the configuration of a liquid crystal display device which is a flat panel display device.

Referring to FIG. 1, the liquid crystal display device includes a timing controller 110, a source driver 120, a DC / DC converter 130, a gate driver 140, and a liquid crystal panel 150.

The timing controller 110 receives a pixel data signal RGB, a horizontal sync signal Hsync, a vertical sync signal Vsync, a data enable signal DE, and a clock signal MCLK input from an external graphic source. . The timing controller 110 converts the pixel data signal RGB ′ converted from the data format to meet the specifications of the liquid crystal panel 150, the horizontal synchronization start signal STH, and the line latch signal TP. And the clock signal HCLK is output to the source driver 120.

The timing controller 110 may further include a vertical synchronization start signal STV, a gate clock signal CPV, and the like in response to the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync, and the data enable signal DE. And control signals, such as an output enable signal (OE), to the gate driver 140.

The source driver 120 may control the data lines D1 -Dm of the liquid crystal panel 150 in response to the pixel data signal RGB ′ and the control signals STH, HCLK, and TP provided from the timing controller 110. Generate signals for driving. In general, the data driving circuit 120 is composed of a plurality of integrated circuits.

The gate driver 140 sequentially scans the gate lines G1 -Gn of the liquid crystal panel 150 according to the control signals TV, CPV, and OE provided from the timing controller 110. In this case, scanning refers to sequentially applying a gate-on voltage VON to the gate line, thereby making the pixel of the gate line to which the gate-on voltage is applied write data.

The DC / DC converter 130 receives a power supply voltage CVDD from the outside and supplies powers required for the operation of the liquid crystal display 100, that is, the analog power supply voltage AVDD_D, the digital power supply voltage DVDD_D, and the gate-on voltage VON), gate off voltage VOFF, and common electrode voltage VCOM. In particular, the voltages AVDD_D and DVDD_D according to the embodiment of the present invention are delayed analog power voltage AVDD_D and delayed digital power supply voltage DVDD_D which are output after being delayed until the timing controller 110 is reset at power on. . This will be described in detail later. The delayed analog supply voltage AVDD_D and the delayed digital supply voltage DVDD_D are provided to the source driver 120 and the gate driver 140, and are provided with a gate on voltage VON, a gate off voltage VOFF, and a common electrode voltage VCOM. ) Is provided to the gate driver 140.

The liquid crystal panel 150 includes a plurality of gate lines G1 -Gn, a plurality of data lines D1 -Dm intersecting the gate lines, and a plurality of gate lines G1-Gn, respectively. It contains the pixels of. Each pixel includes a thin film transistor T1 having a gate electrode and a source electrode connected to a gate line and a data line, and a liquid crystal capacitor C _LC and a storage capacitor C _ST connected to a drain electrode of the thin film transistor. In this pixel structure, when the gate lines are sequentially selected by the gate driver 140, and the gate-on voltage VON is applied to the selected gate line in a pulse form, the thin film transistor T1 of the pixel connected to the gate line is turned on. On, the voltage corresponding to the pixel data signal RGB 'is applied to each data line by the source driver 120. This voltage is applied to the liquid crystal capacitor and the storage capacitor through the thin film transistor of the pixel, and the predetermined display operation is performed by driving the liquid crystal and the storage capacitor.

FIG. 2 is a diagram illustrating a detailed configuration of the source driver 120 shown in FIG. 1. The source driver 120 includes a shift register 210, a data register 220, a latch 230, a level shifter 240, a digital-analog converter 250, and an output buffer 260.

The shift register 210 sequentially shifts the horizontal synchronization start signal STH from the timing controller 310 according to the clock signal HCLK and outputs the sampling signal.

The data register 220 sequentially samples and stores the pixel data RGB ′ from the timing controller 110 in predetermined units in response to the sampling signal from the shift register 210. The latch 230 latches pixel data from the data register 220 and outputs latched pixel data in response to the latch signal TP from the timing controller 110. The level shifter 240 performs level shifting to widen the voltage swing width of the pixel data output from the latch 230. The digital-analog converter 250 converts the digital pixel data signal from the level shifter 240 into an analog pixel data signal using the gray scale voltages VO-V11. The gray voltages VO-V11 are generated by a gray voltage generator (not shown). The output buffer 260 stores the analog pixel data signal output from the digital-analog converter 250 and supplies the same to the data lines D1 -Dm of the liquid crystal panel in synchronization with the latch signal TP. For example, the latch 230 outputs the pixel data from the data register 220 to the level shifter 240 at the rising edge of the latch signal TP, and the output buffer 260 may output the latch signal TP. The output of the digital-analog converter 250 is transferred to the data lines D1-Dk at the falling edge of the signal.

In the source driver 120 illustrated in FIG. 2, the shift register 210, the data register 220, and the latch 230 are supplied with the delayed digital power supply voltage DVDD_D, the level shifter 240, and the digital-analog converter ( 250 and the output buffer 260 are supplied with the delayed analog power supply voltage AVDD_D.

3 is a diagram illustrating a circuit configuration of the DC / DC converter 130 shown in FIG. 1. Referring to FIG. 3, the DC / DC converter 130 includes a voltage generator 310 and a delay circuit 320. The voltage generator 310 receives a power supply voltage CVDD from an external source, and includes a gate-on voltage VON, a gate-off voltage VOFF, a common voltage VCOM, a digital power supply voltage DVDD, and an analog power supply voltage AVDD. Occurs.

The delay circuit 320 is connected to the reset terminal RST of the timing controller 110 shown in FIG. 1, and receives the digital power supply voltage DVDD and the analog power supply voltage AVDD from the voltage generator 310. The delayed digital power supply voltage DVDD_D and the delayed analog power supply voltage AVDD_D are output.

Delay circuit 320 includes first switching signal generation circuit 340 including resistors 321-323 and transistor 324, and second switching signal including resistors 326-328 and transistor 329. Generation circuit 350 and PMOS transistors 325 and 330. One end of the resistor 321 is connected to the reset terminal RST of the timing controller 110. The resistor 322 is connected between the other end of the resistor 321 and the ground voltage. One end of the resistor 323 is connected with a connection node of the resistors 321, 322. The collector of transistor 324 is connected to the gate of transistor 325, the emitter is connected to ground voltage, and the gate is connected to the other end of resistor 323. The source of the transistor 325 is connected to the digital power supply voltage DVDD from the voltage generator 310, and the drain outputs the delayed digital power supply voltage DVDD_D.

One end of the resistor 326 is connected to the reset terminal RST of the timing controller 110. The resistor 327 is connected between the other end of the resistor 326 and the ground voltage. One end of the resistor 328 is connected with a connection node of the resistors 326 and 327. The collector of transistor 329 is connected to the gate of transistor 325, the emitter is connected to the ground voltage, and the gate is connected to the other end of resistor 328. The source of the transistor 330 is connected to the analog power supply voltage AVDD from the voltage generator 310, and the drain outputs the delayed analog power supply voltage AVDD_D.

Subsequently, the operation of the delay circuit shown in FIG. 3 will be described with reference to FIG. 4. 4 is a diagram illustrating an output example of the analog power supply voltage AVDD_D delayed by the delay circuit 320 according to the embodiment of the present invention shown in FIG. 3 at power on.

When the supply of the power supply voltage CVDD is started at power-on, the voltage generator 310 generates a digital power supply voltage DVDD and an analog power supply voltage AVDD. When the power supply voltage CVDD applied to the reset terminal RST of the timing controller 110 rises to reach the predetermined level V _D , the transistors 324 and 329 are turned on, respectively. As a result, the switching signals SW1 and SW2 of the collectors of the transistors 324 and 329 are lowered to the ground voltage level, and the transistors 325 and 330 are turned on, respectively. Therefore, the digital power supply voltage DVDD and the analog power supply voltage AVDD generated by the voltage generator 310 output as the delayed digital power supply voltage DVDD_D and the delayed analog power supply voltage AVDD_D through the transistors 325 and 330, respectively. do.

The timing controller 110 is reset when the power supply voltage VDD reaches a predetermined level V _D at power-on. The delay circuit 320 waits until the timing controller 110 is reset when it is powered on and then outputs the delayed digital power supply voltage DVDD_D and the delayed analog power supply voltage AVDD_D when the timing controller 110 is reset.

Before the timing controller 110 shown in FIG. 1 is reset, the latch signal TP is in a high impedance state. Therefore, the latch 230 in the source driver 120 shown in FIG. 2 outputs null data when the power source DVDD_D is supplied.

The delay circuit 320 according to an embodiment of the present invention is a digital delayed by the circuit blocks in the source driver 120 shown in FIG. 2 only after the time T _D at which the timing controller 110 is reset at power-on has elapsed. The power supply voltage DVDD_D and the delayed analog power supply voltage AVDD_D are provided. Therefore, even when the latch signal TP is in the high impedance state, the null power is not output because the digital power supply voltage DVDD_D is not supplied to the latch 230.

When the timing controller 110 is reset, the normal latch signal TP and the pixel data signal RGB 'are output, and the delay circuit 320 also outputs the power supply voltages DVDD_D and AVDD_D.

While the invention has been described using exemplary preferred embodiments, it will be understood that the scope of the invention is not limited to the disclosed embodiments. Rather, the scope of the present invention is intended to include all of the various modifications and similar configurations. Accordingly, the claims should be construed as broadly as possible to cover all such modifications and similar constructions.

According to the present invention as described above, since power supply voltages for operating the source driver are not generated before the timing controller is reset at power-on, an error image corresponding to null data is not displayed on the liquid crystal panel.

Claims (9)

A liquid crystal including a plurality of gate lines, a plurality of data lines arranged to intersect the plurality of gate lines, and a plurality of pixels respectively formed in the regions defined by the gate lines and the data lines. A panel; A timing controller for outputting control signals and pixel data signal; A data driver driving the plurality of data lines in response to the control signals and the pixel data signal; And And a voltage converter configured to generate first operating voltages supplied to the data driver by receiving a power supply voltage from an external source, and to delay generation of the first operating voltages until the timing controller is reset when the power is turned on. Liquid crystal display. The method of claim 1, The voltage converter, A voltage generator for generating second operating voltages; And A delay circuit connected to the reset terminal of the timing controller and delaying the second operating voltages until the power supply voltage provided to the reset terminal of the timing controller reaches a predetermined level and outputting the first operating voltages. Liquid crystal display device comprising a. The method of claim 2, And the second operating voltages include a digital power supply voltage and an analog power supply voltage, and the first operating voltages include a delayed digital power supply voltage and a delayed analog power supply voltage. The method of claim 3, wherein The delay circuit, A first switching signal generation circuit connected to the reset terminal of the timing controller and generating a first switching signal when the power supply voltage input to the reset terminal reaches a predetermined level; A first switch configured to output the digital power supply voltage to the delayed digital power supply voltage in response to the first switching signal; A second switching signal generation circuit connected to the reset terminal of the timing controller and generating a second switching signal when the power supply voltage input to the reset terminal reaches a predetermined level; And And a second switch configured to output the analog power supply voltage to the delayed analog power supply voltage in response to the second switching signal. The method of claim 4, wherein The first switching signal generation circuit, A first resistor having one end connected to the reset terminal of the timing controller; A second resistor connected between the other end of the first resistor and a ground voltage; A third resistor having one end connected to a connection node of the first and second resistors; And a first transistor having a collector connected to the first switch, an emitter connected to a ground voltage, and a gate connected to the other end of the third resistor. The method of claim 5, The first switch, And a second transistor having a gate connected to the collector of the first transistor and outputting the digital power supply voltage generated by the voltage generator as the delayed digital power supply voltage. The method of claim 4, wherein The second switching signal generation circuit, A first resistor having one end connected to the reset terminal of the timing controller; A second resistor connected between the other end of the first resistor and a ground voltage; A third resistor having one end connected to a connection node of the first and second resistors; And And a first transistor having a collector connected to the second switch, an emitter connected to a ground voltage, and a gate connected to the other end of the third resistor. The method of claim 7, wherein The second switch, And a second transistor having a gate connected to the collector of the first transistor and outputting the digital power supply voltage generated by the voltage generator as the delayed digital power supply voltage. The method of claim 4, wherein The data driver, A shift register for shifting the clock signal in synchronization with the horizontal start signal; A data register for storing the pixel data signal from the timing controller in response to a clock signal output from the shift register; A latch for latching the pixel data signal stored in the data register in response to a line latch signal; A level shifter for converting a level of the pixel data signal from the latch; A digital-analog converter for converting the digital pixel data signal output from the level shifter into an analog pixel data signal; And An output buffer for outputting the analog pixel data signal from the digital-to-analog converter to the data lines in response to the line latch signal; The shift register, the data register and the latch are supplied with the delayed digital power supply voltage from the voltage converter, and the level shifter, the digital-to-analog converter and the output buffer are supplied with the delayed analog power supply voltage from the voltage converter. Liquid crystal display.

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