KR20070060855A - Integrated circuit device for test - Google Patents

Abstract

An IC device for a test is provided to conveniently manage and effectively test internal core circuits in an SoC(System on Chip) or SiP(System in Package) chip, and offer a boundary scan circuit for testing short of each signal terminal of an SoC boundary, the internal core, and a memory boundary, and a structure for testing a memory and/or buffer block. An address MUX(Multiplexer)(210) selects an address input path of a memory(300). A data MUX(220) selects a data input path of the memory. A comparator(230) compares a memory reading value with an output value of the data MUX during a memory test. An output MUX(240) selectively outputs the memory reading value or the output value of the address MUX to an external terminal. A pattern generator(500) transmits a test pattern to the data MUX in a series and stops an operation according to a comparison value while transmitting a sequential address to the address MUX. A test controller(400) generates test commands and a test clock for synchronizing the test operation. The boundary scan circuit(100) transfers a result value to the output MUX by testing the short of the boundary signal terminals.

Description

Integrated Circuit Device for Test

1 is a block diagram illustrating a test apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating the boundary scan circuit of FIG. 1.

3 is a block diagram illustrating a boundary scan register of FIG. 2.

4 is a memory test pattern and test sequence

<Description of Major Symbols in Drawing>

100: core and memory boundary scan circuit

200: core 210, 220, 240: mux

230: non-church 300: memory

400: TAP and TAP Controller 500: Test Pattern Generator

600, 610, 620, 630: scan test circuit and memory output peripheral circuit

Republic of Korea Patent Application 2003-92593

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit boundary scan and test device. In particular, the present invention relates to memory and peripheral circuits in order to improve short-circuit detection and failure detection of a signal terminal of an integrated circuit device in which cores and memories inside SoC or SiP are connected. An integrated circuit device having a circuit capable of scan testing.

Recently, in semiconductor integrated circuit technology, cores and memory such as CPUs are physically integrated in one chip, and this is particularly prominent in specialized chips such as RF chips and DSP chips. As a technology for integrating heterogeneous electronic circuit blocks into a single chip, a system on a chip (SoC) or a system in package (SiP) is used. SoC or SiP has an effective reduction in chip area and high integration. It is expanding.

Cores that make up a SoC or SiP are macro blocks such as a central process controller unit (CPU), memory, or a digital signal processor (DSP) that can be embedded in most systems. In addition, there may be other cores constituting other blocks for performing a specific function therein. Integrated circuit devices, such as SoCs or SiPs, are introduced into the product through a series of steps, including circuit design and processing, chip testing, or post-package testing. Chips are increasingly being evaluated and tested for performance. In the case of SiP, each chip is tested in a wafer state. Each chip is packaged in one package and package tested. In the package test, a macro block test is performed to determine whether a short circuit of each signal terminal of an internal device or normal operation of an internal macro block is performed.

As integrated circuits become smaller, more integrated, and contain more cores, efficient testing becomes increasingly difficult. Therefore, to facilitate testing SiP or SoC, the IEEE 1149.1 specification specifies boundary scans that can be used for wiring and testing between integrated circuits. By providing a boundary scan device in a signal path between an internal circuit and an external terminal between each embedded integrated circuit, the input terminal of the boundary scan device can be controlled and observed at the output terminal.

In the conventional method of testing the internal memory, a test pattern is executed in the memory to determine whether the memory is normally operated. To test the internal memory, a test vector is applied and then the expected value and the memory output are compared to determine whether there is a defect.

On the other hand, when designing an integrated circuit, the design should be made in consideration of fault coverage, and it is necessary to know where the fault occurs when the fault occurs. In order to detect defects that may occur when detecting a defect, an appropriate test vector should be applied to the corresponding cell through the input terminal and the output can be observed through the output terminal. To do this, the input pin must be controllable and the output pin must be observable.

However, in the test for the short circuit of each signal terminal of the internal core and the memory, and the test for the normal operation of the internal memory, there is a limit in the conventional test method. That is, since the external terminal cannot control the flip-flop of the internal memory disposed inside the SoC or the input / output data of the internal memory from the external terminal, only the entire functional test can be performed. There is a problem that it is not easy to detect various defects occurring in a short circuit or a cell of the terminal. Recently, various test methods have been proposed to solve this problem. However, most of the test methods are indirect test methods, rather than controlling flip-flops around the internal memory or inputting input / output data patterns of the internal memory. There is a fundamental limitation that is being achieved.

The present invention has been made to solve the above problems, and the object of the present invention is to provide a test circuit that can be implemented in a SoC or SiP chip, and can test the internal core circuits conveniently and effectively.

In particular, the present invention may perform a test on a memory block and / or a test on a buffer block together with a boundary scan circuit for performing a test on whether each signal terminal of an SoC boundary or an internal core and a memory boundary is shorted. There is a further purpose to provide a structure that exists.

Specifically, the internal memory is tested by inputting a test input pattern suitable for the memory in a test for a short circuit between each signal terminal of an SoC boundary or an internal core and a memory boundary, and a test for whether the internal memory operates normally or a bad point. The present invention provides an integrated circuit device and a method thereof in which a defect type and a spot can be known, and a flip-flop around a core and a memory can be directly tested by a scan test method.

An integrated circuit device according to the first aspect of the present invention for achieving the above technical problem, the core and memory; An address mux for selecting an address input path of the memory; A data mux for selecting a data input path of the memory; A comparator for comparing a read value of the memory and an output value of the data mux during a memory test; An output mux for selectively outputting a read value of the memory or an output value of the address mux to an external terminal; And a pattern generator configured to transmit an input test pattern to the data mux serially while transmitting an address sequentially increasing to the address mux, the pattern generator stopping according to a comparison result of the comparator. .

An integrated circuit device according to a second aspect of the present invention for achieving the above technical problem, the core and memory; A memory input / output buffer for temporarily storing data and addresses input / output into the memory; A test controller for generating test data and a test command for the input / output buffer; And an output mux for selectively outputting a read value of the memory or an output value of the memory input / output buffer to an external terminal. In some embodiments, the output mux selectively outputs the output of the boundary scan circuit.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. . This embodiment is not intended to limit the scope of the invention, but is presented by way of example only.

For example, the following description describes an implementation having both a first feature for testing embedded memory and a second feature for testing a memory input / output buffer consisting of flip-flops, but depending on the implementation Only one of the parts and the second feature may be provided, which is also within the scope of the present invention.

For example, in the following description, as an example of a memory input / output buffer, a test may be performed on an address buffer including a flip-flop for storing an access address of a memory and a data buffer including a flip-flop for storing write data of a memory. Although the present invention has been proposed, a structure in accordance with the same idea may be implemented in an output buffer for reading a memory, and the like, which also belongs to the scope of the present invention.

(Example)

1 is a block diagram illustrating an integrated circuit device 700 according to an embodiment of the present invention. The illustrated integrated circuit device 700 includes a core 200 such as a CPU or an MCP, and an internal memory 300; An address mux 210 for selecting an address input path of the memory 300; A data mux 220 for selecting a data input path of the memory 300; An address buffer 620 for temporarily storing a memory address of a point to be accessed from the core 200; A data buffer (610) for temporarily storing data to be written to the memory (300) in the core (200); A comparator 230 for comparing a read value of the memory 300 and an output value of the data mux 220 during a memory test; A pattern for transmitting a predetermined test pattern in series to the data mux 220 while transmitting an address sequentially increasing to the address mux 210, and stopping the pattern according to a comparison result of the comparator 230. Generator 500; A test controller (400, 600) for generating test commands, test data, and a test clock for the data / address buffers (610, 620) and the memory (300); And an output mux 240 for selectively outputting a read value of the memory 300, an output value of the address mux 210, or an output value of the address buffer 620 to an external terminal DO.

In addition, the integrated circuit device according to the present embodiment further includes a boundary scan circuit 100 according to the prior art, and the output TDO of the boundary scan circuit 100 is also switched by the output mux 240. It is more preferable to do. In this case, the test controller may include a part for generating a TDI for boundary scan, a part for generating a test command and a test clock, and a part for supporting a memory / buffer test. A test access port (TAP) / controller 400 for generating a test clock and a storage test controller 600 supporting memory / buffer tests are implemented.

In brief, the integrated circuit device 700 illustrated in FIG. 1 includes a boundary scan circuit 100, a core 200, a memory 300, a storage test controller 600, a first mux circuit 210, and a first circuit. A two mux circuit 220, a comparison circuit 230, an output mux circuit 240, a pattern generator 500, and a test access port (TAP) / controller 400.

The test access port (TAP) / controller 400 may include a test clock signal (TCK), a test mode select signal (TMS), and a test reset signal (TRST) to determine an operation type. Reset is generated, and accordingly, under the control of the test commands TMS and TRST, input test data TDI for boundary scan test is generated and output according to the test clock TCK.

The core 200 and the memory 300 are core circuit blocks that are widely embedded in the SoC integrated circuit device 700. In the drawing, the core 200 and the memory 300 are implemented with cores and memories. The core 200 receives the input test data TDI through a boundary signal terminal (not shown), and the memory 300 receives an address and data generated from the core 200 during normal operation. In the test, the pattern generator 500 receives an address and data.

The boundary scan circuit 100 receives the input test data TDI serially and applies it to the boundary signal terminals to test whether the boundary signal terminals of the core 200 and the memory 300 are shorted. , Serial output (TDO).

2 is a block diagram illustrating a detailed configuration of the boundary scan circuit 100 of FIG. 1. Referring to FIG. 2, the boundary scan circuit 100 includes a boundary scan register 110, a bypass register 120, an instruction register 130, a first mux 140, and a second mux 150. It is provided.

The boundary scan register 110 receives input test data (TDI) serially and applies the boundary test registers to the boundary signal terminals and outputs the serial signal. The bypass register 120 outputs predetermined data (0 or 1) when the scan path is shortened. The command register 130 stores a part of the input test data TDI and recognizes a short test command (“Extest”), a normal operation command (“Sample / Preload”), and a bypass command (“Bypass”). The command data is output as OP (operation) code. The first mux 140 selectively outputs the boundary scan register 110 output or the bypass register 120 output in response to the mux control signal. The second mux 150 selectively outputs the output of the first mux 140 or the output of the command register in response to the mux control signal.

That is, the boundary scan circuit 100 is composed of an operation mode setting and an input / output circuit required for the mode. The test access port (TAP) controller 400 generates a test clock signal TCK and a test mode selection signal TMS to determine an operation type.

Because the boundary scan register 110 inputs serially by shifting the input test data TDI, the number of bits equal to the number of boundary signal terminals is required, and the bypass register 120 determines the length of the boundary scan path. Used to shorten. The instruction register 130 includes instructions for a function to be performed by the boundary scan register 110. The boundary scan register 110 is selected by the short test command ("Extest") or the normal operation command ("Sample / Preload"), and the bypass register 120 is selected by the bypass command ("Bypass"). .

3 is a block diagram illustrating the boundary scan register 110 of FIG. 2. Referring to FIG. 3, the boundary scan register 110 may include a third mux circuit 111, a first D flip-flop 112, a second D flip-flop 113, and a fourth mux circuit 114. ). The boundary scan register 110 is disposed at the signal terminal boundary so as to be connected to the boundary signal terminals.

The third mux circuit 111 selectively outputs the input test data TDI or the system signal under the control of the first mode signal MODE1. The first D-flip-flop 112 latches the output of the third mux circuit 111 by one clock and outputs it as a signal to be applied to the boundary signal terminals. The second D flip-flop 113 latches the output of the first D flip-flop 112 by one clock. The fourth mux circuit 114 selectively outputs the second D-flip-flop 113 or the system signal under the control of the third mode signal MODE3.

A boundary scan test is started according to a short test command (“Extest”), and the boundary scan register 110 includes a shift part and a hold part as shown in FIG. 3. The third mux circuit 111 receives an input from a system signal and input test data (TDI) output through the system of the core 200 and the memory 300, and controls the shift / hold. Any one is selected by the first mode signal MODE1. The selected data is shifted by the clock of the first D flip-flop 112, and the data output from the first D flip-flop 112 goes to the input of the second D flip-flop 113. The input of the fourth mux circuit 114 is the system data and the output data of the second D-flip-flop 113, and the third mode signal in the normal operation state of the core 200 and the memory 300. The system signal is selected by (MODE), and in the case of the boundary scan test of the core 200 and the memory 300, the output of the second D flip-flop 113 is selected by the third mode signal MODE1.

4 illustrates generating a test input pattern in the pattern generator when the output of the comparator 230 is '0' for testing the memory 300.

The memory test method includes writing data to all memory cells by inputting 0 or 1 as data input (401, 403), and then reading the entire memory cell (402, 404) to detect stuck defects, and sequentially changing addresses. And changing the input from 1 to 0 or from 0 to 1 (405, 406) to write data in one memory cell, and then reading a corresponding cell to detect a defect that detects a transition defect. When a defect occurs in the memory, the output of the comparator 230 becomes '1', and this output is applied to the pattern generator 500 to stop data pattern generation. In this case, the output mux 240 is controlled to output an address. It is possible to know the address where the failure occurred and the type of failure.

In summary, the method may further include: detecting a fixed defect that records a test pattern or a mosaic pattern united as '0' or '1' in a memory cell and then verifies a read value thereof; And writing a second pattern inverting the first pattern into a memory cell and detecting a transition failure to verify the read value.

In addition, the scan test circuit 600 according to the present embodiment may be implemented to test an address or data input / output buffer around a memory as follows. The following is an operation description of an implementation to test the address and data input buffers 610 and 620 configured of flip-flops among the memory peripheral buffers.

The data flip-flop 610 selects normal data generated in the core when the SE is '0', and selects the scan input SI when the SE is '1'. In addition, when SE is '1', the output of the data flip-flop 610 is connected to the input of the address flip-flop 620, the output mux 240 selects the output of the address flip-flop, the DO terminal The output indicates whether there is a defect. That is, the illustrated structure allows scan input data (SI) for a plurality of buffers to be input to only one buffer, and replaces the remaining buffers with the outputs of the other buffers, and has a method of verifying only the output values of the last input buffer. . This is somewhat complicated to recognize in which buffer the detected failure has occurred, but has the advantage of allowing a quick verification test for a plurality of buffers with a simple structure. Unlike the structure of FIG. 1, scan input data SI may be applied to each of the buffers 610 and 620, and outputs of the respective buffers 610 and 620 may be output as DOs.

The pattern generator 500 used in a scan test of the memory may include a logic element block configured to receive a scan test command and test pattern data SI; And a D flip-flop for outputting the output of the logic element block in synchronization with a predetermined clock. Test pattern generation circuits in which predetermined pattern data inputted in series are sequentially written in a memory while increasing addresses are omitted in the art because various implementations are presented in the art.

As described above, the integrated circuit device 700 according to an embodiment of the present invention uses a boundary scan circuit to apply input test data (TDI) to determine whether the core and memory signal terminals of the SoC are shorted. A test is performed to test whether the internal memory 300 is defective by inputting an address and data from the pattern generator. The memory peripheral circuit is tested using the scan test circuit 600 and output to the external minimum pin as a test result. It is possible to determine whether the SoC integrated circuit device 700 is good or bad from the signal DO.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

The integrated circuit device according to the present invention inputs a test and a data pattern for whether a SoC internal core and a memory signal terminal are short-circuited by a boundary scan, so that the internal memory can be normally operated, a bad shape, and a bad point. The scan test method detects defects in peripheral circuits easily, and it is possible to accurately determine whether the SoC integrated circuit device is good or bad, a bad shape, a bad spot, etc. and improve the defect detection rate.

Claims (10)

Core and memory; An address mux for selecting an address input path of the memory; A data mux for selecting a data input path of the memory; A comparator for comparing a read value of the memory and an output value of the data mux during a memory test; An output mux for selectively outputting a read value of the memory or an output value of the address mux to an external terminal; And A pattern generator which transmits an input test pattern to the data mux in serial while transmitting an address sequentially increasing to the address mux, and stops the operation according to the comparison result of the comparator. Integrated circuit device comprising a. The method of claim 1, And a test controller for generating test clocks and test instructions for synchronizing test operations. The method of claim 1, wherein the test pattern, A test pattern or mosaic pattern unified with '0' or '1', comprising: a first pattern for detecting stuck failure of the memory; And A second pattern for detecting a defect in the memory as a pattern in which the first pattern is inverted; Integrated circuit device comprising a. The method according to any one of claims 1 to 3, And a boundary scan circuit for testing whether or not there is a short circuit to boundary signal terminals and transferring a result value to the output mux. Core and memory; A memory input / output buffer for temporarily storing data and addresses input / output into the memory; A test controller for generating test data and a test command for the input / output buffer; And Output mux for selectively outputting the read value of the memory or the output value of the memory input / output buffer to an external terminal Integrated circuit device comprising a. The method of claim 5, wherein the memory input / output buffer, An address buffer for temporarily storing a memory address of a point to be accessed in the core; And A data buffer for temporarily storing data to be written to the memory in the core Integrated circuit device comprising a. The method of claim 5, And a boundary scan circuit for testing whether or not there is a short circuit to boundary signal terminals and transferring a result value to the output mux. The method according to any one of claims 5 to 7, An address mux for selecting an address input path of the memory; A data mux for selecting a data input path of the memory; A comparator for comparing a read value of the memory and an output value of the data mux during a memory test; A pattern generator which transmits an input test pattern to the data mux in serial while transmitting an address sequentially increasing to the address mux, and stops the operation according to the comparison result of the comparator. Integrated circuit device further comprising. The method of claim 8, The output mux selectively outputs a read value of the memory, an output value of the address mux, or an output value of the memory input / output buffer to an external terminal, And the test controller generates a test clock for designating a test clock for synchronizing the test operation, test data for an input / output buffer, and a target to be tested. The method of claim 8, wherein the test pattern, A test pattern or mosaic pattern unified with '0' or '1', comprising: a first pattern for detecting a fixed failure of the memory; And A second pattern for detecting a defect in the memory as a pattern in which the first pattern is inverted; Integrated circuit device comprising a.

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