KR20070058129A - Level shift circuit of semiconductor memory device - Google Patents

Abstract

A level shift circuit of a semiconductor memory device is provided to reduce current consumption in a deep power down mode, by disconnecting a power supply voltage in an on-state from a ground when one power supply voltage is in on-state and the other power supply voltage is in off-state. An input part(110) is driven by a first power supply voltage, and outputs an input signal to a first node. A potential difference generation part(120) generates a potential difference between a second node in the input side and a third node in the output side, in response to the first power supply voltage and an output of the input part inputted to the first node. An amplification part(130) is driven by a second power supply voltage, and amplifies the potential difference between the second node and the third node. A control part(140) is constituted between the first node and a ground, and receives a deep power down signal enabled in a deep power down mode, and blocks the path of the third node to the ground by controlling the potential of the first node. An output part(150) is driven by the second power supply voltage, and outputs a signal amplified by the amplification part as an output signal.

Description

LEVEL SHIFT CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE}

1 is a circuit diagram of a level shift circuit of a semiconductor memory device according to the prior art.

2 is a circuit diagram of a level shift circuit of a semiconductor memory device according to a first embodiment of the present invention.

3 is a circuit diagram of a level shift circuit of a semiconductor memory device according to a second embodiment of the present invention.

4 is a circuit diagram of a level shift circuit of a semiconductor memory device according to a third embodiment of the present invention.

The present invention relates to a semiconductor memory device, and more particularly, to a level shift circuit of a semiconductor memory device for reducing an amount of current consumption generated in a level shift circuit during a deep power down mode operation.

In general, a semiconductor memory device operates peripheral circuits in an activated state to store data or outputs stored data to the outside, and minimizes power consumption by disabling unnecessary peripheral circuits in a standby state.

In addition, when the semiconductor memory device is in a standby state for a long time, the semiconductor memory device enters a deep power down mode in which peripheral circuits are stopped to reduce unnecessary power consumption.

However, since the semiconductor memory device entering the deep power down mode cannot turn off all the power supplies, the power turned off internally and the power not turned off coexist. In such a situation, the level shift circuit provided in the semiconductor memory device consumes a lot of current, which will be described in detail below.

1 is a circuit diagram of a level shift circuit of a semiconductor memory device according to the prior art.

As shown, the level shift circuit of the semiconductor memory device according to the prior art operates using the power source A and the power source B, and the power source A is at a level higher than the power source B. Applied to the shift circuit.

The level shift circuit of the semiconductor memory device according to the related art is an inverter INV1 driven by the power B when the power A is turned on and the power B is turned off during the deep power down mode operation. Does not work. Then, the node ND3 is in a floating state, that is, it is not known whether the level is 'high' or 'low'.

In this state, a current caused by the power source A (A) flows to the ground GND through the PMOS transistor P2 and the NMOS transistor N2. This current path is formed by turning on the PMOS transistor P2 by the power source B and turning on the NMOS transistor N2 as the node ND3 is floated. Therefore, in the level shift circuit of the semiconductor memory device according to the related art, current consumption occurs from the power supply PowerA to the ground GND along the current path.

The level shift circuit of the semiconductor memory device according to the prior art should minimize the waste of power by blocking the flow of current in the deep power down mode operation. However, in the level shift circuit of the semiconductor memory device according to the related art, when the power source PowerA is on and the power source PowerB is off, the node ND3 is in a floating state as described above with reference to FIG. Transistor N2 may be turned on.

Accordingly, the level shift circuit of the semiconductor memory device according to the related art has a problem in that a continuous current consumption occurs from the power source PowerA to the ground GND in the above case in the deep power down mode operation.

In addition, the level shift circuit of the semiconductor memory device according to the related art amplifies the potential difference between the node ND1 and the node ND2 through the PMOS transistors P1 and P2 during normal operation. There is a problem that the amplification operation is slow or an error occurs by the PMOS transistor P2.

For example, the level shift circuit of the semiconductor memory device according to the related art may amplify a potential difference between the node ND1 and the node ND2 when the input signal Vin has a high level potential during normal operation. The output signal Vout with the potential of the level should be output.

However, when the PMOS transistor P1 is first turned on due to a difference in size between the PMOS transistor P1 and the PMOS transistor P2, a potential of a high level is applied to the node ND1, thereby providing a PMOS transistor P2. ) May be turned off. Accordingly, there is a problem in that an error of outputting the output signal Vout having the potential of the 'high' level occurs because the node ND1 is at the 'high' level and the node ND2 is at the 'low' level. .

In addition, the level shift circuit of the semiconductor memory device according to the related art gradually amplifies the potential difference between the node ND1 and the node ND2 due to the operation characteristics of the PMOS transistors P1 and P2, and thus has a disadvantage in that the amplification operation is slow.

Accordingly, the present invention was created to solve the problems inherent in the prior art as described above, and an object of the present invention is to reduce current consumption occurring during deep power down mode operation in a level shift circuit of a semiconductor memory device, and This is to prevent an error from occurring during operation.

A level shift circuit of a semiconductor memory device for achieving the above object, the level shift circuit is driven by a first power source, for outputting an input signal to the first node; A potential difference generator for causing a potential difference between an input second node and an output third node in response to an output of the input unit input to the first node and the first power source; An amplifier driven by a second power source and configured to amplify according to a potential difference between the input second node and the output third node; A control unit configured to receive a deep power down signal configured between the first node and the ground and to be enabled in a deep power down mode and to control a potential of the first node to block a ground path of the third node; ; And an output unit driven by the second power source and outputting the signal amplified by the amplifier as an output signal.

In the above configuration, the second power source preferably has a higher potential than the first power source.

In the above configuration, the control unit preferably lowers the potential of the first node to a low level when the deep power down signal is enabled when the first power is not supplied.

In the above configuration, the controller may be configured as an NMOS transistor connected between the first node and the ground and receiving the deep power down signal to a gate.

In the above configuration, the control unit preferably receives the deep power down signal to further control the potential of the input second node.

In the above configuration, when the deep power down signal is enabled, the controller preferably lowers the potential of the input second node to a low level.

In the above configuration, the controller is connected between the second node and the ground, it is preferable that the NMOS transistor is configured to receive the deep power down signal to the gate.

In the above configuration, it is preferable that the input unit further receives the deep power down signal to control the input signal to be fixed when the deep power down signal is enabled.

In the above configuration, the input unit is driven by the first power source, it is preferable that the input signal and the deep power down signal is input is composed of a Noah gate.

In the above configuration, it is preferable to further include a fixing portion connected between the amplifier and the output portion, and for controlling the potential of the output third node when the deep power down signal is in a disabled state.

In the above configuration, the fixed part may include a PMOS transistor configured to input the deep power down signal to the gate and turn on when the deep power down signal is in a disabled state to fix the output third node to a high level. desirable.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of a level shift circuit of a semiconductor memory device according to a first embodiment of the present invention.

As shown, the level shift circuit of the semiconductor memory device according to the first embodiment of the present invention includes an input unit 110 for receiving an input signal Vin; A potential difference generator 120 inducing a potential difference between the node ND4 and the node ND5 in response to the signal output from the input unit 110; An amplifier 130 for amplifying the potential difference between the node ND4 and the node ND5; A controller 140 that receives a deep power down signal dpds enabled in the deep power down mode and adjusts potentials of the nodes ND4 and ND5; And an output unit 150 that inverts the amplified output of the amplifier 130 and outputs the output signal as Vout.

Here, the input unit 110 is driven by the power source PowerB, and is configured as an inverter INV3 which inverts the input signal Vin and outputs it to the node ND6.

The potential difference generator 120 includes an NMOS transistor N3 connected between an input node ND4 and a node ND6 of the amplifier 130, an output node ND5 of the amplifier 130, and a ground ( It consists of an NMOS transistor N4 connected between GNDs. Here, the gate of the NMOS transistor N3 is connected to the power source B, the output of the inverter INV3 is applied to the node ND6, and the gate of the NMOS transistor N4 is connected to the node ND6.

In addition, the amplifier 130 is configured such that the power source A for driving is supplied to the PMOS transistors P3 and P4 in common, and the other end of each of the PMOS transistors P3 and P4 is input side node ND4, respectively. And the output node ND5, and the gates of the PMOS transistors P3 and P4 and the input and output node ND4 and ND5 are cross-connected.

The controller 140 includes an NMOS transistor N5 connected between the node ND4 and the ground GND, and an NMOS transistor N6 connected between the node ND6 and the ground GND. Here, the gates of the NMOS transistors N5 and N6 receive the deep power down signal dpds.

In addition, the output unit 150 is driven by the power source B, and is configured as an inverter INV4 that receives the potential of the node ND5 and inverts it and outputs it as an output signal Vout.

The level shift circuit of the semiconductor memory device according to the first embodiment of the present invention having the configuration as described above normally turns off the control unit 140 to perform the level shift operation normally.

The level shift circuit of the semiconductor memory device according to the first exemplary embodiment of the present invention has a 'high' level and an 'low' level during normal operation in which power A and power B are normally supplied. If you look at in detail as follows.

First, when the input signal is at the 'high' level, the input unit 110 outputs the potential at the 'low' level to the node ND6 through the inverter INV3. At the same time, the transistors N5 and N6 of the controller 140 are turned off because the deep power down signal dpds is in a disabled state, and the connection between the nodes ND4 and ND6 and the ground GND is cut off.

Subsequently, since the potential of the power B level is applied to the gate terminal of the NMOS transistor N3 of the potential difference generator 120, the potential of the node ND4 rises to a 'high' level. At the same time, the NMOS transistor N4 of the controller 120 is turned on because the inverter INV3 outputs a high level potential, and the potential of the node ND5 falls to a low level.

Subsequently, since the potential of the low level is applied to the gate terminal of the PMOS transistor P3 of the amplifier 130, the potential of the node ND4 gradually rises to the power source A level. At the same time, since the potential of the 'high' level is applied to the gate terminal of the PMOS transistor P4 of the amplifier 130, the potential of the node ND5 is gradually lowered to the ground GND level.

Subsequently, the inverter INV4 of the output unit 150 receives the potential of the power A level through the node ND4 and outputs the output signal Vout having the potential of the 'low' level.

Next, when the input signal is at the 'low' level, the input unit 110 outputs the potential of the 'high' level to the node ND6 through the inverter INV3. At the same time, the transistors N5 and N6 of the controller 140 are turned off because the deep power down signal dpds is in a disabled state, and the connection between the nodes ND4 and ND6 and the ground GND is cut off.

Subsequently, since the potential of the power B level is applied to the gate terminal of the NMOS transistor N3 of the potential difference generator 120, the potential of the node ND4 rises to a 'high' level. At the same time, the NMOS transistor N4 of the controller 120 is turned off because the inverter INV3 outputs a potential having a low level, and the connection between the node ND5 and the ground GND is cut off.

Subsequently, since the potential of the 'high' level is applied to the gate terminal of the PMOS transistor P3 of the amplifier 130, the potential of the node ND5 gradually decreases to the ground GND level. At the same time, since the potential of the low level is applied to the gate terminal of the PMOS transistor P4 of the amplifier 130, the potential of the node ND5 gradually rises to the power A level.

Subsequently, the inverter INV3 of the output unit 150 receives the potential of the power source A level and outputs an output signal Vout having the potential of the 'low' level.

As described above, the level shift circuit of the semiconductor memory device according to the first exemplary embodiment shifts the level of the input signal Vin and outputs the output signal Vout during normal operation.

A deep power down operation of the level shift circuit of the semiconductor memory device according to the first embodiment of the present invention will be described in detail as follows. Here, it is assumed that power source A is in an on state and power source B is in an off state.

First, the transistors N5 and N6 of the controller 140 are turned on because the deep power down signal dpds is enabled, and the potentials of the nodes ND4 and ND6 fall to the 'low' level.

As a result, the NMOS transistor N4 of the potential difference generator 120 is turned off by applying a 'low' level potential to the gate, so that the connection between the node ND5 and the ground GND is cut off. At the same time, the NMOS transistor N3 of the potential difference generator 120 is turned off because the power source B is in an off state, and the connection between the node ND4 and the node ND6 is cut off.

Subsequently, the PMOS transistor P4 of the amplifier 130 is turned on by applying a low level potential to the gate terminal.

At this time, since the NMOS transistor N4 of the potential difference generator 120 is turned off, current does not flow from the power source A to the ground GND. That is, the level shift circuit of the semiconductor memory device according to the first embodiment of the present invention lowers the potential of the node ND6 to the 'low' level through the transistor N6 of the controller 140, and thus the potential difference generator 120. NMOS transistor N4 is turned off so as not to form a current path between power source A and ground GND.

At the same time, since the PMOS transistor P3 of the amplifier 130 is turned off by applying a high level potential to the gate terminal, current does not flow from the power source A to the node ND4.

Subsequently, the inverter INV3 of the output unit 150 receives the potential of the 'high' level and outputs the output signal Vout having the potential of the 'low' level.

As described above, in the level shift circuit of the semiconductor memory device according to the first embodiment of the present disclosure, the potential of the nodes ND4 and ND6 is set to the 'low' level through the control unit 140 in the deep power down mode operation. Lower

Accordingly, in the level shift circuit of the semiconductor memory device according to the first embodiment of the present invention, the NMOS transistor N4 and the PMOS transistor P3 are turned off so that current does not flow from the power source A to the ground GND. .

As described above, the level shift circuit of the semiconductor memory device according to the first embodiment of the present invention does not form a current path between the power source A and the ground GND during the deep power-down mode operation. ) Is on and power B is off to reduce current consumption.

Accordingly, the level shift circuit of the semiconductor memory device according to the first exemplary embodiment of the present invention may provide a power source A when power A is on and power B is off during a deep power down mode operation. The current path between the power supply A and the ground GND is reduced by blocking the current path between the power supply A and the ground GND.

3 is a circuit diagram of a level shift circuit of a semiconductor memory device according to a second embodiment of the present invention.

As illustrated, the level shift circuit of the semiconductor memory device according to the second embodiment of the present invention may include an input unit 210, a potential difference generator 220, which receive an input signal Vin and a deep power down signal dpds. It includes an amplifier 230, the control unit 240 and the output unit 250.

Herein, the input unit 210 is driven by the power source B, and a logic gate combining the input signal Vin and the deep power down signal dpds outputs a potential of a high or low level. NR1).

The potential difference generator 220, the amplifier 230, the controller 240, and the output unit 250 include the potential difference generator 120, the amplifier 130, the controller 140, and the output described above with reference to FIG. 2. Since each is the same as the unit 150, detailed description thereof will be omitted.

The level shift circuit of the semiconductor memory device according to the second embodiment of the present invention having such a configuration normally performs a level shift operation because the deep power down signal dpds is disabled during normal operation.

The level shift circuit of the semiconductor memory device according to the second exemplary embodiment of the present invention is in a deep power-down mode operation, as in the first exemplary embodiment of the present invention, power A is on and power B is off. In this state, current consumption from power A to ground (GND) can be prevented, and power A also remains on when both power A and power B are on. There is an effect of preventing current consumption from occurring in the ground GND.

In detail, the level shift circuit of the semiconductor memory device according to the second exemplary embodiment of the present invention may be implemented in a case where power A is on and power B is off in a deep power down mode operation. Since the same operation as in the first embodiment is omitted.

The level shift circuit of the semiconductor memory device according to the second exemplary embodiment of the present disclosure may provide a deep power down signal dpds when both the power source A and the power source B are turned on in the deep power down mode operation. Is enabled, and node ND9 is lowered to the 'low' level.

In other words, since the deep power down signal dpds is enabled in the NOR gate NR1 of the input unit 210, the potential of the node ND9 is fixed at a low level regardless of the logic level of the input signal Vin. do.

Accordingly, the level shift circuit of the semiconductor memory device according to the second embodiment of the present invention fixes the potential of the node ND9 to a low level when the power source B is in the deep power-down mode operation and thus the NMOS transistor. Since the N8 is turned off, current consumption is prevented from occurring from the power source PowerA to the ground GND.

4 is a circuit diagram of a level shift circuit of a semiconductor memory device according to a third embodiment of the present invention.

As illustrated, the level shift circuit of the semiconductor memory device according to the third embodiment of the present invention may include an input unit 310, a potential difference generator 320, an amplifier 330, a controller 340, and a fixing unit 350. And an output unit 360.

Here, the fixed part 350 is configured of a PMOS transistor P9 connected between the power source A and the node ND11 and determined to be turned on according to the deep power down signal dpds.

That is, the PMOS transistor P9 receives the deep power down signal dpds through the gate terminal, and when the deep power down signal dpds is disabled, the potential of the node ND11 falls to the 'high' level.

In addition, the input unit 310, the potential difference generator 320, the amplifier 330, the controller 340, and the output unit 360 include the input unit 210, the potential difference generator 220, and the amplifier described above with reference to FIG. 3. 230, the control unit 240 and the output unit 250 are the same, so a detailed description thereof will be omitted.

The level shift circuit of the semiconductor memory device according to the third embodiment of the present invention having such a configuration has a low power since the deep power down signal dpds is disabled and the PMOS transistor P9 is turned on in normal operation. The potential of the level is output as an output signal Vout.

In detail, the level shift circuit of the semiconductor memory device according to the third exemplary embodiment transfers a potential having a low level to the node ND10 when the input signal has a potential having a 'high' level.

Thereafter, the amplifier 330 amplifies the potential difference between the node ND10 and the node ND11 through the PMOS transistors P7 and P8. In this case, the amplification operation is performed by the PMOS transistor P7 and the PMOS transistor P8. It can be slow or error prone.

In order to solve this problem, the level shift circuit of the semiconductor memory device according to the third exemplary embodiment of the present disclosure may change the potential of the node ND11 through the PMOS transistor P9 of the fixed part 350 in a normal operation. Since it rises to the 'level, there is an effect of outputting the output signal (Vout) having a potential of the normal' low 'level.

That is, since the fixing unit 350 is turned on by receiving the disabled deep power down signal dpds during normal operation, the potential of the node ND11 is increased to the 'high' level by the power source A. . Accordingly, the level shift circuit of the semiconductor memory device according to the third embodiment of the present invention fixes the potential of the node ND11 to the 'high' level through the fixing part 350 in the normal operation, and thus, the 'low' level. There is an effect that the output signal Vout having a potential of?

At this time, the PMOS transistor P9 of the fixing unit 350 should be turned on faster than the PMOS transistors P7 and P8 of the amplifier 330 in order to fix the potential of the node ND11 to a 'high' level. Therefore, the fixing unit 350 is configured of the PMOS transistor P9 having a smaller size than the PMOS transistors P7 and P8.

In addition, although not shown in the drawings, the level shift circuit of the semiconductor memory device according to the third embodiment of the present invention may provide an output signal Vout having a high level potential between the node and the ground. It can be replaced by a fixed portion 350 having an NMOS transistor connected to it. Here, the gate terminal of the NMOS transistor is inputted by inverting the deep power down signal dpds.

As described above, the level shift circuit of the semiconductor memory device according to the first exemplary embodiment of the present disclosure may control the controller 140 when the power source A is on and the power source B is off in a deep power down mode operation. By cutting the current path between the power source (PowerA) and the ground (GND) through), there is an effect of reducing the current consumption generated between the power source (PowerA) and ground (GND).

In addition, the level shift circuit of the semiconductor memory device according to the second exemplary embodiment of the present invention may apply the potential of the node ND7 through the input unit 210 when the powers PowerA and PowerB are turned on in the deep power-down mode operation. By fixing at the low level, there is an effect of reducing the current consumption generated between the power source (PowerA) and ground (GND).

In addition, in the level shift circuit of the semiconductor memory device according to the third embodiment of the present disclosure, during the normal operation, the potential of the node ND11 is 'high' or 'low' according to the input signal Vin through the fixing unit 350. By fixing at the 'level, the error of the output signal Vout does not occur, and the output signal Vout is output more quickly.

According to the configuration as described above in the first embodiment of the present invention, in the level shift circuit of the semiconductor memory device, when one power is on and one power is off in the deep power down mode operation, the on state By blocking the connection between the power supply and the ground, there is an effect to reduce the current consumption generated between the power supply and the ground in the on state.

Further, according to the configuration as described above in the second embodiment of the present invention, in the level shift circuit of the semiconductor memory device, when the two power supply is on in the deep power down mode operation, the power supply in the on state and the ground By cutting off the connection between the power supplies, the current consumption between the on-state power supplies and the ground is reduced.

In addition, according to the configuration as described above in the third embodiment of the present invention, in the level shift circuit of the semiconductor memory device, by fixing the potential of the output node during normal operation, an error of the output signal does not occur, It is effective to output the output signal more quickly.

While the invention has been shown and described with reference to specific embodiments, the invention is not limited thereto, and the invention is not limited to the scope of the invention as defined by the following claims. Those skilled in the art will readily appreciate that modifications and variations can be made.

Claims (11)

An input unit driven by a first power source and outputting an input signal to the first node; A potential difference generator for causing a potential difference between an input second node and an output third node in response to an output of the input unit input to the first node and the first power source; An amplifier driven by a second power source and configured to amplify according to a potential difference between the input second node and the output third node; A control unit configured to receive a deep power down signal configured between the first node and the ground and to be enabled in a deep power down mode and to control a potential of the first node to block a ground path of the third node; ; And And an output unit driven by the second power supply and outputting the signal amplified by the amplifying unit as an output signal. The method of claim 1, And the second power supply has a higher potential than the first power supply. The method of claim 1, And the control unit lowers the potential of the first node to a low level when the deep power down signal is enabled when the first power is not supplied. The method of claim 3, wherein And the control unit comprises an NMOS transistor connected between the first node and the ground and receiving the deep power down signal to a gate. The method of claim 1, And the control unit further controls the potential of the input second node by receiving the deep power down signal. The method of claim 5, And the control unit lowers the potential of the input second node to a low level when the deep power down signal is enabled. The method of claim 6, And the control unit is configured between an NMOS transistor connected between the second node and the ground and receiving the deep power down signal to a gate. The method of claim 1, And the input unit further receives the deep power down signal to control the input signal to be fixed when the deep power down signal is in an enabled state. The method of claim 8, And the input unit is driven by the first power source and comprises a noah gate for receiving the input signal and the deep power down signal. The method of claim 1, A level shift circuit connected between the amplifier and the output unit and configured to control a potential of the output third node when the deep power down signal is in a disabled state. . The method of claim 10, The fixed part may include a PMOS transistor configured to input the deep power down signal to a gate and to turn on the deep power down signal when the deep power down signal is in a disabled state to fix the output third node to a high level. Level shift circuit of a semiconductor memory device.

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