KR20070038670A - DL circuit of semiconductor memory device - Google Patents

Abstract

The present invention proposes a DLL circuit of a semiconductor memory device that increases the area margin in the memory device and reduces power consumption by reconfiguring the delay unit in one circuit in the DLL circuit of the semiconductor memory device.

The DLL circuit of the semiconductor memory device of the present invention includes a clock buffer for converting a positive external clock and a negative external clock into a single internal clock, a delay unit and a delayed unit in which a unit delay or a variable delay of the internal clock is generated, and an internal clock output from the delay unit. And a phase splitter, a clock driver, a data driver, a first clock divider, a replica delay unit, a second clock divider, a phase comparator, and a delay controller.

Memory, DLL Circuit, External Clock

Description

DCL circuit of a semiconductor memory device {DLL Circuit of Semiconductor Memory Apparatus}

1 is a block diagram showing a DLL circuit of a semiconductor memory device according to the prior art;

2 is a block diagram illustrating a DLL circuit of a semiconductor memory device according to the present invention.

<Description of the symbols for the main parts of the drawings>

10: duty cycle correction unit 20: first clock buffer

30: second clock buffer 40: first delay unit

50: second delay unit 60: clock driver

70: data driver 80: first clock divider

90: replica delay unit 100: second clock divider

110: phase comparator 120: delay control unit

200: clock buffer 300: delay unit

400: phase splitter

The present invention relates to a delay locked loop (DLL) circuit of a semiconductor memory device, and more particularly, a DLL circuit of a semiconductor memory device in which a positive external clock and a negative external clock reduce the area of a DLL circuit delayed through each delay unit. It is about.

The DLL circuit is used to provide an internal clock signal that is in constant phase with respect to the reference clock signal. In general, an internal clock signal is generated to operate in synchronization with an external clock signal in a semiconductor memory device having a relatively high degree of integration, such as a synchronous DRAM (SDRAM).

In more detail, when the external clock signal input through the input pin is input to the clock input buffer, the internal clock signal is generated from the clock input buffer. Thereafter, the internal clock signal controls the data output buffer to output data to the outside. At this time, the internal clock signal is delayed for a predetermined time from the external clock signal by the clock buffer, and the output data from the data output buffer is also output after being delayed for a predetermined time from the internal clock signal.

Therefore, there is a problem that the output data is output after a large time delay with respect to the external clock signal. In other words, there is a problem in that the time that data is output after the external clock signal is applied, that is, the output data access time becomes long.

In order to solve this problem, by using the DLL circuit to make the phase of the internal clock signal ahead of a predetermined time, the output data can be output without delay with respect to the external clock signal. In other words, the DLL circuit receives an external clock signal and generates an internal clock signal that is advanced at a predetermined time phase, and the internal clock signal is used as a reference clock signal of each part of the semiconductor device such as a data output buffer.

Hereinafter, a DLL circuit according to the related art will be described with reference to FIG. 1.

1 is a block diagram illustrating a DLL circuit of a semiconductor memory device according to the related art.

The semiconductor memory device according to the related art has a duty cycle corrector 10 for detecting a duty cycle of a clock and a positive internal clock synchronized with a rising edge of the positive external clock CLK and having a value of an external supply power level. A first clock buffer 20 to generate, a second clock buffer 30 to generate a sub internal clock synchronized with the rising edge of the sub external clock CLKB and having a value of an external supply power level, and the positive internal clock A first delay unit 40 having a unit delay or a variable delay of the second delay unit, a second delay unit 50 having a unit delay or a variable delay of the sub-internal clock, and a first delay unit 40 and a second delay. A clock driver 60 for driving the positive internal clock and the negative internal clock output from the unit 50, a data driver 70 for driving data using the output of the clock driver 60, and the first internal clock. 1 Inside the output from the delay unit 40 A first clock divider 80 for dividing a clock signal, a replica delay unit 90 for compensating a delay time of an internal clock received from the first clock divider 80, and the first The second clock divider 100 for generating a reference clock from the positive internal clock output from the clock buffer 20 and the phase of the feedback signal fed back from the reference clock and the replica delay unit 90 are compared. A phase comparator 110 and a delay control unit 120 for adjusting the delay time of the first delay unit 40 and the second delay unit 50.

The operation of the DLL circuit of the conventional semiconductor memory device configured as described above is as follows.

In a semiconductor memory device that processes data at a high speed such as a double data rate (DDR) SDRAM, data is not only read at the rising edge of the external clock but also at the falling edge of the external clock. However, in actual operation, there is a negative external clock signal CLKB having an inverted pulse of the positive external clock signal CLK, so that the data read operation occurs in the rising operation of each clock signal. Therefore, in addition to the positive external clock CLK, a negative external clock CLKB is used for data processing of the high speed semiconductor memory device.

When the positive external clock signal is buffered and output by the first clock buffer 20, there is a slight delay time. The negative external clock signal is also buffered and output by the second clock buffer 30 and has a slight delay time.

Subsequently, the positive internal clock signal and the negative internal clock signal output from the first clock buffer 20 and the second clock buffer 30 are respectively transferred to the first delay unit 40 and the second delay unit 50. By a certain time delay has the same phase as inverted. Thereafter, the sub-internal clock and the positive internal clock output from the first delay unit 40 and the second delay unit 50 are transferred to the data driver 70 through the clock driver 60. The intra subclock is also transmitted to and divided by the first clock divider 80.

Thereafter, when the sub-internal clock is divided in the first clock divider 80 and input to the replica delay unit 90, the divided sub-internal clock is divided by the delay time of the external clock signal and the data output buffer. The time delayed by the operation clock and the time delayed by the first delay unit 40 are added to have a delay time. The replica delay unit 80 compensates for this delay time.

Meanwhile, the reference clock signal, which is a signal in which the sub-internal clock signal is divided and inverted by the second clock divider 100, is input to the phase comparator 110.

When the clock compensated for the delay time is input to the phase comparator 110, the clock is compared with the reference clock delivered from the second clock divider 100, and the comparison value is output to the delay controller 120. . The delay control unit 120 adjusts the delay time generated in the process of outputting the internal clock signal as the operation clock signal through this value.

As this process continues to be fed back, the phase comparator 110 continuously performs a comparison operation until the reference clock and the feedback clock are the same, and if the clocks are the same, the phase is fixed to fix the clock at this time. To print.

However, in the DLL circuit using the positive external clock and the negative external clock, the area margin is reduced by using two delay parts having the same operation, thus increasing the power consumption.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems and disadvantages. The present invention relates to a semiconductor memory device that increases the area margin and reduces power consumption in a memory device by reconfiguring a delay unit in a circuit of a semiconductor memory device. The technical challenge is to provide a DLL circuit.

The DLL circuit of the semiconductor memory device of the present invention for achieving the above technical problem, the clock buffer for converting the positive external clock and the negative external clock to a single internal clock; A delay unit configured to perform a unit delay or a variable delay of the internal clock; A phase splitter for converting one internal clock output from the delay unit into a positive internal clock and a negative internal clock; A clock driver for driving the positive internal clock and the negative internal clock output from the phase splitter; A data driver for driving data using the output of the clock driver; A first clock divider for dividing a signal of a sub-internal clock output from the phase splitter; A replica delay unit that compensates for a delay time of an internal clock received from the first clock divider; A second clock divider for generating a reference clock from an internal clock output from the clock buffer; A phase comparator for comparing a phase of a feedback signal fed back from the reference clock and a replica delay unit; And a delay controller for adjusting a delay time of the delay unit.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 is a block diagram of a DLL circuit of a semiconductor memory device according to the present invention.

The DLL circuit of the semiconductor memory device according to the present invention includes a duty cycle correction unit 10 for detecting a duty cycle of an external clock, a clock buffer 200 for converting a positive external clock and a negative external clock into one internal clock, A delay unit 300 in which a unit delay or a variable delay of the internal clock is made, a phase splitter 400 for converting one internal clock output from the delay unit 300 into a positive internal clock and a negative internal clock, and A clock driver 60 for driving the positive and second internal clocks output from the phase splitter 400, a data driver 70 for driving data using the output of the clock driver 60, and The first clock divider 80 for dividing the signal of the sub-internal clock output from the phase splitter 400 and the replier for compensating the delay time of the internal clock received from the first clock divider 80. Feedback from the delay unit 90, the second clock divider 100 for generating a reference clock from the internal clock output from the clock buffer 20, and feedback from the reference clock and replica delay unit 90. A phase comparator 110 for comparing the phase of the signal, and a delay control unit 120 for adjusting the delay time of the delay unit 300.

The operation of the DLL circuit of the semiconductor memory device of the present invention configured as described above is as follows.

When the positive external clock and the negative external clock are input to the DLL circuit, the clock buffer 200 simultaneously receives the positive external clock and the negative external clock and outputs only one internal clock. In this case, the clock buffer 200 may buffer only the positive external clock or only the negative external clock to output only one internal clock. The delay time generated by the clock buffer 200 is sufficiently controlled by the delay controller 120, and thus is not limited to any one external clock.

Subsequently, the internal clock signal is delayed for a predetermined time by the delay unit 300. The internal clock is then delivered to the phase splitter 400. The phase splitter 400 converts the input internal clock back into a positive internal clock and a negative internal clock. At this time, the respective internal clocks are synchronized and only the phases are reversed.

The positive internal clock and the sub internal clock are transmitted to the data driver 70 through the clock driver 60. The secondary internal clock is also transmitted to and divided by the first clock divider 80.

Thereafter, when the sub-internal clock is input to the replica delay unit 90 through the first clock divider 80, the sub-internal clock delays the operation clock by the delay time of the external clock signal and the data output buffer. The delay time as much as the time to be added and the time delayed by the delay unit 300 is added. The replica delay unit 90 compensates for this delay time.

The reference clock signal, which is a signal in which the internal clock signal is divided and inverted by the second clock divider 100, is input to the phase comparator 110.

When the clock compensated for the delay time is input to the phase comparator 110, the clock is compared with the reference clock delivered from the second clock divider 100, and the comparison value is output to the delay controller 120. . The delay control unit 120 adjusts the delay time generated in the process of outputting the internal clock signal as the operation clock signal through this value.

As this process continues to be fed back, the phase comparator 110 continuously performs a comparison operation until the reference clock and the feedback clock are the same, and if the clocks are the same, the phase is fixed to fix the clock at this time. To print.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The present invention described above has the effect of increasing the area margin in the memory device and reducing power consumption by reconfiguring the delay unit having the same structure and performing the same operation in the DLL circuit of the semiconductor memory into one circuit.

Claims (1)

A clock buffer for converting the positive external clock and the sub external clock into one internal clock; A delay unit configured to perform a unit delay or a variable delay of the internal clock; A phase splitter for converting one internal clock output from the delay unit into a positive internal clock and a negative internal clock; A clock driver for driving the positive internal clock and the negative internal clock output from the phase splitter; A data driver for driving data using the output of the clock driver; A first clock divider for dividing a signal of a sub-internal clock output from the phase splitter; A replica delay unit that compensates for a delay time of an internal clock received from the first clock divider; A second clock divider for generating a reference clock from an internal clock output from the clock buffer; A phase comparator for comparing a phase of a feedback signal fed back from the reference clock and a replica delay unit; And A delay controller for adjusting a delay time of the delay unit; DLL circuit of a semiconductor memory device comprising a.

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