KR20070037011A - Array substrate for lcd and the operating method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device capable of improving image quality while reducing the number of data lines and a driving method thereof.

The array substrate for a liquid crystal display according to the present invention can reduce the number of data drive ICs mounted by reducing the number of data lines, maintain a constant capacitor capacity of the entire pixel, and use the left and right pixels of the common data line. The image quality can be improved by changing the thin film transistor driving order.

In addition, the present invention sequentially drives the first to fourth pixels defined by the intersection of one common data line and the first, second, third, and fourth gate lines, and sequentially drives pixels adjacent to each other from left to right. Image quality can be improved by preventing flickering problems such as flicker.

Common Data Lines, Gate-Source Capacitors

Description

Array substrate for LCD and driving method thereof

1 is a plan view showing a pixel structure of a conventional liquid crystal display device.

FIG. 2 is an equivalent circuit diagram of a pixel structure of the liquid crystal display of FIG. 1. FIG.

3 is a plan view showing a portion of an array substrate for a liquid crystal display according to an embodiment of the present invention.

4 is an equivalent circuit diagram of an array substrate for a liquid crystal display according to the present invention.

FIG. 5 is a schematic representation of a portion of FIG. 4; FIG.

FIG. 6 is a diagram illustrating a gate signal for driving the pixels of FIG. 5. FIG.

<Description of Signs of Major Parts of Drawings>

111a and 111b: first and second gate lines 111c and 111d: third and fourth gate lines

112: common data lines 113a and 113b: pixel electrodes

116a and 116b: semiconductor layers 121a and 121b: gate electrodes

122a, 122b: source electrode 124a, 124b: drain electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device capable of improving image quality while reducing the number of data lines and a driving method thereof.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display panels (PDPs), electro luminescent displays (ELD), and vacuum fluorescent (VFD) Various flat panel display devices have been studied.

Among them, LCD is the most widely used as the substitute for CRT (Cathode Ray Tube) for mobile image display device because of its excellent image quality, light weight, thinness, and low power consumption. In addition to the use of the present invention has been developed a variety of monitors, such as television and computer for receiving and displaying broadcast signals.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the arrangement of molecules can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light polarized by optical anisotropy may be arbitrarily modulated to express image information.

Currently, active matrix liquid crystal displays (AM-LCDs) in which thin film transistors and pixel electrodes connected to the thin film transistors are arranged in a matrix manner are attracting the most attention because of their excellent resolution and ability to implement video.

Hereinafter, a pixel structure of a conventional liquid crystal display device configured as described above will be described in detail with reference to the accompanying drawings.

1 is a plan view illustrating a pixel structure of a conventional liquid crystal display.

As shown in FIG. 1, the liquid crystal display according to the related art includes a plurality of gate lines 11 and a plurality of data lines crossing the gate lines 11 and defining a pixel region P at regular intervals. 12) is formed.

A thin film transistor TFT is formed at an intersection point of each of the gate lines 11 and each data line 12, and the thin film transistor TFT includes a gate electrode 21 that protrudes from the gate line 11, and A semiconductor layer 16 formed on the gate electrode 21 with a gate insulating layer (not shown) therebetween, and a source electrode 22 formed on the semiconductor layer 16 and protruding from the data line 12. ) And a drain electrode 24 spaced apart from the source electrode 22 by a predetermined interval, and a pixel electrode 13 connected to the drain electrode 24 is formed in the pixel region P.

FIG. 2 is an equivalent circuit diagram of a pixel structure of the liquid crystal display of FIG. 1.

As shown in FIG. 2, the intersections of the plurality of gate lines GL1, GL2,..., GLn-1, GLn and the plurality of data lines DL1, DL2, DL3,. A thin film transistor TFT is provided and is connected to the drain electrode of the thin film transistor to form a liquid crystal capacitor C _LC . The liquid crystal capacitor C _LC is not a separate device, but a pixel electrode on the lower substrate and a common electrode on the upper substrate as first and second electrodes, and a liquid crystal formed between the upper and lower substrates as a dielectric. will be. At this time, it is the role of the liquid crystal capacitor C _{LC to} maintain a data voltage value charged in each pixel electrode for a predetermined time.

Although not shown in the drawing, a separate storage capacitor Cst is formed between the pixel electrode and the common electrode to adjust the charging time of the liquid crystal.

Referring to the operation of the conventional liquid crystal display, the driving voltage (pulse signal) is sequentially applied to each of the gate lines G1, G2, ... Gn-1, Gn, and the corresponding gate line G1, The thin film transistor TFT connected to G2, ..., Gn-1, Gn is turned on, during which the data voltage applied to each data line D1, D2, D3, ..., Dn is applied to the pixel electrode. Is applied to charge the data voltage. At this time, the data voltage is charged in one frame period for each pixel electrode and maintained until the next signal is applied.

That is, the gate voltage is sequentially applied to each gate line every one frame time, and in the selected pixel to which the gate voltage is applied, the voltage of the gate electrode of the thin film transistor connected to the gate line becomes high, and the thin film transistor is turned on. In this case, the liquid crystal driving voltage is applied to the liquid crystal from the data line via the drain and the source of the thin film transistor to charge the pixel capacitance combined with the liquid crystal capacitance and the auxiliary capacitance. By repeating this operation, a voltage corresponding to the video signal is applied to the pixel capacitance of the front panel for each frame time.

Recently, the resolution of such an active matrix liquid crystal display device has been considerably increased. Accordingly, in the case of a high resolution liquid crystal display device, the number of gate lines and data lines constituting pixels increases.

Therefore, a plurality of gate driver ICs and data drive ICs corresponding to the number of the gate lines and the data lines must be mounted.

However, in the case of XGA (1024 × 768) class, since 3 sub pixels of data line 3072 (R, G, B constitute one pixel, 384 pins are required to correspond to 1024 × 3) and 768 gate lines. Data Driver IC with 8 Gates with 256 Pins

Three Iber ICs are required.

Here, since the data driver IC is more expensive than the gate driver IC, the data driver IC consumes about 100 mW, and the gate driver IC consumes about 20 mW, so that the data driver IC consumes more data than the gate driver IC. The manufacturing cost and power consumption are determined by the driver IC.

In addition, when a high resolution is realized in a panel of the same size, the width of each pixel becomes smaller, and as the ultra-miniaturization progresses, the driving circuit of the liquid crystal display device and the liquid crystal panel are connected in order to mount a drive IC corresponding to the pixel structure. This is getting harder.

In order to solve this problem, research on an array structure for reducing the number of data lines has been actively conducted.

A first object of the present invention is to provide an array substrate for a liquid crystal display device having an array structure capable of reducing the number of data lines and keeping the capacitor capacitance of the entire pixel constant in response to misalignment of the mask.

Another object of the present invention is to provide a method of driving an array substrate for a liquid crystal display device which can improve image quality by changing a driving order of thin film transistors of left and right pixels using a common data line.

According to an aspect of the present invention, there is provided an array substrate for a liquid crystal display device, including: first and second gate lines adjacent to each other, and third and fourth gate lines spaced apart from each other by a predetermined distance; A common data line crossing the first to fourth gate lines and defining first to fourth pixels left, right, up, and down; First to fourth thin film transistors formed in a horizontal direction in pixels adjacent to the common data line in left and right directions; And first to fourth pixel electrodes connected to each of the first to fourth thin film transistors.

In addition, the driving method of the array substrate for a liquid crystal display device according to the present invention in order to achieve the above-described second object, the first and second gate lines adjacent to each other and the third and fourth gate lines adjacent to each other spaced apart from each other, The common data lines cross each other to define first to fourth pixels, and the first to fourth thin film transistors formed in a horizontal direction from pixels adjacent to the left and right sides with respect to the data lines to drive the liquid crystal panel. The method of claim 1, wherein when a gate voltage is sequentially applied to the first to fourth gate lines, the first to fourth pixels are sequentially driven to pixels adjacent to left, right, top, and bottom with respect to the common data line. It is done.

The first to fourth pixels may be driven in the order of the top left, top right, bottom right, and bottom left with respect to the common data line.

The first to fourth pixels may be driven in the order of top right, top left, bottom left and bottom right with respect to the common data line.

The first and second gate lines may drive the first and second pixel electrodes formed on the same line.

The third and fourth gate lines may drive third and fourth pixel electrodes formed on the same line.

Hereinafter, an array substrate for a liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view showing a portion of an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

As illustrated in FIG. 3, an array substrate for a liquid crystal display according to the present invention has a structure in which pixels disposed adjacent to left and right share a data line and time-dividing data to each pixel.

That is, the array substrate for a liquid crystal display according to the present invention includes first and second gate lines 111a and 111b which are provided in neighboring first and second pixels P1 and P2 and are adjacent to each other. A common data line 112 is formed to cross the gate lines 111a and 111b and to supply the time-divided data signal to the first and second pixels P1 and P2. The first and second gate lines 111a are formed. And 111b and first and second thin film transistors TFT1 and TFT2 are formed at the intersection of the common data line 112.

The first and second thin film transistors TFT1 and TFT2 are formed in a horizontal direction with respect to the common data line 112.

The first thin film transistor TFT1 includes a gate electrode 121a protruding from the first gate line 111a, a semiconductor layer 116a formed on the gate electrode 121a, and the semiconductor layer 116a. And a source electrode 122a and a drain electrode 124a in contact with a predetermined region on the substrate, and a pixel electrode 113a formed in the first pixel P1 in contact with the drain electrode 124a.

The first thin film transistor TFT1 forms a first gate-source capacitor Cgs1 between the gate electrode 121a and the drain electrode 124a.

Meanwhile, in the neighboring second pixel P2 which shares the common data line 112 with the first pixel P1, the second thin film transistor TFT2 protrudes from the second gate line 111b. A gate electrode 121b, a semiconductor layer 116b formed on the gate electrode 121b, a source electrode 122b and a drain electrode 124b in contact with a predetermined region on the semiconductor layer 116b, and the drain And a pixel electrode 113b formed in the first pixel P1 in contact with the electrode 124b.

Here, the second thin film transistor TFT2 forms a second gate-source capacitor Cgs2 between the gate electrode 121b and the drain electrode 124b.

In this case, since the first and second thin film transistors TFT1 and TFT2 are formed in a horizontal direction with respect to the common data line 112, the drain electrodes forming the first gate-source capacitor Cgs1 ( If 124a overlaps the gate electrode 121a in the first direction and in the second direction, the drain electrode 124b forming the second gate-source capacitor Cgs2 is formed in the second direction from the first direction. It overlaps with the gate electrode 121b.

Therefore, when the photo process is performed to form the source electrode and the drain electrode pattern, a photo mask may be twisted so that the source electrode and the drain electrode pattern may be twisted up, down, left, and right. In this case, since the overlap directions of the gate electrodes 121a and 121b and the drain electrodes 124a and 124b of the first and second thin film transistors TFT1 and TFT2 are the same as described above, the first and second gate-source capacitors Cgs1. , Cgs2) increase and decrease the same.

Therefore, the entire gate-source capacitor capacity is uniform in the first and second pixels P1 and P2, and image quality defects can be prevented.

In the liquid crystal display according to the present invention, gate electrodes 121a and 121b protrude from the first and second gate lines 111a and 111b to correspond to the first thin film transistor TFT1 and the second thin film transistor TFT2. It is characterized by.

Hereinafter, for convenience of explanation, the first to fourth pixels in which the common data line and the first to fourth gate lines intersect are described.

The first and second gate lines drive first and second pixel electrodes formed on the same line, and the third and fourth gate lines drive third and fourth pixel electrodes formed on the same line. .

The gate electrode protruding from the second and fourth gate lines overlaps the first and third gate lines.

Although not shown, the second and fourth pixel electrodes may overlap the first and third gate lines.

Although not shown, each pixel electrode may overlap with an adjacent gate line to form storage.

In addition, the liquid crystal display according to the present invention reduces the number of data lines by half, thereby reducing data driver ICs that are expensive and require high power consumption.

In addition, as the number of data lines is reduced, the pitch margin of the data pad portion may be doubled, so that a design corresponding to a high resolution may be facilitated for a liquid crystal panel having the same size.

In order to mount a drive IC corresponding to a high resolution pixel structure, the driving circuit of the liquid crystal display and the liquid crystal panel are easily connected.

4 is a diagram illustrating an equivalent circuit diagram of an array substrate for a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 5 is a schematic view of a portion of FIG. 4, and FIG. 6 is a gate signal for driving the pixels of FIG. 5. It is a figure which shows.

As shown in FIG. 4 and FIG. 5, when the array substrate for a liquid crystal display according to the present invention is configured as a circuit diagram, the data lines are formed to be reduced by a factor of 1/2, and the left, right, It demonstrates as four pixels of upper and lower.

Hereinafter, the upper left pixel is described as a first pixel A, the upper right pixel is a second pixel B, the lower left pixel is a third pixel C, and the lower right pixel is a fourth pixel D. The first, second, The three and four pixels A, B, C, and D use one common data line 112 and four gate lines 111a, 111b, 111c, and 111d.

In addition, the common data line 112 and the four gate lines cross each of the first, second, third, and fourth pixels A, B, C, and D, and the first, second, third, and fourth thin films are formed at the intersections thereof. Transistors TFT1, TFT2, TFT3, and TFT4 are formed.

The first and second gate lines 111a and 111b are adjacent to each other in pairs, and the third and fourth gate lines 1113c and 111d are adjacent to each other in pairs.

When gate voltages are sequentially applied to the first, second, third, and fourth gate lines 111a, 111b, 111c, and 111d, the first to fourth pixels A, B, C, and D are one common data. Pixels adjacent to the line from left to right and top to bottom are sequentially driven.

Referring to FIG. 4, thin film transistors are formed at intersections of the plurality of gate lines GL1, GL2,..., GLn-1, GLm and the plurality of data lines DL1, DL2, DL3,..., DLn, respectively. (TFT) is provided, and is connected to the drain electrode of the thin film transistor to form a liquid crystal capacitor (C _LC ). The liquid crystal capacitor C _LC is not a separate device, but a pixel electrode on the lower substrate and a cavity electrode on the upper substrate as first and second electrodes, and a liquid crystal formed between the upper and lower substrates as a dielectric. At this time, it is the role of the liquid crystal capacitor C _{LC to} maintain a data voltage value charged in each pixel electrode for a predetermined time.

Although not shown in the drawing, a separate storage capacitor Cst is formed between the pixel electrode and the common electrode to adjust the charging time of the liquid crystal.

4 and 5, the operation of the liquid crystal display according to the present invention configured as described above will be briefly described. First to fourth gate lines GL1, GL2, GL3, and GL4 111a, 111b, and 111c may be described. When the driving voltage (pulse signal) is sequentially applied to, 111d, the thin film transistor TFT connected to the corresponding gate lines GL1, GL2,..., GLm-1, GLm is turned on, while the common data line ( Data voltages applied to DL1, DL2, DL3, ..., DLn) are applied to the pixel electrode to charge the data voltage. At this time, the data voltage is charged in one frame period for each pixel electrode and maintained until the next signal is applied.

That is, a gate voltage is sequentially applied to each of the first, second, third, and fourth gate lines 111a, 111b, 111c, and 111d every one frame time, and the gate voltage is applied to the first, second, third, and fourth gate lines 111a, 111b, 111c, and 111d. In the 3 and 4 pixels A, B, C, and D, the voltage of the gate electrode of the thin film transistor connected to the gate line becomes high, and the thin film transistor is turned on. In this case, the liquid crystal driving voltage is the data. It is applied to the liquid crystal from the line via the drain and the source of the thin film transistor to charge the pixel capacitance combined with the liquid crystal capacitance and the auxiliary capacitance. By repeating this operation, a voltage corresponding to the video signal is applied to the pixel capacitance on the front panel for each frame time.

As described above, two pairs of gate lines and one common data line correspond to each other to define the first to fourth pixels A, B, C, and D, and the driving order thereof is left top (A) → right top ( B) → right bottom (C) → left bottom (D) are sequentially driven as the gate voltage is sequentially applied to the gate line.

On the other hand, although not shown, in the order of the upper right (B) → upper left (A) → lower left (D) → lower right (C) with respect to the common data line according to the signal input direction or order of the gate line to which the gate voltage is applied. The first to fourth pixels may be driven, and the present invention may be applied to an embodiment conforming to the technical spirit of the present invention.

As described above, when gate voltages are sequentially applied to the first, second, third, and fourth gate lines, the first to fourth pixels sequentially drive pixels adjacent to each other from left to right on a common data line. In this case, if the capacity of the gate-source capacitor is different for each pixel, this can be compensated for.

For example, in a photo process to pattern the source electrode and the drain electrode, when the photo mask is misaligned and the arrangement of the gate electrode and the drain electrode is misaligned, a difference occurs in the gate-source capacitor capacity, which is the first gate. The source capacitor capacity is at a maximum value, the second gate-source capacitor capacity is at a minimum value, the third gate-source capacitor capacity is at a maximum value, and the fourth gate-source capacitor capacity is at a minimum value.

Therefore, when the first to fourth pixels are driven in the order A → B → C → D, the order of the gate-source capacitor values becomes maximum-minimum-minimum-maximum, which causes flickering, such as flicker of the screen. The image quality can be improved since it can be reduced.

As mentioned above, the present invention has been described in detail with reference to specific embodiments, which are intended to specifically describe the present invention, and the array substrate for a liquid crystal display device and a method of manufacturing the same according to the present invention are not limited thereto. It is apparent that modifications and improvements are possible by those skilled in the art.

According to the present invention, since two adjacent pixels share one data line in the liquid crystal display, the number of data lines of the liquid crystal panel may be reduced, thereby increasing the resolution.

In addition, according to the present invention, even when the source electrode and the drain electrode pattern are misaligned due to misalignment of the mask for forming the data line, the capacitor capacity of the entire pixel can be kept constant, so that the image quality of each pixel is uniform and the image quality of the entire liquid crystal panel is improved. There is a second effect that is improved.

In addition, the present invention sequentially drives the first to fourth pixels defined by the intersection of one common data line and the first, second, third, and fourth gate lines, and sequentially drives pixels adjacent to each other from left to right. There is a third effect of improving the image quality by preventing the flicker phenomenon such as flicker phenomenon.

Claims (14)

First and second gate lines adjacent to each other and third and fourth gate lines adjacent to each other spaced apart from each other by a predetermined distance; A common data line crossing the first to fourth gate lines and defining first to fourth pixels left, right, up, and down; First to fourth thin film transistors formed in a horizontal direction in pixels adjacent to the common data line in left and right directions; And first to fourth pixel electrodes connected to the first to fourth thin film transistors, respectively. The method of claim 1, And a gate electrode protruding from the first to fourth gate lines to correspond to the first to fourth thin film transistors. The method of claim 1, And a source electrode of the first to fourth thin film transistors protrudes from the common data line. The method of claim 1, And the first and second gate lines drive first and second pixel electrodes formed on the same line. The method of claim 1, And the third and fourth gate lines drive third and fourth pixel electrodes formed on the same line. The method of claim 1, And a gate electrode protruding from the second and fourth gate lines overlaps the first and third gate lines. The method of claim 1, And the second and fourth pixel electrodes overlap each other with the first and third gate lines. The method of claim 1, And each pixel electrode overlaps an adjacent gate line to further form a storage capacitor. First and second gate lines adjacent to each other, and third and fourth gate lines spaced apart from each other by a predetermined distance, and the common data line cross each other to define first to fourth pixels, and are adjacent to the data lines to the left and right sides. In the method for driving the liquid crystal panel formed by including the first to fourth thin film transistor formed in the horizontal direction in the pixel, When a gate voltage is sequentially applied to the first to fourth gate lines, the first to fourth pixels are sequentially driven to pixels adjacent to left, right, top, and bottom with respect to the common data line. A method of driving an array substrate for a device. The method of claim 9, Wherein each of the pixel electrodes overlaps an adjacent gate line to further form a storage capacitor. The method of claim 9, And first to fourth pixels are driven in the order of upper left, upper right, lower right and lower left with respect to the common data line. The method of claim 9, And first to fourth pixels are driven in the order of top right, top left, bottom left and bottom right with respect to the common data line. The method of claim 9, And said first and second gate lines drive first and second pixel electrodes formed on the same line. The method of claim 9, And the third and fourth gate lines drive third and fourth pixel electrodes formed on the same line.

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