KR20070003145A - Method for manufacturing semiconductor device - Google Patents

Abstract

A method for fabricating a semiconductor substrate is provided to increase the uniformity of a thickness of a polycrystalline silicon film between wafers in a lot and the uniformity of a thickness of a gate polycrystalline silicon film between lots. A substrate(110) having a silicon film(114) is prepared. a naturally oxidized film(116) is formed on an upper surface of the silicon film. The substrate is subjected to a first polishing process using a first slurry containing a ceria abrasive, to remove the naturally oxidized film from the upper portion of the silicon film. The silicon film is subjected to a second polishing process using a second slurry to planarize the silicon film.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

1 is a plan view showing a semiconductor device having a recessed (R) -gate structure according to the prior art.

2A to 2E are cross-sectional views illustrating a method of manufacturing the semiconductor device illustrated in FIG. 1.

3 is a transmission electron microscope (TEM) photograph of a semiconductor device corresponding to FIG. 2E.

4 and 5 are TEM photographs showing a semiconductor device corresponding to FIG. 2D.

6 is a view showing the amount of polishing between a polysilicon film and an oxide film when applying the method of manufacturing a semiconductor device according to the prior art.

7 is a view showing the amount of polishing per wafer when applying the method of manufacturing a semiconductor device according to the prior art.

8A and 8B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

9 is a view for explaining the structure of the slurry shown in Figure 8a.

FIG. 10 is a view illustrating the polymer structure contained in the slurry shown in FIG. 8A. FIG.

FIG. 11 shows the amount of polishing of the silicon film by the silica abrasive in FIG. 8B. FIG.

FIG. 12 is a diagram illustrating a silicon film thickness variation between wafers when a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention is applied. FIG.

<Explanation of symbols for main parts of the drawings>

10, 110: semiconductor substrate

12, 112: device isolation film

14: trench

16, 114: silicon film

18, 116: natural oxide film

118, 120: slurry

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device using an R-gate process capable of forming a three-dimensional gate structure.

In recent years, as the design rules of semiconductor devices have gradually decreased, the margin of manufacturing processes has gradually decreased. In particular, in the case of a DRAM (Dynamic Random Access Memory) device, a problem occurs in forming the device due to deterioration of the refresh characteristics. In order to solve this problem, a gate process for forming a three-dimensional gate structure instead of a conventional two-dimensional gate structure, a so-called R-gate process, has been introduced.

Hereinafter, a method of manufacturing a semiconductor device to which an R-gate process is applied will be described.

FIG. 1 is a plan view illustrating a method of manufacturing a semiconductor device according to the prior art, and FIGS. 2A to 2E are cross-sectional views illustrating a cutting line taken along the line I-I of FIG. 1.

First, as shown in FIGS. 1 and 2A, a shallow trench isolation (STI) process is performed to form the device isolation layer 12 in the semiconductor substrate 10 in a field region.

Subsequently, as illustrated in FIG. 2B, an R-gate etching process is performed to form an R-gate trench 14 having a predetermined depth T2 in the active substrate 10.

Meanwhile, the R-gate etching process is performed by first forming a R-gate mask by performing a mask process and then etching the substrate 10 which performs an etching process using the mask.

Next, as shown in FIG. 2C, a polysilicon film 16 for R-gate is deposited on the entire structure so that the trench 14 is buried. At this time, as shown by the 'A' in the figure, the polysilicon film 16 of the portion corresponding to the trench 14 is recessed due to the step by the trench 14 to generate a valley portion. Such unnecessary valleys A may cause disconnection due to poor step coverage during the subsequent gate electrode deposition process.

Subsequently, as illustrated in FIGS. 2D and 2E, a CMP (Chemical Mechanical Polishing) process is performed to polish the polysilicon film 16. As a result, all of the valleys A shown in FIG. 2C are removed to planarize the upper portion. The state in which the valley portion A is removed can also be confirmed through a transmission electron microscope (TEM) photograph shown in FIG. 3.

However, the following problem occurs in the method of manufacturing a semiconductor device according to the prior art.

First, as shown in FIG. 2D, the upper surface is not uniform as the 'A' region due to the step of the trench 14 after deposition of the polysilicon film 16. As a result, in the subsequent deposition process of the tungsten silicide layer for the gate electrode, the covering property due to the underlying topology is degraded to cause disconnection of the gate electrode, or the self alignment contact during the etching process to form the subsequent landing plug. (Self Align Contact; SAC) cause a failure. In order to solve this problem, the polysilicon layer 16 is generally deposited, and then a CMP process is introduced as a planarization process to planarize the top surface of the polysilicon layer 16.

However, as shown in FIG. 2D, a native oxide 18 is grown on the upper surface of the polysilicon film 16 before the CMP process. The natural oxide film 18 can be confirmed through the TEM photograph shown in FIGS. 4 and 5. The natural oxide film 18 is not easily removed by a poly polishing slurry due to its characteristics, and its thickness is several tens of micrometers or less, and its thickness varies from wafer to wafer, which acts as a factor of deteriorating uniformity in the CMP process.

However, it is not possible to accurately know the growth thickness of the native oxide film 18 until the CMP process. This is because the deposition of the polysilicon film 16 continues to grow to a constant thickness until the TEM specimen is fabricated. In addition, because of its small thickness, it is difficult to monitor on the actual in-line, and it is difficult to set the polishing time in the CMP process.

Meanwhile, in the semiconductor device manufacturing process according to the prior art, a slurry having a high polishing selectivity between the oxide film and the polysilicon film is used during the CMP process. In this case, as shown in Fig. 6, the selectivity between the polysilicon film and the oxide film is shown to be approximately 20. In addition, as shown in FIG. 7, the thickness variation of the polysilicon film between wafers in the lot becomes approximately 100 kPa. As such, if the thickness variation of the gate polysilicon film in the lot is severe, the subsequent exposure and etching process margins are insufficient. In addition, a wafer having a low thickness of the polysilicon film during the gate etching process may damage the substrate and cause a defect of the device, thereby reducing the yield and increasing the manufacturing cost.

Therefore, in the case of the slurry used for polishing a polysilicon film, the polishing rate for the polysilicon film is large, so that wafer to wafer variation and lot to lot variation remain after the gate polysilicon film polishing. It is difficult to control the thickness of the film constantly. In particular, the edge of the wafer is polished faster than the center portion, so that the thickness of the film remaining at the edge portion is significantly lower than the center portion. As a result, the CMP process lacks a margin and thus is difficult to apply to an actual device, and a device defect occurs due to a lack of subsequent process margins due to different thicknesses of polysilicon film for each wafer.

Accordingly, the present invention has been made to solve the above problems, and improves the uniformity of the thickness of the polysilicon film between the wafers in the lot and the uniformity of the thickness of the gate polysilicon film between the lots, thereby ensuring a process margin during subsequent processing, thereby resulting in device defects. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can improve the yield by preventing the.

According to an aspect of the present invention, there is provided a substrate including a silicon film having a natural oxide film formed on an upper surface thereof, and any one polymer selected from anionic polymers or at least two kinds of the polymers. Removing the natural oxide film formed on the silicon film by performing a first polishing process using a first slurry containing a ceria abrasive compound in which a mixture of polymers of the polymer is mixed; and removing the silicon film from which the natural oxide film is removed. It provides a method for manufacturing a semiconductor device comprising the step of performing a second polishing step using a second slurry for the planarization.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

Example

8A and 8B are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention. For convenience of explanation and explanation, the manufacturing process of the semiconductor device having the R-gate structure will be described as an example.

First, as shown in FIG. 8A, a trench trench (STI) etching process is performed to form trenches (not shown) in the semiconductor substrate 110 in the field region. At this time, the trench has a constant slope (slope), it is formed to a depth of 1500 ~ 3000Å.

Subsequently, an insulating film for device isolation film is deposited so as to fill the trench. In this case, the insulating film for device isolation film is preferably formed of a high density plasma (HDP) oxide film having good coating properties.

Next, the CMP process is performed to planarize the HDP oxide film. As a result, an isolation layer 112 is formed in the trench.

Next, a trench for a gate electrode (not shown) is formed in the substrate 110 of the active region. At this time, the trench for the gate electrode is formed to a depth of 500 ~ 2500Å. The trench forming process for the gate electrode may be performed by applying a hard mask scheme. In this case, the hard mask may be formed of a doped silicon film, a polysilicon film, or a nitride film. For example, when the nitride film is formed, the pad nitride film (not shown) formed on the substrate 110 during the STI etching process may be used as a hard mask without being removed.

Subsequently, a gate oxide film (not shown) is formed along the stepped portion of the entire structure including the trench for gate electrodes. At this time, the gate oxide film is formed by a wet oxidation process. For example, the gate oxide film is formed by performing a wet oxidation process at a temperature of about 750 to 800 ° C., then increasing the temperature to about 850 to 950 ° C. and performing an annealing process for 20 to 30 minutes in a nitrogen (N ₂ ) atmosphere.

Subsequently, the gate electrode silicon film 114 is deposited on the gate oxide film to fill the gate electrode trench. At this time, the gate electrode silicon film 114 is formed of a doped silicon film or a polysilicon film with a thickness of about 500 to 2000 micrometers. For example, the gate electrode silicon film 114 is formed by using any one source gas selected from a group of source gases such as SiH ₄ and Si ₂ H _6, and using a group of doping gases such as PH ₃ and AsH _3. do. The gate electrode silicon film 114 may be formed in a stacked structure, in which case a doped silicon film and an un-doped silicon film are stacked.

On the other hand, as shown in the figure, the gate electrode silicon film 114 of the portion corresponding to the trench is recessed due to the step by the trench during the deposition process of the silicon film 114 for the gate electrode to generate a valley portion. Such unnecessary valleys A may cause disconnection due to poor step coverage during the subsequent gate electrode deposition process. In addition, the surface of the silicon film 114 is oxidized by oxygen caused by exposure to air in the gate electrode silicon film 114 to form a natural oxide film 116.

Subsequently, a CMP process is performed. The CMP process is largely performed by a first polishing process for removing the native oxide film 116 and a second polishing process for planarizing the silicon film 114.

First Polishing Process

As shown in FIG. 9, the first polishing process is performed using a slurry containing a ceria (CeO ₂ ) abrasive compounded with an anionic polymer having a high etching selectivity between an oxide film and a silicon film. At this time, as shown in Figure 10, the polymer uses a carbon compound having a molecular weight of at least 100,000, preferably 100,000 to millions. For example, the polymer may be any one of all the polymer containing a group having an R a group of functions, such as -COOH, -NH _2, -COHN _2, and -NO _2. In addition, the polymer may be a polymer in acid or salt form. The slurry contains a ceria abrasive in which any one of the polymers selected above or the polymer of the polymer is combined. Preferably, a polymer containing -COOH is used.

For example, anionic -COOH (hereinafter referred to as carboxyl group) acts as a complexing agent that can complex with metal elements in solution. The polymer containing such a carboxyl group is polyacrylic acid, but commercially available derivatives thereof include NOVEON's trade name "CARBOPOL". Typically, "CARBOPOL 940" having a molecular weight of 4 million, or a molecular weight of about 1.25 million There is a compound called “CARBOPOL 941.” In addition, there are all commercially available anionic polymers, including Aldrich's polyacrylic acid series compounds, which are long stretched in chains by the repulsive force between the anions in the basic solution. A complex compound may be formed with a metal compound having a cation.

As shown in FIG. 9, the slurry 118 used in the first polishing process forms a complex round like a ball by the interaction between the polymer and the ceria abrasive particles described above. That is, the slurry 118 is present in a form in which many ceria abrasive particles are enclosed in a round ball by a polymer. This slurry 118 is present in the solution in a size of several hundred to several thousand nm in diameter. On the other hand, the polymer content contained in the slurry 118 is 0.01 to 5.0 wt% based on the total weight of the slurry 118. More preferably, you may be 0.05-1.5 wt%.

On the other hand, in order for a polymer such as polyacrylic acid to be activated in a slurry solution, a basic compound must be added as a neutralizing agent. Representative basic compounds include hydroxides of alkali metals such as potassium hydroxide, ammonium hydroxide, MonoEthanol Amine (MEA), DiEthanol Amine (DEA), and TriEthanol Amine (TEA). That is, the slurry 118 is used by mixing at least one or more selected from the group of organic salts such as hydroxide of alkali metal, ammonium hydroxide, MEA, DEA, and TEA.

The selectivity ratio between the oxide film and the silicon film of the slurry 118 described above is controlled to 10: 1 to several hundred: 1. More preferably, the selection ratio is controlled to 20: 1 to 100: 1. In addition, the first polishing process is performed using the slurry 118, but is performed by rotating the turn table at 10 to 100 rpm at a polishing pressure of about 1 to 10 psi. As a result, the natural oxide film 116 is selectively polished and removed. As shown in FIG. 11, when the slurry 118 of the present invention is used, the polishing of the silicon film 114 is hardly performed.

Second Polishing Process

The second polishing process is performed on the silicon film 114, as shown in FIG. 8B, and uses a slurry 120 containing silica (SiO ₂ ) abrasive, which is a dedicated abrasive for the polysilicon film. In this case, as the silica abrasive, a colloidal silica or fumed abrasive having a size of about 10 to 5000 nm, preferably about 50 to 1000 nm is used. For example, Fujimi's "DCMO4" slurry is used.

Meanwhile, alumina, titania, zirconia, ceria, germania, magnesia, silicon nitride, silicon carbide, boron carbide, titanium carbide, titanium diboride, tungsten carbide, diamond, and co-forming thereof, which can polish the silicon film 114 instead of the silica abrasive Any one selected from the group consisting of products, and combinations thereof. Preferably, silica and alumina are used.

In addition, the slurry 120 may include a pH regulator (pH reducing agent or increasing agent) according to the mixing ratio to have a pH of 4 to 10, preferably 5 to 8 range. In this case, the pH adjusting agent may be used by adding an inorganic acid (HCl) or an inorganic base (NaOH), but more preferably, it is preferable to use an organic acid or an organic salt in order to minimize metal or halogen contamination of the semiconductor device. Do. In addition, the pH increasing agent uses any one organic salt selected from a group of organic salts such as ammonium hydroxide, MEA, DEA, and TEA. And, the pH reducing agent uses all organic acids such as acetic acid.

On the other hand, it is preferable to perform using a hard pad in a 2nd grinding | polishing process.

Since the process is the same as the general process, a description thereof will be omitted here.

On the other hand, Figure 12 is a scatter diagram showing the thickness of the polysilicon film between the wafer in the lot when applying the CMP process according to a preferred embodiment of the present invention, the range of the thickness of the inter-wafer polysilicon film is conventional, that is, using a single slurry It can be significantly reduced than the case of the CMP process. In other words, the thickness of the polysilicon film can be controlled to be constant.

In addition, the present invention can be applied not only to a semiconductor device having an R-gate structure, but also to any process of planarization using a CMP process on a polysilicon film formed on a semiconductor device.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, in the CMP process for planarizing the polysilicon film, a natural formed on the surface of the polysilicon film using a slurry containing an anionic polymer or a compound containing a ceria abrasive compound thereof. After removing the oxide film, a slurry containing silica abrasive is used to polish and planarize the polysilicon film from which the natural oxide film is removed, thereby improving the uniformity of the thickness of the polysilicon film between the wafers in the lot and the uniformity of the thickness of the gate polysilicon film between the lots. By securing the process margin during the process it is possible to prevent the failure of the device to improve the yield.

Claims (20)

Providing a substrate including a silicon film having a natural oxide film formed on an upper surface thereof; A first polishing process using a first slurry containing a ceria polishing compound comprising a mixture of any one selected from anionic polymers or a mixture of at least two kinds of polymers is formed on the silicon film; Removing the native oxide film; And Performing planarization by performing a second polishing process using a second slurry on the silicon film from which the natural oxide film is removed. Method of manufacturing a semiconductor device comprising a. The method of claim 1, The polymer is a method of manufacturing a semiconductor device having a molecular weight of at least 100,000. The method of claim 2, The polymer is -COOH, -NH _2, -COHN method of manufacturing a semiconductor device having any one of a polymer containing a group having a functional group of R, such as ₂ and -NO _2. The method of claim 3, wherein The polymer is a method of manufacturing a semiconductor device in which at least one of polyacrylic acid and derivatives of the polyacrylic acid is mixed. The method of claim 2, The polymer is a method of manufacturing a semiconductor device having an acid or salt form. The method according to any one of claims 1 to 5, A method of manufacturing a semiconductor device in which the polymer content contained in the first slurry is 0.01 to 5.0 wt% based on the total weight of the first slurry. The method of claim 6, The first slurry is a method of manufacturing a semiconductor device further comprising a basic compound. The method of claim 7, wherein The basic compound is at least one selected from a group of organic salts such as hydroxides of alkali metals, ammonium hydroxide, MonoEthanol Amine (MEA), DiEthanol Amine (DEA), and TriEthanol Amine (TEA), or the organic salts are mixed. The manufacturing method of the semiconductor element of the semiconductor element which is a mixture. The method of claim 8, And the first polishing step is performed such that the selectivity ratio between the natural oxide film and the silicon film is 10: 1 to 100: 1. The method of claim 9, The first polishing process is a semiconductor device manufacturing method performed by rotating the turntable at 10 ~ 100rpm at a polishing pressure of about 1 ~ 10psi. The method of claim 6, The second slurry is an abrasive of any one selected from silica, alumina, titania, zirconia, ceria, germania, magnesia, silicon nitride, silicon carbide, boron carbide, titanium carbide, titanium diboride, tungsten carbide and diamond, and the selected abrasive A method for manufacturing a semiconductor device containing any one selected from the group consisting of a coformed product of these and a combination of the selected abrasives. The method of claim 11, The silica abrasive is a manufacturing method of a semiconductor device having a colloidal silica (fumed) form or a fumed (colloidal silica) of about 10 ~ 5000nm size. The method of claim 11, The second slurry is a method of manufacturing a semiconductor device further comprises a pH regulator according to the mixing ratio to have a range of pH 4 ~ 10. The method of claim 13, The pH adjuster is a method of manufacturing a semiconductor device using an inorganic acid (HCl) or inorganic base (NaOH) is added. The method of claim 13, The pH adjusting agent is a method of manufacturing a semiconductor device using an organic acid or an organic salt. The method of claim 13, PH increasing agent of the pH adjuster using a semiconductor salt of any one selected from the group of organic salts such as ammonium hydroxide, MEA, DEA and TEA. The method of claim 13, The method of manufacturing a semiconductor device using a pH reducing agent of the pH regulator is an organic acid. The method of claim 6, And the silicon film is formed of a doped silicon film or a polysilicon film. The method of claim 18, Forming a trench in an active region of the substrate before forming the silicon film; And And forming a gate oxide film along the surface of the trench. The method of claim 19, And the silicon film is formed so that the trench is buried.

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