KR20070002784A - Shift register and liquid crystal display using the same - Google Patents

Abstract

A shift register and a liquid crystal display device having the same are provided to stabilize an output signal of a dummy stage by increasing the size of a reset transistor in the dummy stage. A shift register includes an n-th stage(31) and a dummy stage(32). An output buffer includes a pull-up transistor(T6), which outputs clock signals(CLKV,CLKVB) under the control of a Q node, and a pull-down transistor(T7), which outputs a low driving voltage(VSS) under the control of a QB node. A controller includes first to fifth transistors, which control the Q and QB nodes. High and low driving voltages and an output signal from the previous stage are supplied to the n-th stage and the dummy stage. The first and second clock signals of different phases are supplied to the n-th and dummy stages. The QB node of a final stage, instead of a start pulse, is used to reset the dummy stage.

Description

SHIFT REGISTER AND LIQUID CRYSTAL DISPLAY USING THE SAME}

1 is a view schematically showing a conventional liquid crystal display device.

FIG. 2 is a schematic view of the gate driving circuit of FIG. 1; FIG.

3 is a schematic representation of a shift register in accordance with the present invention;

4A and 4B are driving waveform diagrams of FIG. 3.

5 schematically illustrates another example of a shift register according to the present invention;

6, 7A and 7B show the shift register output and Q node characteristics according to FIGS. 3 and 5;

8 is a view showing a first embodiment of a dummy stage according to the present invention.

Fig. 9 is a drive waveform diagram of the first and second embodiments.

FIG. 10 is a drive waveform diagram for explaining the period T3 in FIG. 9; FIG.

11A and 11B show simulation results according to FIG. 8.

12 is a view showing a second embodiment of a dummy stage according to the present invention;

13 is a view showing a third embodiment of a dummy stage according to the present invention;

14A and 14B are drive waveform diagrams of the third to tenth embodiments.

15 is a view showing a fourth embodiment of a dummy stage according to the present invention;

16 is a view showing a fifth embodiment of a dummy stage according to the present invention;

17 is a view showing a sixth embodiment of a dummy stage according to the present invention;

18 is a view showing a seventh embodiment of a dummy stage according to the present invention.

19 is a view showing an eighth embodiment of a dummy stage according to the present invention;

20 is a ninth embodiment of a dummy stage according to the present invention;

21 is a view showing a tenth embodiment of a dummy stage according to the present invention;

22 is a view showing an eleventh embodiment of a dummy stage according to the present invention.

23 is a drive waveform diagram of an eleventh and twelfth embodiments;

24 is a twelfth embodiment of a dummy stage according to the present invention;

Description of the main parts of the drawing

11 data driving circuit 12 gate driving circuit

13: liquid crystal display panels 31, 32, 42: stage

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a shift register and a liquid crystal display device using the same for resetting a dummy stage and improving the quality of a gate pulse while reducing wiring space and parasitic capacitance.

Liquid crystal displays are widely used in display devices of office equipment, monitors of computers, and even large-screen televisions with the recent development of process and driving technologies. Such a liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display device includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.

Referring to FIG. 1, in the conventional LCD, m × n liquid crystal cells Clc are arranged in a matrix type, m data lines D1 to Dm and n gate lines G1 to Gn. Intersect with the liquid crystal display panel 13 to which the thin film transistor TFT is connected, and the data driver circuit 11 for supplying data to the data lines D1 to Dm of the liquid crystal display panel 13. And a gate driving circuit 12 supplying a scan pulse to the gate lines G1 to Gn.

The liquid crystal display panel 13 is formed by bonding a thin film transistor substrate on which a thin film transistor array is formed and a color filter substrate on which a color filter array is formed, with the liquid crystal layer interposed therebetween. The data lines D1 to Dm and the gate lines G1 to Gn formed on the thin film transistor substrate of the liquid crystal display panel 13 are perpendicular to each other. The thin film transistor TFT connected to the intersection of the data lines D1 to Dm and the gate lines G1 to Gn may connect the data lines D1 to Dn in response to a scan pulse of the gate lines G1 to Gn. The supplied data voltage is supplied to the pixel electrode of the liquid crystal cell Clc. A black matrix, a color filter, a common electrode, and the like are formed on the color filter substrate. Accordingly, in the liquid crystal cell Clc, the liquid crystal having dielectric anisotropy is rotated to adjust the light transmittance by a potential difference between the data voltage supplied to the pixel electrode and the common voltage supplied to the common electrode. On the thin film transistor substrate and the color filter substrate of the liquid crystal display panel 13, a polarizing plate having an optical axis orthogonal to each other is attached, and an alignment layer for determining the pretilt angle of the liquid crystal is further formed on the inner side of the liquid crystal layer. In addition, a storage capacitor Cst is further formed in each of the liquid crystal cells Clc. The storage capacitor Cst is formed between the pixel electrode and the front gate line, or is formed between the pixel electrode and a common line (not shown) to keep the data voltage charged in the liquid crystal cell Clc constant.

The data driving circuit 11 converts the input digital video data into an analog data voltage using a gamma voltage and supplies it to the data lines D1 to Dm.

The gate driving circuit 12 sequentially supplies scan pulses to the gate lines G1 to Gn to select a horizontal line of the liquid crystal cell Clc to which data is to be supplied.

Specifically, as shown in FIG. 2, the gate driving circuit 12 includes a stage connected to each gate line, a high potential driving voltage VDD, a low potential driving voltage VSS, and a start pulse Vst. And a clock signal CLK. The stage is driven using the clock signal CLK by receiving the high potential driving voltage VDD, the low potential driving voltage VSS, and the start pulse Vst. Each stage supplies one output voltage Vg_out to each gate line as a scan pulse for one frame period. These outputs occur sequentially, with each output acting as a start pulse for the next stage drive and a reset signal for resetting the previous stage. The dummy stage must be additionally provided to reset the nth stage. In order to reset this dummy stage, the start pulse Vst is generally used. However, since the wiring of the start pulse Vst must be extended throughout the shift register, not only the layout space is lost but also the wiring of the start pulse Vst is vertically arranged so that the parasitic capacitance is increased due to overlap with the horizontal lines. There is a problem that the dummy stage output signal is distorted due to the increased parasitic capacitance.

Accordingly, an object of the present invention is to provide a shift register and a liquid crystal display using the same to reset the output of the dummy stage and stabilize the output of the dummy stage while reducing unnecessary wiring space and parasitic capacitance.

In order to achieve the above object, the shift register according to the present invention controls the charging of the output terminal in response to the voltage of the first node, respectively, and controls the discharge of the output terminal in response to the voltage of the second node to sequentially output the output signal. A plurality of stages for shifting; The output of the dummy output terminal connected to the first node of the last stage generating the last output signal of the plurality of stages is controlled in response to the voltage of the third node and the third node in response to the voltage of the fourth node. A dummy stage for resetting is provided.

The dummy stage is supplied with a final stage output signal, a high potential driving voltage, a low potential driving voltage, and a clock signal.

The dummy stage includes an output buffer for supplying an output signal to an output terminal; A control unit for controlling the output buffer

The output buffer includes a pull-up transistor controlled by the third node to supply one of a high voltage and a low voltage to the output terminal according to a clock signal.

The control unit may include a first transistor configured to receive a last stage output signal and to be turned on to supply a high voltage to a third node to turn on the pull-up transistor to supply a first clock signal to the output terminal; A fourth transistor configured to receive the high voltage of the second clock signal and to be turned on to supply a high potential driving voltage to the fourth node; Third and third a transistors configured to discharge the third node by being turned on through a high voltage of the second node; A fifth transistor configured to receive the output signal of the last stage to be turned on to discharge a fourth node; And a fifth a transistor configured to discharge the fourth node by being turned on through the high voltage of the first node.

The controller may include: a first transistor configured to receive an output signal of a last stage and to be turned on to supply a high voltage to a third node to turn on the pull-up transistor to supply a first clock signal to the output terminal; A fourth a transistor configured to charge the fifth node with a high potential driving voltage by being turned on by receiving a high voltage of the fourth clock signal; A fourth transistor configured to charge the fourth node to the high potential driving voltage by being turned on by receiving the high voltage of the fifth node; A fourth b transistor configured to discharge the fifth node by turning on the high voltage of the second clock signal; A fourth c transistor configured to discharge the fifth node by being turned on by receiving the output signal of the last stage; Third and third a transistors configured to discharge the third node by being turned on through a high voltage of the fourth node; A fifth a transistor configured to discharge the fourth node by being turned on by receiving a high voltage from the third node; A fifth transistor configured to receive the output signal of the last stage to be turned on to discharge a fourth node; And a fifth i transistor configured to discharge the fourth node by being turned on by receiving the high voltage of the second clock signal.

The output buffer further includes a pull-down transistor controlled by a fourth node to supply a low potential driving voltage to the output terminal.

The fourth node comprises a first QB node for discharging the third node during an odd frame period; And a second QB node for discharging the third node during the even frame period.

The dummy stage is supplied with an odd frame high potential driving voltage in the case of an odd frame and an even frame high potential driving voltage in the case of an even frame.

The control unit includes a first control unit for charging and discharging a third node; A second control unit for charging and discharging the first QB node; And a third controller for charging and discharging the second QB node.

The first control unit receives the output signal of the last stage and is turned on to supply a high voltage to the third node to turn on the pull-up transistor to supply a first clock signal to the output terminal. It is provided.

The second controller includes: a fourth O transistor which charges the first QB node to the odd frame high potential driving voltage by being turned on by receiving the odd frame high potential driving voltage; A third_O and third a_O transistor configured to discharge the third node by being turned on by receiving the high voltage of the first QB node; A fifth_O transistor configured to discharge the first QB node by being turned on by receiving a high voltage of the last stage output signal; A fifth a_O transistor configured to discharge the first QB node by being turned on by receiving the high voltage of the third node; And a fifth i_O transistor configured to discharge the first QB node by being turned on by receiving the high voltage of the second QB node.

The third controller comprises: a fourth E transistor to charge the second QB node to the even frame high potential driving voltage by being turned on by receiving the even frame high potential driving voltage; Third_E and thirda_E transistors configured to discharge the third node by being turned on by being supplied with the high voltage of the second QB node; A fifth_E transistor configured to receive the high voltage of the last stage output signal and to be turned on to discharge the second QB node; A 5a_E transistor configured to discharge the second QB node by being turned on by receiving the high voltage of the third node; And a fifth i_E transistor configured to discharge the second QB node by being turned on by receiving the high voltage of the first QB node.

The second controller includes: a fourth O transistor which charges the first QB node to the odd frame high potential driving voltage by being turned on by receiving the odd frame high potential driving voltage; A third_O and third a_O transistor configured to discharge the third node by being turned on by receiving the high voltage of the first QB node; A fifth_O transistor configured to discharge the first QB node by being turned on by receiving a high voltage of the last stage output signal; A fifth a_O transistor configured to discharge the first QB node by being turned on by receiving the high voltage of the third node; And a fifth i_O transistor configured to discharge the first QB node by being supplied with an even frame high potential driving voltage.

The third controller comprises: a fourth E transistor to charge the second QB node to the even frame high potential driving voltage by being turned on by receiving the even frame high potential driving voltage; Third_E and thirda_E transistors configured to discharge the third node by being turned on by being supplied with the high voltage of the second QB node; A fifth_E transistor configured to receive the high voltage of the last stage output signal and to be turned on to discharge the second QB node; A 5a_E transistor configured to discharge the second QB node by being turned on by receiving the high voltage of the third node; A fifth i_E transistor is provided to discharge the second QB node by being turned on by receiving the odd frame high potential driving voltage.

The second control unit includes: a 4a_O transistor configured to receive an odd frame high potential driving voltage and to be turned on to supply the odd frame high potential driving voltage to a fifth node; A fourth_O transistor configured to receive a high voltage from the fifth node and turn on to charge the first QB node to an odd frame high potential driving voltage; A fourth b_O transistor configured to discharge the fifth node by turning on the high voltage of the last stage output signal; A fourth c_O transistor configured to discharge the fifth node by being turned on by receiving the high voltage of the third node; A third_O and third a_O transistor configured to discharge the third node by being turned on by receiving the high voltage of the first QB node; A fifth_O transistor configured to discharge the first QB node by being turned on by receiving the high voltage of the last stage output signal; A fifth a_O transistor configured to discharge the first QB node by being turned on by receiving the high voltage of the third node; And a fifth i_O transistor configured to discharge the first QB node by being turned on by receiving the high voltage of the second QB node.

The third controller includes: a 4a_E transistor for supplying an even frame high potential driving voltage to a sixth node by being turned on by receiving the even frame high potential driving voltage; A fourth_E transistor configured to receive a high voltage from the sixth node and turn on to charge the second QB node to an odd frame high potential driving voltage; A fourth b_E transistor configured to discharge the sixth node by being turned on by receiving the high voltage of the last stage output signal; A fourth c_E transistor configured to discharge the sixth node by turning on the high voltage of the third node; Third_E and thirda_E transistors configured to discharge the third node by being turned on by receiving the high voltage of the second QB node; A fifth_E transistor configured to discharge the second QB node by being turned on by receiving the high voltage of the last stage output signal; A 5a_E transistor configured to discharge the second QB node by being turned on by receiving the high voltage of the third node; And a fifth i_E transistor configured to discharge the second QB node by being turned on by receiving the high voltage of the first QB node.

The second control unit includes: a 4a_O transistor configured to receive an odd frame high potential driving voltage and to be turned on to supply the odd frame high potential driving voltage to a fifth node; A fourth_O transistor configured to receive a high voltage from the fifth node and turn on to charge the first QB node to an odd frame high potential driving voltage; A fourth b_O transistor configured to discharge the fifth node by turning on the high voltage of the last stage output signal; A fourth c_O transistor configured to discharge the fifth node by being turned on by receiving the high voltage of the third node; A third_O and third a_O transistor configured to discharge the third node by being turned on by receiving the high voltage of the first QB node; A fifth_O transistor configured to discharge the first QB node by being turned on by receiving the high voltage of the last stage output signal; A fifth a_O transistor configured to discharge the first QB node by being turned on by receiving the high voltage of the third node; And a fifth i_O transistor configured to discharge the first QB node by being supplied with an even frame high potential driving voltage.

The third controller includes: a 4a_E transistor for supplying an even frame high potential driving voltage to a sixth node by being turned on by receiving the even frame high potential driving voltage; A fourth_E transistor configured to receive a high voltage from the sixth node and turn on to charge the second QB node to an odd frame high potential driving voltage; A fourth b_E transistor configured to discharge the sixth node by being turned on by receiving the high voltage of the last stage output signal; A fourth c_E transistor configured to discharge the sixth node by turning on the high voltage of the third node; Third_E and thirda_E transistors configured to discharge the third node by being turned on by being supplied with the high voltage of the second QB node; A fifth_E transistor configured to discharge the second QB node by being turned on by receiving the high voltage of the last stage output signal; A 5a_E transistor configured to discharge the second QB node by being turned on by receiving the high voltage of the third node; And a fifth i_E transistor configured to discharge the second QB node by being turned on by receiving an odd frame high potential driving voltage.

A first pull-down transistor controlled by a first QB node to supply a low potential driving voltage to the output terminal; And a second pull-down transistor controlled by a second QB node to supply a low potential driving voltage to the output terminal.

The liquid crystal display according to the present invention comprises: a liquid crystal display panel in which a plurality of gate lines and a plurality of data lines intersect and a plurality of liquid crystal cells are disposed; A plurality of stages for sequentially shifting the output signal by controlling the charging of the output terminal in response to the voltage of the first node and controlling the discharge of the output terminal in response to the voltage of the second node, the last output of the plurality of stages The charging of the dummy output terminal connected to the first node of the last stage of generating a signal is controlled in response to the voltage of the third node and the discharge of the dummy output terminal is controlled in response to the voltage of the fourth node. A gate driver sequentially supplying gate pulses to the gate lines, including a dummy stage for resetting the third node in response to a voltage of a node; And a data driving circuit for supplying a data voltage to the data lines.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 3 to 24.

3 is a view schematically showing a shift register according to the present invention.

Referring to FIG. 3, the n-th stage 31 and the dummy stage 32 are stored under the control of the pull-up transistor T6 and the QB node that output the clock signals CLKV and CLKVB under the control of the Q node. An output buffer comprising a pull-down transistor T7 for outputting the potential driving voltage VSS, and a control unit comprising first to fifth transistors T1 to T5 for controlling the Q node and the QB node. The n-th stage 31 and the dummy stage 32 are supplied with the high potential driving voltage and the low potential driving voltages VDD and VSS and the output signals of the previous stage, and the phases are different from each other as shown in FIGS. 4A and 4B. The other first and second clock signals CLKV and CLKVB are supplied. Hereinafter, an operation process of the n-th stage 31 and the dummy stage 32 will be described in detail with reference to the driving waveforms shown in FIGS. 4A and 4B, respectively.

First, when the n-th stage 31 refers to FIG. 4A, the first transistor T1 is turned on by the high voltage of the n-th stage output signal Vg_outn-1 in the period A so that the high voltage is Q node. Pre-charged. The pull-up transistor T6 is turned on by the high voltage pre-charged to the Q node, and the low voltage of the first clock signal CLKV is supplied to the n-th gate line GLn as the output signal Vg_outn. . At this time, the QB node is in a low voltage state by the fifth transistor T5 turned on according to the high voltage of the Q node, and the third and pull-down transistors T3 and T7 are turned off.

In the period B, since the first transistor T1 is turned off by the low voltage of the n-1th stage output signal Vg_outn-1, the Q node is floated to a high voltage state and the pull-up transistor T6 is turned off. Remains turned on. At this time, due to the high voltage of the first clock signal CLKV, the Q node is bootstrapping due to the parasitic capacitance formed by the overlap of the gate electrode and the drain electrode of the pull-up transistor T6, and is higher than the period A. Charged to voltage. Accordingly, the pull-up transistor T6 is reliably turned on so that the high voltage of the first clock signal CLKV is quickly supplied to the n-th gate line GLn as the output signal Vg_outn. Meanwhile, the QB node discharged through the 5a transistor T5a turned on by the Q node maintains a low voltage state.

In the C period, the third a transistor T3a is turned on by the high voltage of the dummy stage output signal Vg_outn + 1 and is turned on by the fourth transistor T4 turned on by the high potential driving voltage VDD. The above driving voltage VDD is supplied to turn the QB node into a high voltage state and turn on the third and pull-down transistors T3 and T7. The Q node is quickly discharged by the turned-on third and third a transistors, and a low voltage is supplied to the n-th gate line GLn as the output signal Vg_outn by the turned-on pull-down transistor T7.

In the D period, the QB node floated to the high voltage state in the C period maintains the floating state to turn on the third and pull-down transistors T3 and T7. As a result, the Q node is discharged to maintain the low voltage state, and the low voltage is supplied to the n-th gate line GLn as the output signal Vg_outn. The output signal Vg_outn maintains the low voltage state of the D period until the n-th stage output signal Vg_outn-1 is supplied in the next frame.

Referring to FIG. 4B, the dummy stage 32 turns on the first transistor T1 by the high voltage of the nth stage output signal Vg_outn in the A ′ period, and the high voltage is pre-charged to the Q node. . The pull-up transistor T6 is turned on by the high voltage pre-charged to the Q node to output the low voltage of the second clock signal CLKVB. At this time, the QB node is in a low voltage state by the fifth transistor T5 turned on according to the high voltage of the Q node, and the third and pull-down transistors T3 and T7 are turned off.

In the B ′ period, the first node T1 is turned off by the low voltage of the nth stage output signal Vg_outn, so that the Q node is floated to a high voltage state, and the pull-up transistor T6 is turned on. Keep it. At this time, due to the high voltage of the second clock signal CLKVB, the Q node is bootstrapping due to the parasitic capacitance formed by the overlap of the gate electrode and the drain electrode of the pull-up transistor T6, and thus, is longer than the A 'period. Charged to high voltage Accordingly, the pull-up transistor T6 is reliably turned on to output the high voltage of the second clock signal CLKVB. Meanwhile, the QB node discharged through the 5a transistor T5a turned on by the Q node maintains a low voltage state.

In the C ′ period, the third a transistor T3a is turned on by the high voltage of the nth stage QB node, and the high potential driving voltage is turned on through the fourth transistor T4 turned on by the high potential driving voltage VDD. (VDD) is supplied to bring the QB node into a high voltage state and turn on the third and pull-down transistors T3 and T7. The Q node is quickly discharged by the turned-on third and third a transistors, and a low voltage is output by the turned-down pull-down transistor T7.

In the D 'period, the QB node floated to the high voltage state in the C' period maintains the floating state to turn on the third and pull-down transistors T3 and T7. As a result, the Q node is discharged to maintain the low voltage state and the low voltage is output.

As described above, the liquid crystal display device according to the present invention does not use the start pulse Vst to reset the dummy stage but uses the previous stage of the dummy stage, that is, the QB node of the last stage, in the same manner as in FIG. 3. Space and thus parasitic capacity can be reduced.

5 is a view schematically showing another example of a shift register according to the present invention.

Referring to FIG. 5, the dummy stage 42 outputs the pull-up transistor T6 outputting the clock signal CLKVB under the control of the Q node and the low potential driving voltage VSS under the control of the QB node. An output buffer composed of a pull-down transistor T7, and a control unit composed of first to fifth transistors T1 to T5 for controlling the Q node and the QB node. The dummy stage 42 is supplied with the high potential driving voltage and the low potential driving voltages VDD and VSS and the output signal Vg_outn of the last stage, and the clock signal CLKVB having a phase as shown in FIG. 4B is supplied. do. Hereinafter, an operation process of the dummy stage 42 will be described in detail with reference to the driving waveform shown in FIG. 4B.

Referring to FIG. 4B, the dummy stage 42 turns on the first transistor T1 by the high voltage of the n-th stage output signal Vg_outn in the A ′ period so that the high voltage is pre-charged to the Q node. . The pull-up transistor T6 is turned on by the high voltage pre-charged to the Q node to output the low voltage of the clock signal CLKVB. At this time, the QB node is in a low voltage state by the fifth transistor T5 turned on according to the high voltage of the Q node, and the third and pull-down transistors T3 and T7 are turned off.

In the B ′ period, the first node T1 is turned off by the low voltage of the nth stage output signal Vg_outn, so that the Q node is floated to a high voltage state, and the pull-up transistor T6 is turned on. Keep it. At this time, due to the high voltage of the clock signal CLKVB, the Q node is bootstrapping due to the parasitic capacitance formed by the overlapping of the gate electrode and the drain electrode of the pull-up transistor T6, so that the voltage is higher than the A 'period. Is charged. As a result, the pull-up transistor T6 is reliably turned on to output the high voltage of the clock signal CLKVB. Meanwhile, the QB node discharged through the 5a transistor T5a turned on by the Q node maintains a low voltage state.

In the C 'period, the third transistor T3a is turned on by the output signal of the dummy stage which is in the high voltage state in the B' period, and the fourth transistor T4 is turned on by the high potential driving voltage VDD. The high potential driving voltage VDD is supplied to the QB node to turn into a high voltage state and turn on the third and pull-down transistors T3 and T7. The Q node is quickly discharged by the turned-on third and third a transistors, and a low voltage is output by the turned-down pull-down transistor T7.

In the D 'period, the QB node floated to the high voltage state in the C' period maintains the floating state to turn on the third and pull-down transistors T3 and T7. As a result, the Q node is discharged to maintain the low voltage state and the low voltage is output.

As described above, the liquid crystal display according to the present invention uses the output signal of the dummy stage itself in the same manner as in FIG. 5 without using the start pulse Vst to reset the dummy stage and thus the parasitic capacitance. Can be reduced.

6, 7A, and 7B are diagrams illustrating shift register output and Q node characteristics when the dummy stage is reset in the same manner as in FIGS. 3 and 5.

Referring to FIG. 6, it can be seen that the output 62 of the dummy stage shows low peak characteristics for a considerably short time when compared to the output 61 of the last stage. Since the dummy stage only needs to perform the reset function of the last stage without output to the gate line, this characteristic is not a big problem in the initial stage of driving as shown in FIG. 7A.

Referring to FIG. 7A, it can be seen that the driving waveform 71 of the last stage Q node, the output waveform 72 of the last stage, and the output waveform 73 of the dummy stage all appear normally.

However, the third transistor T3 and the pull-down transistor T7 of FIGS. 3 and 5 are turned on continuously except for the 2H period because the QB node is in the low voltage state only during the 2H period during one frame period. It maintains its state, which is most severely degraded by bias stress. Accordingly, when the third and pull-down transistors T3 and T7 do not function properly, only the third a transistor T3a can discharge the Q node.

FIG. 7B is a diagram illustrating a case where a threshold voltage is 10 V or more in a simulation performed to identify the above phenomenon.

Referring to FIG. 7B, it can be seen that the driving waveform 74 of the last stage Q node is not properly discharged, and thus, multiple outputs are generated so that the multi outputs have also occurred in the output waveform 75 of the last stage and the output waveform 76 of the dummy stage. Can be.

In order to solve this problem, the shift register according to the present invention may reset the output signal of the dummy stage to the QB node of the dummy stage itself.

8 is a view showing a first embodiment of a dummy stage according to the present invention.

Referring to FIG. 8, the dummy stage includes a pull-up transistor T6 outputting the first clock signal CLK1 under the control of the Q node, and a pull-up output low voltage driving voltage VSS under the control of the QB node. An output buffer composed of a -down transistor T7, and a controller composed of first to fifth a transistors T1 to T5a for controlling the Q node and the QB node. The dummy stage is supplied with the high potential driving voltage and the low potential driving voltage VDD and VSS and the output signal Vg_outn of the last stage, and the first and second clock signals having different phases as shown in FIG. CLK1, CLK2) are supplied. Hereinafter, an operation process of the dummy stage will be described in detail with reference to the driving waveform shown in FIG. 9.

Referring to FIG. 9, the first transistor T1 is turned on by the high voltage of the last stage output signal Vg_outn in the T1 period so that the high voltage is pre-charged to the Q node. The pull-up transistor T6 is turned on by the high voltage pre-charged to the Q node, and the low voltage of the first clock signal CLK1 is output. At this time, the QB node is in a low voltage state by the fifth transistor T5 turned on according to the high voltage of the last stage output signal Vg_outn and the fifth a transistor T5a turned on according to the high voltage of the Q node. The third and pull-down transistors T3 and T7 are turned off.

In the T2 period, since the first transistor T1 is turned off by the low voltage of the last stage output signal Vg_outn, the Q node is floated to a high voltage state, and the pull-up transistor T6 remains turned on. do. At this time, due to the high voltage of the first clock signal CLK1, the Q node is bootstrapping due to the parasitic capacitance formed by the overlap of the gate electrode and the drain electrode of the pull-up transistor T6, and is higher than the T1 period. Charged to voltage. Accordingly, the pull-up transistor T6 is surely turned on so that the high voltage of the first clock signal CLK1 is output. At this time, the output output signal Vg_outn + 1 is supplied to the nth stage, that is, the last stage, to reset the last stage. Meanwhile, the QB node discharged through the 5a transistor T5a turned on by the Q node maintains a low voltage state.

In the T3 period, the high potential driving voltage VDD is supplied through the fourth transistor T4 turned on by the high voltage of the second clock signal CLK2 so that the QB node is in a high voltage state, and the third and pull-down are performed. The transistors T3 and T7 are turned on. The third a transistor T3a is turned on by the QB node in the high voltage state, and the Q node is quickly discharged by the turned on third and third a transistors. Referring to FIG. 10, there is actually a time difference such as G between clock signals. In other words, there is a slight time difference before the supply of the first clock signal ends and the supply of the second clock signal. Accordingly, the first clock inverted to a low voltage before the end of the T2 period by turning on the pull-up transistor T6 by the Q node maintaining the high voltage state until the second clock signal is supplied in the T3 period. The signal is supplied to the output terminal. After the start of the T3 period, a low voltage is output through the pull-down transistor T7 turned on as described above.

In the T4 period, the QB node floating in the high voltage state in the T3 period maintains the high voltage state to turn on the third, third a, and pull-down transistors T3, T3a, and T7. As a result, the Q node is discharged to maintain the low voltage state and the low voltage is output. In the next frame, the output signal Vg_outn + 1 maintains the low voltage state of the T4 period until the output signal Vg_outn of the nth stage is supplied.

11A and 11B are diagrams each illustrating the initial driving time and the threshold voltage of the simulation result of FIG. 8 when 10 V or more.

Referring to FIG. 11A, the initial stage Q node output 101 and the last stage output 102 are all normal at the beginning of driving, and the waveform of the dummy stage output 103 is also the output 102 of the last stage as compared with FIG. 7A. You can see that it is normal.

Referring to FIG. 11B, unlike FIG. 7B, it can be seen that the waveforms of the last stage Q node output 103, the last stage output 104, and the dummy stage output 105 are all the same as the initial driving.

As in the dummy stage of the liquid crystal display according to the present invention, deterioration may occur quickly because a transistor serving as a reset is subjected to a bias stress, as in the conventional dummy stage. However, since the dummy stage according to the present invention uses the QB node of the dummy stage itself, the deterioration phenomenon can be alleviated by increasing the size of only the transistor that performs the reset function in the dummy stage. Since there is a space occupied by the non-display area under the display area in the LCD, the size of the dummy stage reset transistor is not a big problem.

12 is a view showing a second embodiment of a dummy stage according to the present invention.

Referring to FIG. 12, in the second embodiment of the dummy stage according to the present invention, the pull-down transistor T7 of the output buffer is deleted in the dummy stage of FIG. 8, and the first to fifth a and the pull-up transistors T1 to The configurations of T5a and T6 are the same and have a drive waveform as shown in FIG.

13 is a view showing a third embodiment of a dummy stage according to the present invention.

Referring to FIG. 13, the dummy stage frames the pull-up transistor T6 that outputs the first clock signal CLK1 under the control of the Q node, and the low potential driving voltage VSS under the control of the QB_O and QB_E nodes. An output buffer composed of odd frame pull-down and even frame pull-down transistors T7_O and T7_E alternately output each time, and first to fifth i_O transistors T1 to T5i_O controlling Q nodes and QB_O and QB_E nodes. A control unit is provided. The dummy stage is supplied with the high potential driving voltage and the low potential driving voltages VDD and VSS and the output signal Vg_outn of the last stage, and the first clock signal CLK1 having a phase as shown in FIGS. 14A and 14B. Is supplied. Hereinafter, an operation process of the dummy stage will be described in detail with reference to the driving waveforms shown in FIGS. 14A and 14B.

FIG. 14A is a drive waveform showing the odd frame period of FIG. 13.

Referring to FIG. 14A, in the A_O period, the first transistor T1 is turned on by the high voltage of the last stage output signal Vg_outn so that the high voltage of the high potential driving voltage VDD is pre-charged to the Q node. . The pull-up transistor T6 is turned on by the high voltage pre-charged to the Q node, and the low voltage of the first clock signal CLK1 is output. At this time, the fifth_O, fifth_E, fourthb_O, and fourthb_E transistors T5_O, T5_E, T4b_O, and T4b_E are turned on according to the high voltage of the last stage output signal Vg_outn, and the fourth c_O according to the high voltage of the Q node. The fourth c_E, fifth a_O, and fifth a_E transistors T4c_O, T4c_E, T5a_O, and T5a_E are turned on.

Meanwhile, the fourth a_O transistor T4a_O is turned on by the odd frame high potential driving voltage VDD_O, and the fourth_O transistor T4_O is caused by the low voltages supplied through the fourth and fourth c_O transistors T4b_O and T4c_O. Is turned off. In this case, the turned-off fourth_O transistor T4_O blocks the high voltage of the odd frame high potential driving voltage VDD_O from being supplied to the QB_O node. In addition, as described above, the turned on fifth and fifth transistors T5_O and T5a_O supply a low voltage to the QB_O node, and the turned on fifth_E and fifth a_E transistors T5_E and T5a_E provide a low voltage to the QB_E node. To supply. That is, the QB_O and QB_E nodes are discharged to maintain a low voltage state, thereby turning off the third_O, third_E, odd frame pull-down and even frame pull-down transistors T3_O, T3_E, T7_O, and T7_E to turn off the third_O, The discharge path of the Q node through the third_E, thirda_O, and thirda_E transistors T3_O, T3_E, T3a_O, and T3a_E is blocked.

In the B_O period, since the first transistor T1 is turned off by the low voltage of the last stage output signal Vg_outn, the Q node is floated to a high voltage state, and the pull-up transistor T6 remains turned on. do. At this time, due to the high voltage of the first clock signal CLK1, the Q node is bootstrapping due to the parasitic capacitance formed by the overlap of the gate electrode and the drain electrode of the pull-up transistor T6, and is higher than the A_O period. Charged to voltage. Accordingly, the pull-up transistor T6 is reliably turned on so that the high voltage of the first clock signal CLK1 is outputted quickly. Meanwhile, the QB_O and QB_E nodes discharged through the 5a_O and 5a_E transistors T5a_O and T5a_E turned on by the Q node maintain the low voltage state. In addition, although the fourth a_O transistor T4a_O is turned on by the odd frame high potential driving voltage VDD_O, a low voltage is applied to the fourth_O transistor T4_O through the fourth b_O transistor T4b_O turned on by the Q node. Supplied. That is, the fourth_O transistor T4_O is turned off to block the supply of the odd frame high potential driving voltage VDD_O to the QB_O node.

In the C_O period, the high voltage of the odd frame high potential driving voltage VDD_O is supplied to the QB_O node through the fourth_O transistor T4_O to turn the third_O, 5i_E and the odd frame pull-down transistors T3_O, T5i_E, and T7_O. -Turn on. In addition, the third a_O transistor T3a_O is turned on by the QB_O node in the high voltage state to discharge the Q node together with the third_O transistor T3_O, and the fifth i_E transistor T5i_E discharges the QB_E node. The 5a_O and 5a_E transistors T5a_O and T5a_E are turned off by the Q node to block the discharge paths of the QB_O and QB_E nodes, and the odd frame pull-down transistor T7_O outputs a low voltage. In the C_O period, as described with reference to FIG. 10, the first clock signal is inverted to a low voltage before the pull-up transistor is turned off by the Q node, so that the low voltage is actually output before the start of the C_O period. .

In the D_O period, the fourth_O and fourth-a_O transistors are turned on through the high voltage of the odd frame high potential driving voltage VDD_O, so that the QB_O node also maintains the high voltage state. The third_O, thirda_O, fifthi_E, and odd frame pull-down transistors T3_O, T3a_O, T5i_E, and T7_O are turned on by the QB_O node. The third_O and thirda_O transistors T3_O and T3a_O and the fifth i_E transistor T5i_E discharge Q nodes and QB_E nodes, respectively, to maintain a low voltage state, and the odd frame pull-down transistor T7_O maintains the remaining odd frame period. Output a low voltage.

FIG. 14B is a drive waveform illustrating the even frame period of FIG. 13.

Referring to FIG. 14B, in the A_E period, the first transistor T1 is turned on by the high voltage of the last stage output signal Vg_outn so that the high voltage of the high potential driving voltage VDD is pre-charged to the Q node. . The pull-up transistor T6 is turned on by the high voltage pre-charged to the Q node, and the low voltage of the first clock signal CLK1 is output. At this time, the fifth_O, fifth_E, fourthb_O, and fourthb_E transistors T5_O, T5_E, T4b_O, and T4b_E are turned on according to the high voltage of the last stage output signal Vg_outn, and the fourth c_O according to the high voltage of the Q node. The fourth c_E, fifth a_O, and fifth a_E transistors T4c_O, T4c_E, T5a_O, and T5a_E are turned on.

Meanwhile, the fourth a_E transistor T4a_E is turned on by the even frame high potential driving voltage VDD_E and the fourth_E transistor T4_E due to the low voltages supplied through the fourth b_E and fourth c_E transistors T4b_E and T4c_E. Is turned off. In this case, the turned-off fourth_E transistor T4_E blocks the high voltage of the even frame high potential driving voltage VDD_E from being supplied to the QB_E node. In addition, as described above, the turned on fifth and fifth transistors T5_O and T5a_O supply a low voltage to the QB_O node, and the turned on fifth_E and fifth a_E transistors T5_E and T5a_E provide a low voltage to the QB_E node. To supply. That is, the QB_O and QB_E nodes are discharged to maintain a low voltage state, thereby turning off the third_O, third_E, odd frame pull-down and even frame pull-down transistors T3_O, T3_E, T7_O, and T7_E to turn off the third_O, The discharge path of the Q node through the third_E, thirda_O, and thirda_E transistors T3_O, T3_E, T3a_O, and T3a_E is blocked.

In the B_E period, since the first transistor T1 is turned off by the low voltage of the last stage output signal Vg_outn, the Q node is floated to a high voltage state, and the pull-up transistor T6 remains turned on. do. At this time, due to the high voltage of the first clock signal CLK1, the Q node is bootstrapping due to the parasitic capacitance formed by the overlap of the gate electrode and the drain electrode of the pull-up transistor T6, and is higher than the A_E period. Charged to voltage. Accordingly, the pull-up transistor T6 is reliably turned on so that the high voltage of the first clock signal CLK1 is outputted quickly. Meanwhile, the QB_O and QB_E nodes discharged through the 5a_O and 5a_E transistors T5a_O and T5a_E turned on by the Q node maintain a low voltage state. In addition, while the fourth a_E transistor T4a_E is turned on by the even frame high potential driving voltage VDD_E, a low voltage is transmitted to the fourth_E transistor T4_E through the fourth b_E transistor T4b_E turned on by the Q node. Supplied. That is, the fourth_E transistor T4_E is turned off to block the even frame high potential driving voltage VDD_E from being supplied to the QB_E node.

In the C_E period, the high voltage of the even frame high potential driving voltage VDD_E is supplied to the QB_E node through the fourth_E transistor T4_E to turn the third_E, fifthi_O and even frame pull-down transistors T3_E, T5i_O, and T7_E. -Turn on. In addition, the 3a_E transistor T3a_E is turned on by the QB_E node in the high voltage state to discharge the Q node together with the third_E transistor T3_E, and the 5i_O transistor T5i_O discharges the QB_O node. The 5a_O and 5a_E transistors T5a_O and T5a_E are turned off by the Q node to block the discharge paths of the QB_O and QB_E nodes, and the even frame pull-down transistor T7_E outputs a low voltage. In the C_E period, as described with reference to FIG. 10, the first clock signal is inverted to a low voltage before the pull-up transistor is turned off by the Q node, so that the low voltage is actually output before the start of the C_E period. .

In the D_E period, the fourth_E and fourtha_E transistors are turned on through the high voltage of the even frame high potential driving voltage VDD_E, so that the QB_E node also maintains the high voltage state. The third_E, thirda_E, fifthi_O, and even frame pull-down transistors T3_E, T3a_E, T5i_O, and T7_E are turned on by the QB_E node. The third_E and thirda_E transistors T3_E and T3a_E and the fifth i_O transistor T5i_O discharge the Q node and the QB_O node, respectively, to maintain a low voltage state, and the even frame pull-down transistor T7_E maintains the remaining even frame period. Output a low voltage.

15 is a view showing a fourth embodiment of a dummy stage according to the present invention.

Referring to FIG. 15, in the fourth embodiment of the dummy stage according to the present invention, the odd frame pull-down and even frame pull-down transistors T7_O and T7_E of the output buffer are deleted in the dummy stage of FIG. The fifth i_O and the pull-up transistors T1 to T5i_O and T6 have the same configuration and have the driving waveforms as shown in FIGS. 14A and 14B.

16 is a view showing a fifth embodiment of a dummy stage according to the present invention.

Referring to FIG. 16, in the fifth embodiment of the dummy stage according to the present invention, the gate terminal of the 5i_E transistor T5i_E is connected to the odd frame high potential driving voltage VDD_O instead of the QB_O node in the dummy stage of FIG. 13. The QB_E node is discharged during the odd frame period. In addition, the gate terminal of the fifth i_O transistor T5i_O is connected to the even frame high potential driving voltage VDD_E instead of the QB_E node to discharge the QB_O node during the even frame period. Meanwhile, configurations of the first to fifth a_O, pull-up, odd frame pull-down, and even frame pull-down transistors T1 to T5a_O, T6, T7_O, and T7_E are the same as those of FIG. 13, and FIGS. 14A and 14B It has the same drive waveform.

17 is a view illustrating a sixth embodiment of a dummy stage according to the present invention.

Referring to FIG. 17, according to the sixth embodiment of the dummy stage according to the present invention, the odd frame pull-down and even frame pull-down transistors T7_O and T7_E of the output buffer are deleted in the dummy stage of FIG. The fifth i_O and the pull-up transistors T1 to T5i_O and T6 have the same configuration and have the driving waveforms as shown in FIGS. 14A and 14B.

18 is a view illustrating a seventh embodiment of a dummy stage according to the present invention.

Referring to FIG. 18, a seventh embodiment of a dummy stage according to the present invention includes the fourth a_O, fourth b_O, fourth c_O, fourth a_E, fourth b_E, and fourth c_E transistors T4a_O, T4b_O, T4c_O, and T4a_E in the dummy stage of FIG. 13. , T4b_E, T4c_E) are deleted, and the configurations of the remaining first to fifth i_O, pull-up, odd frame pull-down and even frame pull-down transistors T1 to T5i_O, T6, T7_O, and T7_E are the same, and FIG. 14A And a driving waveform as shown in FIG. 14B.

19 is a view showing an eighth embodiment of a dummy stage according to the present invention.

Referring to FIG. 19, in the eighth embodiment of the dummy stage according to the present invention, the odd frame pull-down and even frame pull-down transistors T7_O and T7_E of the output buffer are deleted in the dummy stage of FIG. The fifth i_O and the pull-up transistors T1 to T5i_O and T6 have the same configuration and have the driving waveforms as shown in FIGS. 14A and 14B.

20 is a view illustrating a ninth embodiment of a dummy stage according to the present invention.

Referring to FIG. 20, a ninth embodiment of a dummy stage according to the present invention includes the fourth a_O, fourth b_O, fourth c_O, fourth a_E, fourth b_E, and fourth c_E transistors T4a_O, T4b_O, T4c_O, and T4a_E in the dummy stage of FIG. 16. , T4b_E, T4c_E) are deleted, and the configurations of the remaining first to fifth i_O, pull-up, odd frame pull-down and even frame pull-down transistors T1 to T5i_O, T6, T7_O, and T7_E are the same, and FIG. 14A And a driving waveform as shown in FIG. 14B.

21 is a view illustrating a tenth embodiment of a dummy stage according to the present invention.

Referring to FIG. 21, in the tenth embodiment of the dummy stage according to the present invention, the odd frame pull-down and even frame pull-down transistors T7_O and T7_E of the output buffer are deleted in the dummy stage of FIG. The fifth i_O and the pull-up transistors T1 to T5i_O and T6 have the same configuration and have the driving waveforms as shown in FIGS. 14A and 14B.

22 is a view illustrating an eleventh embodiment of a dummy stage according to the present invention.

Referring to FIG. 22, the dummy stage includes a pull-up transistor T6 outputting the first clock signal CLK1 under the control of the Q node, and a pull-up output low voltage driving voltage VSS under the control of the QB node. An output buffer composed of a -down transistor T7, and a controller composed of first to fifth i transistors T1 to T5i for controlling the Q node and the QB node. The dummy stage is supplied with the high potential driving voltage and the low potential driving voltages VDD and VSS and the last stage output signal Vg_outn, and the first, second and fourth clocks having different phases as shown in FIG. The signals CLK1, CLK2 and CLK4 are supplied. Hereinafter, an operation process of the dummy stage will be described in detail with reference to the driving waveform shown in FIG. 23.

Referring to FIG. 23, the first transistor T1 is turned on by the high voltage of the last stage output signal Vg_outn in the S1 period so that the high voltage is pre-charged to the Q node. The pull-up transistor T6 is turned on by the high voltage pre-charged to the Q node, and the low voltage of the first clock signal CLK1 is output. At this time, the QB node is in a low voltage state by the fifth transistor T5 turned on according to the high voltage of the last stage output signal Vg_outn and the fifth a transistor T5a turned on according to the high voltage of the Q node. The third and pull-down transistors T3 and T7 are turned off. On the other hand, although the fourth transistor T4a is turned on by the fourth clock signal CLK4, the low potential driving voltage VSS is turned off from the fourth c transistor T4c turned on by the last stage output signal Vg_outn. The low voltage is supplied and the fourth transistor T4 is turned off to cut off the charging path of the QB node.

In the S2 period, since the first transistor T1 is turned off by the low voltage of the last stage output signal Vg_outn, the Q node is floated to a high voltage state, and the pull-up transistor T6 remains turned on. do. At this time, due to the high voltage of the first clock signal CLK1, the Q node is bootstrapping due to the parasitic capacitance formed by the overlap of the gate electrode and the drain electrode of the pull-up transistor T6, and is higher than the S1 period. Charged to voltage. Accordingly, the pull-up transistor T6 is reliably turned on so that the high voltage of the first clock signal CLK1 is outputted quickly. Meanwhile, the QB node discharged through the 5a transistor T5a turned on by the Q node maintains a low voltage state.

In the period S3, the low-voltage driving voltage is applied to the QB node through the 5i transistor T5i, in which the fourth and fifth i transistors T4b and T5i are turned on and turned on by the high voltage of the second clock signal CLK2. The low voltage of VSS) is supplied to maintain the low voltage state. At this time, the fourth transistor T4 is reliably blocked from being supplied with the high voltage to the QB node while the fourth transistor T4 is turned off through the turned-on fourth b transistor T4b. Meanwhile, the Q node in which the discharge paths are all blocked is continuously floated in the high voltage state to output the low voltage of the first clock signal CLK1. The fifth a transistor T5a turned on by the Q node discharges the QB node.

In the S4 period, all the transistors are turned off so that the Q node keeps floating to the high voltage state of the S3 period, and the first clock signal CLK1 is turned low through the pull-up transistor T6 turned on by the Q node. The voltage is output.

In the S5 period, as the fourth clock signal CLK4 is inverted to a high voltage, the high voltage is supplied to the QB node as the fourth and fourth transistors T4a and T4 are turned on, and the third and third voltages are supplied by the QB node. 3a and pull-down transistors T3, T3a, and T7 are turned on. At this time, the low potential driving voltage VSS is supplied to the Q node through the third and third a transistors T3 and T3a so that the Q node is in a low voltage state, and the low potential driving voltage is applied through the pull-down transistor T7. A low voltage of (VSS) is output.

In the S6 period, the fourth clock signal CLK4 is inverted to a low voltage again, but the discharge paths of the QB node are all kept in a blocked state, so that the QB node continues to float to the high voltage state. The third, third, and pull-down transistors T3, T3a, and T7 are turned on by the high voltage of the QB node, and the Q node and the output signal Vg_outn + 1 are low as described above in the period S5. Keep it.

In the S7 period, the second clock signal CLK2 is inverted to a high voltage to turn on the fourth and fifth i transistors T4b and T5i. The fourth transistor T4 is turned off by the fourth transistor T4b to block the high voltage from being supplied to the QB node. The fifth i transistor T5i supplies the low potential driving voltage VSS to the QB node so that the QB node maintains a low voltage state. On the other hand, the Q node is floated to the low voltage state of the S6 period. As both the Q node and the QB node maintain a low voltage state, both the pull-up and pull-down transistors are turned off and the output signal Vg_outn + 1 also floats to the low voltage state.

In the S8 period, all the transistors are turned off to keep the Q node, the QB node, and the output signal Vg_outn + 1 low. The dummy stage repeatedly maintains the state of the period T5 to the period T8 until the end of the frame after the period T8.

24 is a view illustrating a twelfth embodiment of a dummy stage according to the present invention.

Referring to FIG. 24, according to the twelfth embodiment of the dummy stage according to the present invention, in the dummy stage of FIG. 23, the pull-down transistor T7 is deleted, and the first to fifth i_O and the pull-up transistors T1 to T5i_O and T6. ) Have the same configuration, and have a driving waveform as shown in FIG.

As a result, the dummy stage of the shift register according to the present invention connects the gate terminal of the reset transistor to the QB node of the dummy stage itself, and is applied to all the shift registers regardless of the circuit configuration, so that unnecessary wiring space and corresponding parasitics are applied. While reducing the capacity, the dummy stage output can be reset and the dummy stage output can be stabilized.

As described above, the shift register according to the present invention and the liquid crystal display using the same in the shift register having a dummy stage for resetting the last stage, the reset signal for controlling the output of the dummy stage QB node of the dummy stage itself By supplying from the system, unnecessary wiring space and thus parasitic capacitance can be reduced. In addition, it is possible to stabilize the output signal of the dummy stage by preventing the deterioration by increasing the size of the transistor which plays a reset role in the dummy stage.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (21)

A plurality of stages for sequentially controlling the charging of the output terminal in response to the voltage of the first node and sequentially shifting the output signal by controlling the discharge of the output terminal in response to the voltage of the second node; The output of the dummy output terminal connected to the first node of the last stage generating the last output signal of the plurality of stages is controlled in response to the voltage of the third node and the third node in response to the voltage of the fourth node. And a dummy stage for resetting. According to claim 1, The dummy stage, A shift register characterized by receiving a last stage output signal, a high potential driving voltage, a low potential driving voltage, and a clock signal. The method of claim 2, The dummy stage, An output buffer for supplying an output signal to the output terminal; And a control unit for controlling the output buffer. The method of claim 3, wherein The output buffer, And a pull-up transistor controlled by the third node to supply one of a high voltage and a low voltage to the output terminal according to a clock signal. The method of claim 4, wherein The control unit, A first transistor receiving the last stage output signal and being turned on to supply a high voltage to a third node to turn on the pull-up transistor to supply a first clock signal to the output terminal; A fourth transistor configured to receive the high voltage of the second clock signal and to be turned on to supply a high potential driving voltage to the fourth node; Third and third a transistors configured to discharge the third node by being turned on through a high voltage of the second node; A fifth transistor configured to receive the output signal of the last stage to be turned on to discharge a fourth node; And a fifth a transistor configured to discharge the fourth node by being turned on through the high voltage of the first node. The method of claim 4, wherein The control unit, A first transistor receiving the output signal of the last stage and being turned on to supply a high voltage to a third node to turn on the pull-up transistor to supply a first clock signal to the output terminal; A fourth a transistor configured to charge the fifth node with a high potential driving voltage by being turned on by receiving a high voltage of the fourth clock signal; A fourth transistor configured to charge the fourth node to the high potential driving voltage by being turned on by receiving the high voltage of the fifth node; A fourth b transistor configured to discharge the fifth node by turning on the high voltage of the second clock signal; A fourth c transistor configured to discharge the fifth node by being turned on by receiving the output signal of the last stage; Third and third a transistors configured to discharge the third node by being turned on through a high voltage of the fourth node; A fifth a transistor configured to discharge the fourth node by being turned on by receiving a high voltage from the third node; A fifth transistor configured to receive the output signal of the last stage to be turned on to discharge a fourth node; And a fifth i transistor configured to discharge the fourth node by being turned on by receiving the high voltage of the second clock signal. The method according to any one of claims 5 and 6, The output buffer, And a pull-down transistor controlled by a fourth node to supply a low potential driving voltage to the output terminal. The method of claim 4, wherein The fourth node, A first QB node for discharging said third node during an odd frame period; And a second QB node for discharging said third node during an even frame period. The method of claim 8, The dummy stage, In the case of an odd frame, an odd frame high potential driving voltage is supplied, In the case of an even frame, a shift register characterized in that an even frame high potential driving voltage is supplied. The method of claim 9, The control unit, A first control unit for charging and discharging the third node; A second control unit for charging and discharging the first QB node; And a third controller for charging and discharging the second QB node. The method of claim 10, The first control unit, And a first transistor receiving the output signal of the last stage and being turned on to supply a high voltage to a third node to turn on the pull-up transistor to supply a first clock signal to the output terminal. Shift register. The method of claim 11, wherein The second control unit, A fourth O transistor which charges the first QB node with the odd frame high potential driving voltage by being turned on by receiving the odd frame high potential driving voltage; A third_O and third a_O transistor configured to discharge the third node by being turned on by receiving the high voltage of the first QB node; A fifth_O transistor configured to discharge the first QB node by turning on the high voltage of the last stage output signal; A fifth a_O transistor configured to discharge the first QB node by being turned on by receiving the high voltage of the third node; And a fifth i_O transistor configured to discharge the first QB node by being turned on by receiving the high voltage of the second QB node. The method of claim 12, The third control unit, A fourth_E transistor configured to receive the even frame high potential driving voltage and to be turned on to charge the second QB node to the even frame high potential driving voltage; Third_E and thirda_E transistors configured to discharge the third node by being turned on by being supplied with the high voltage of the second QB node; A fifth_E transistor configured to receive the high voltage of the last stage output signal and to be turned on to discharge the second QB node; A 5a_E transistor configured to discharge the second QB node by being turned on by receiving the high voltage of the third node; And a fifth i_E transistor configured to receive the high voltage of the first QB node to turn on to discharge the second QB node. The method of claim 11, wherein The second control unit, A fourth O transistor which charges the first QB node with the odd frame high potential driving voltage by being turned on by receiving the odd frame high potential driving voltage; A third_O and third a_O transistor configured to discharge the third node by being turned on by receiving the high voltage of the first QB node; A fifth_O transistor configured to discharge the first QB node by being turned on by receiving a high voltage of the last stage output signal; A fifth a_O transistor configured to discharge the first QB node by being turned on by receiving the high voltage of the third node; And a fifth i_O transistor configured to discharge the first QB node by being supplied with an even frame high potential driving voltage and being turned on. The method of claim 14, The third control unit, A fourth_E transistor configured to receive the even frame high potential driving voltage and to be turned on to charge the second QB node to the even frame high potential driving voltage; Third_E and thirda_E transistors configured to discharge the third node by being turned on by being supplied with the high voltage of the second QB node; A fifth_E transistor configured to receive the high voltage of the last stage output signal and to be turned on to discharge the second QB node; A 5a_E transistor configured to discharge the second QB node by being turned on by receiving the high voltage of the third node; And a fifth i_E transistor configured to discharge the second QB node by being turned on by receiving an odd frame high potential driving voltage. The method of claim 11, wherein The second control unit, A fourth a_O transistor configured to receive an odd frame high potential driving voltage and to be turned on to supply the odd frame high potential driving voltage to a fifth node; A fourth_O transistor configured to receive a high voltage from the fifth node and turn on to charge the first QB node to an odd frame high potential driving voltage; A fourth b_O transistor configured to discharge the fifth node by turning on the high voltage of the last stage output signal; A fourth c_O transistor configured to discharge the fifth node by being turned on by receiving the high voltage of the third node; A third_O and third a_O transistor configured to discharge the third node by being turned on by receiving the high voltage of the first QB node; A fifth_O transistor configured to discharge the first QB node by being turned on by receiving the high voltage of the last stage output signal; A fifth a_O transistor configured to discharge the first QB node by being turned on by receiving the high voltage of the third node; And a fifth i_O transistor configured to discharge the first QB node by being turned on by receiving the high voltage of the second QB node. The method of claim 16, The third control unit, A fourth a_E transistor configured to receive the even frame high potential driving voltage and to be turned on to supply the even frame high potential driving voltage to the sixth node; A fourth_E transistor configured to receive a high voltage from the sixth node and turn on to charge the second QB node to an odd frame high potential driving voltage; A fourth b_E transistor configured to discharge the sixth node by being turned on by receiving the high voltage of the last stage output signal; A fourth c_E transistor configured to discharge the sixth node by turning on the high voltage of the third node; Third_E and thirda_E transistors configured to discharge the third node by being turned on by receiving the high voltage of the second QB node; A fifth_E transistor configured to discharge the second QB node by being turned on by receiving the high voltage of the last stage output signal; A 5a_E transistor configured to discharge the second QB node by being turned on by receiving the high voltage of the third node; And a fifth i_E transistor configured to discharge the second QB node by being turned on by receiving the high voltage of the first QB node. The method of claim 11, wherein The second control unit, A fourth a_O transistor configured to receive an odd frame high potential driving voltage and to be turned on to supply the odd frame high potential driving voltage to a fifth node; A fourth_O transistor configured to receive a high voltage from the fifth node and turn on to charge the first QB node to an odd frame high potential driving voltage; A fourth b_O transistor configured to discharge the fifth node by turning on the high voltage of the last stage output signal; A fourth c_O transistor configured to discharge the fifth node by being turned on by receiving the high voltage of the third node; A third_O and third a_O transistor configured to discharge the third node by being turned on by receiving the high voltage of the first QB node; A fifth_O transistor configured to discharge the first QB node by being turned on by receiving the high voltage of the last stage output signal; A fifth a_O transistor configured to discharge the first QB node by being turned on by receiving the high voltage of the third node; And a fifth i_O transistor configured to discharge the first QB node by being turned on by receiving an even frame high potential driving voltage. The method of claim 18, The third control unit, A fourth a_E transistor configured to receive the even frame high potential driving voltage and to be turned on to supply the even frame high potential driving voltage to the sixth node; A fourth_E transistor configured to receive a high voltage from the sixth node and turn on to charge the second QB node to an odd frame high potential driving voltage; A fourth b_E transistor configured to discharge the sixth node by being turned on by receiving the high voltage of the last stage output signal; A fourth c_E transistor configured to discharge the sixth node by turning on the high voltage of the third node; Third_E and thirda_E transistors configured to discharge the third node by being turned on by receiving the high voltage of the second QB node; A fifth_E transistor configured to discharge the second QB node by being turned on by receiving the high voltage of the last stage output signal; A 5a_E transistor configured to discharge the second QB node by being turned on by receiving the high voltage of the third node; And a fifth i_E transistor configured to discharge the second QB node by being turned on by receiving an odd frame high potential driving voltage. The method according to any one of claims 13, 15, 17 and 19, The output buffer, A first pull-down transistor controlled by a first QB node to supply a low potential driving voltage to the output terminal; And a second pull-down transistor controlled by a second QB node to supply a low potential driving voltage to the output terminal. A liquid crystal display panel in which a plurality of gate lines and a plurality of data lines intersect and a plurality of liquid crystal cells are disposed; A plurality of stages for sequentially shifting the output signal by controlling the charging of the output terminal in response to the voltage of the first node and controlling the discharge of the output terminal in response to the voltage of the second node, the last output of the plurality of stages The charging of the dummy output terminal connected to the first node of the last stage of generating a signal is controlled in response to the voltage of the third node and the discharge of the dummy output terminal is controlled in response to the voltage of the fourth node. A gate driver sequentially supplying gate pulses to the gate lines, including a dummy stage for resetting the third node in response to a voltage of a node; And a data driving circuit for supplying data voltages to the data lines.

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