KR20070001754A - Method for manufacturing semiconductor device having step gate - Google Patents

Abstract

A method for manufacturing a semiconductor device having a step gate is provided to increase refresh time and to improve punch through characteristic by optimizing a junction profile between a bit line contact region and a storage node contact. A step mask pattern is formed on a semiconductor substrate(400). The semiconductor substrate is etched by using the step mask pattern as a mask to form a step-type profile including a lower surface, a vertical surface, and an upper surface. A gate stack(428) is formed to be overlapped with the step-type profile. A first mask layer pattern is formed on the gate stack to expose a bit line contact node unit(432). First ion implantation is performed on the bit line contact node unit by using the first mask layer pattern as a mask. The first mask layer pattern is removed. Second ion implantation is performed on the semiconductor substrate. A second mask layer pattern(444) is formed on the gate stack to block the bit line contact node unit. Third ion implantation is performed on the rest region except for the bit line contact node unit by using the second mask layer pattern as a mask.

Description

Method for manufacturing semiconductor device having step gate

1A to 1F are diagrams illustrating a method of manufacturing a semiconductor device having a step gate according to the prior art.

2 and 3 are views for explaining a problem occurring when forming a step gate according to the prior art.

4A through 4G are views illustrating a method of manufacturing a semiconductor device having a step gate according to the present invention.

<Explanation of symbols for the main parts of the drawings>

400: semiconductor substrate 428: gate stack

432: bit line contact node portion 434: first mask layer pattern

436: storage node portion 444: second mask layer pattern

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a step gate.

In semiconductor integrated circuits, the density of devices must be increased in order to increase the density of devices per unit area in accordance with an increase in memory capacity. The density of such devices can be achieved by reducing the size of individual devices and narrowing the spacing between devices. However, this method leads to a reduction in design rules, which causes various problems.

In particular, when the size of a horizontal channel semiconductor device having a general structure is reduced, the length of the channel is shortened. If the channel length of the device is shortened, a short channel effect occurs. Accordingly, it is increasingly difficult to secure an effective channel length region in a conventional horizontal channel semiconductor device. Therefore, in order to overcome such structural limitations, a study has been proposed to increase the degree of integration of a device by forming a channel region of a conventional horizontal channel semiconductor device in a stepwise manner to replace the semiconductor device having an effective channel length.

1A to 1F are diagrams illustrating a method of manufacturing a semiconductor device having a step gate according to the prior art.

2 and 3 are views for explaining a problem occurring when forming a step gate according to the prior art.

First, referring to FIG. 1A, a photosensitive film is coated on a semiconductor substrate 100 divided into an active region and a device isolation region by a device isolation layer 102, and a photolithography process is performed to define a formation region of a stepped profile. The step mask pattern 104 is formed. Subsequently, the semiconductor substrate 100 is etched using the step mask pattern 104 as a mask to form a stepped profile including a lower surface A, a vertical surface B, and an upper surface C, and the step mask pattern 104. ) Remove.

Next, referring to FIG. 1B, the gate insulating layer 108, the conductive layer 110, the metal layer 112, and the hard mask nitride layer 114 are sequentially formed on the entire surface of the semiconductor substrate 100 including the stepped profile. do. Subsequently, a photoresist film is coated on the hard mask nitride film 114 and a photoresist pattern 116 is formed through a photolithography process to define a region where the step gate is to be formed.

Next, referring to FIG. 1C, an etching process using the photoresist pattern 116 as a mask is performed to form a hard mask layer pattern 124, a metal layer pattern 122, a conductive layer pattern 120, and a gate insulating layer pattern 118. Form a gate stack 126 having a stepped profile comprising a. The spacer layer 128 is disposed on the side of the gate stack 126.

Next, referring to FIG. 1D, a mask layer pattern 134 having an opening through which the storage node 130 is covered and the bit line contact node 132 is exposed is formed on the semiconductor substrate 100. Next, the mask film pattern 134 and the gate stack 126 partially exposed are subjected to a cell-halo ion implantation process with the ion implantation mask film. Cell-halo ion implantation is a method of injecting impurity ions of the opposite conductivity type such as boron (B) after covering the storage node portion 130 of the semiconductor substrate 100 and exposing only the bit line contact node portion 132. As a result, it is well known to improve the refresh characteristics of DRAM devices and to improve various operating characteristics of other devices.

1E and 1F, after removing the mask film pattern 134, the ion implantation process for forming the junction is performed in two steps using the hard mask film pattern 124 as a mask. To this end, as shown in FIG. 1E, first ion implantation is performed to form a primary asymmetric junction region 136 between the storage node 130 and the bit line contact node 132. Next, as illustrated in FIG. 1F, a second ion implantation is performed to form a secondary asymmetric junction region 138 between the storage node 130 and the bit line contact node 132. In this case, n-type impurity ions are used as impurity ions to be implanted, and phosphorus (P) ions may be used as a representative one. At this time, the bit line contact node unit 132 and the storage node are implanted with n-type impurity ions in the state where the boron (B) ion is implanted through the cell-halo ion implantation process. An asymmetric junction profile 138 is formed in the portion 130.

Meanwhile, referring to FIG. 2, in the gate stack 126 having the stepped profile formed as described above, the ion implantation process for forming the junction is performed in two stages while impurity ions are injected into the bit line contact node unit 132. As the n-type impurity and the p-type impurity form a boundary between the bit line contact node unit 132 and the junction island 200 is formed, the junction depth with the storage node unit 130 is similarly formed. Punch-through characteristics between / drain are degraded. Accordingly, in order to eliminate the phenomenon in which the junction island 200 occurs, a method of changing the ion implantation process from the conventional two stages to the first stage and performing ion implantation with high energy has been proposed. In this case, referring to FIG. 3, when the ion implantation process is changed from the conventional two stages to the first stage and the ion implantation proceeds with high energy, the ion island 200 is removed, but the ion implantation is performed in the conventional two stages. As the ion implantation proceeds at a higher energy than the progression, the electric field increases, causing a problem of deterioration of the refresh characteristics of the DRAM.

SUMMARY OF THE INVENTION The present invention provides a method of manufacturing a semiconductor device having a step gate that improves the refresh time by improving the cell-halo ion implantation process to optimize the junction profile of the bit line contact region and the storage node contact region. have.

In order to achieve the above technical problem, a method of manufacturing a semiconductor device having a step gate according to the present invention, forming a step mask pattern on the semiconductor substrate, by etching the semiconductor substrate using the step mask pattern as a mask Forming a stepped profile comprising a face, a vertical face, and a top face; forming a gate stack overlapping the stepped profile; Forming a first mask layer pattern exposing a bit line contact node portion on the gate stack; Performing first ion implantation into the bit line contact node with the first mask layer pattern as a mask, and removing the first mask layer pattern; Performing a second ion implantation on the semiconductor substrate; Forming a second mask layer pattern on the gate stack to block the bit line contact node; And performing a third ion implantation into the remaining region except for the bit line contact node portion using the second mask layer pattern as a mask.

In the present invention, in the step of performing the first ion implantation into the bit line contact node, one of n-type or p-type impurities may be used.

The second ion implantation is preferably implanted with n-type impurities.

In the step of performing the third ion implantation in the remaining region except for the bit line contact node, it is preferable to implant an n-type impurity.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification.

4A through 4G are views illustrating a method of manufacturing a semiconductor device having a step gate according to an embodiment of the present invention.

First, referring to FIG. 4A, a photosensitive film is coated on a semiconductor substrate 400 divided into an active region and a device isolation region by the device isolation layer 402, and a photolithography process is performed to define a stepped profile formation region. A step mask pattern 404 is formed.

Next, referring to FIG. 4B, when the semiconductor substrate 400 is etched using the step mask pattern 404 as an etch mask, a stepped profile including a lower surface A, a vertical surface B, and an upper surface C may be formed. The vertical surface B is then formed into a vertical channel region through a channel ion implantation process.

Referring next to FIG. 4C, the gate insulating film 408, the conductive film 410, the metal film 412, and the hard mask film 414 are sequentially formed on the entire surface of the semiconductor substrate 400 including the stepped profile. do. The gate insulating film 408 may be formed of an oxide film using a thermal process, and the conductive film 410 may be formed of a polysilicon film by applying polysilicon or the like. In addition, the metal film 412 may be formed of a tungsten silicide (WSix) film, and the hard mask film 414 may be formed of a nitride film. Subsequently, a photoresist film is coated on the hard mask layer 414 and a photoresist pattern 416 defining a region where a step gate is to be formed is formed through a photolithography process.

Next, referring to FIG. 4D, an etching process using the photoresist pattern 416 as a mask is performed to form the gate stack 428. The gate stack 428 may include a hard mask film pattern 424, a metal film pattern 422, a conductive film pattern 420, and a gate insulating film pattern 418. Meanwhile, when the gate stack 428 is formed, the conductive film on the sidewall portion is exposed. Accordingly, in the subsequent wet process, the gate stack 428 may be damaged by the etching solution, and the adhesion may be weak between the insulating film for the gate spacer and the conductive film pattern 420 to be formed later. May occur. Accordingly, a step of oxidizing the upper portion of the gate insulating layer pattern 418 and the sidewall of the conductive layer pattern 420 may be prevented by further forming a sidewall oxide layer 426, for example, a gate poly oxide layer. Subsequently, a nitride film is formed as a spacer insulating film on the entire surface of the gate stack 428, and then a spacer nitride film 430 is disposed on the sidewall of the gate stack 428 through a predetermined process. The photoresist pattern 416 is then removed using a conventional strip method.

Next, referring to FIG. 4E, after the photoresist is coated on the semiconductor substrate 400 including the gate stack 428, a photolithography process may be performed to form the first mask layer pattern 434. The first mask layer pattern 434 has an opening that exposes the bit line contact node portion 432 in the active region of the semiconductor substrate 400. On the other hand, the storage node 436 is covered by the first mask layer pattern 436 in the active region of the semiconductor substrate 400.

Subsequently, as indicated by arrows in the drawing, impurity ions are applied to the bit line contact node portion 432 of the semiconductor substrate 400 by performing a first ion implantation process using the first mask layer pattern 436 as an ion implantation mask layer. Inject. As the implanted impurity ion, one of n-type or p-type impurities is used, and representative examples thereof may include boron (B) or phosphorus (P) ions. The impurity region 438 is formed in the bit line contact node portion 432 of the semiconductor substrate 400 by the first ion implantation. In this case, the first ion implantation covers the storage node portion 436 of the semiconductor substrate 400, exposes only the bit line contact node portion 432, and injects impurity ions of the opposite conductivity type, such as boron (B). It is effective in improving the refresh characteristics of the device and improving various operating characteristics of the other devices. After the first ion implantation is performed, the first mask layer pattern 434 is removed. Meanwhile, before performing the first ion implantation, a photoresist residue removal process may be performed first.

Referring next to FIG. 4F, a second ion implantation is applied to an opening that exposes the storage node portion 436 and the bit line contact node portion 432 of the active region of the semiconductor substrate 400 including the gate stack 428. To form junction profiles 440 and 442. Here, n-type impurity ions are used as impurity ions to be implanted, and phosphorus (P) ions may be used as a representative one. Here, when the p-type impurity is implanted during the first ion implantation, the junction profile 440 of the bit line contact node unit 432 has an interface between the n-type and p-type regions while injecting the n-type impurity through the second ion implantation. A junction island (not shown) may be generated. Accordingly, ion implantation is performed to remove the junction island in a subsequent process.

Referring to FIG. 4G, after the photoresist is coated on the semiconductor substrate 400 including the gate stack 428, a photolithography process is performed to form a second mask layer pattern 444. The second mask layer pattern 440 has an opening that exposes the storage node portion 436 in the active region of the semiconductor substrate 400. On the other hand, the bit line contact node portion 432 is covered by the second mask layer pattern 444 in the active region of the semiconductor substrate 400. Accordingly, in the related art, ion implantation is repeatedly performed in the bit line contact node unit 432 to generate a junction island generated by changing a doping profile in which impurities are injected between the storage node unit 436 and the bit line contact node unit 432. 200, see FIG. 2), and the punch-through phenomenon caused by the junction island can also be improved. In addition, the ion implantation is carried out at a high concentration to remove the junction island, the leakage current is generated while the electric field is increased to prevent the effect of reducing the refresh time.

Subsequently, as indicated by arrows in the drawing, a junction ion implantation using the second mask layer pattern 444 as an ion implantation mask layer is performed to perform a third ion implantation process on the storage node portion 436 of the semiconductor substrate 400. Profiles 444 and 448 are formed. Here, n-type impurity ions are used as impurity ions to be implanted, and phosphorus (P) ions may be used as a representative one. After the third ion implantation is performed, the second mask layer pattern 444 is removed. Meanwhile, before performing the third ion implantation, a photoresist residue removing process may be performed first.

In the prior art, the semiconductor device having the step gate according to the present invention performs a cell-halo ion implantation process and a junction formation ion implantation process to form an asymmetric junction between the bit line contact node portion and the storage node portion, and thus, between the source and the drain. While the punch-through property is deteriorated, in the present invention, the ion implantation is performed using a mask layer pattern covering the bit line contact node to optimize the junction profile between the bit line contact node and the storage node to increase the refresh time. The punch through characteristics can be improved.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the invention.

For example, in the above-described embodiment, a semiconductor device having a step gate has been described, but it can also be used for a semiconductor device having a planar and a recess gate.

As described above, according to the method of manufacturing a semiconductor device having a step gate according to the present invention, the ion implantation process method can be improved to optimize the junction profile between the bit line contact region and the storage node contact to increase the refresh time. And punch-through characteristics can be improved.

Claims (4)

Forming a step mask pattern on the semiconductor substrate, Etching the semiconductor substrate using the step mask pattern as a mask to form a stepped profile including a lower surface, a vertical surface, and an upper surface; Forming a gate stack overlapping the stepped profile; Forming a first mask layer pattern exposing a bit line contact node portion on the gate stack; Performing first ion implantation into the bit line contact node with the first mask layer pattern as a mask, and removing the first mask layer pattern; Performing a second ion implantation on the semiconductor substrate; Forming a second mask layer pattern on the gate stack to block the bit line contact node; And And performing a third ion implantation into the remaining region except the bit line contact node portion using the second mask layer pattern as a mask. The method of claim 1, In the performing of the first ion implantation into the bit line contact node portion, a method of manufacturing a semiconductor device having a step gate, characterized in that for implanting using one of n-type or p-type impurities. The method of claim 1, The second ion implantation uses a n-type impurity, the manufacturing method of a semiconductor device having a step gate. The method of claim 1, In the step of performing the third ion implantation in the remaining regions other than the bit line contact node, n-type impurity is implanted.

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