KR20060134457A - Unit for driving liquid crystal display device and method for driving the same - Google Patents

Abstract

A method and an apparatus for driving a liquid crystal display(LCD) device are provided to prevent the LCD device from erroneously operating by lowering the operation speed by decreasing the frequency of a clock signal. An apparatus for driving a liquid crystal display device includes a storage(240) and a timing controller(210). The storage stores data having bits, whose number corresponds to the bandwidth of the storage. The timing controller rearranges input image data from the outside corresponding to the bandwidth of the memory and stores the rearranged result on the memory. The timing controller rearranges image data, which is read from the memory, to recover the initial bit number and processes the recovered image data. The timing controller includes a data arranging unit and a memory interface. The memory interface delivers the image data between the data arranging unit and the storage.

Description

Driving part of liquid crystal display device and driving method thereof {UNIT FOR DRIVING LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME}

1 is a view showing a driving unit of a liquid crystal display device to which two frame memories according to the prior art are applied.

2 is a view showing a driving unit of a liquid crystal display device to which one frame memory according to the related art is applied.

3 is a view showing a driving unit of a liquid crystal display according to the present invention.

4 is a view showing an example of rearrangement driving of a data arranging unit in the driving unit of the liquid crystal display according to the present invention;

*** Description of the symbols for the main parts of the invention ***

210: timing controller 212: memory interface

215: data array 240: memory

DATA100: First image data DATA 200: Second image data

ADR20: Address signal CTR20: Control signal

CLK20: Clock Signal

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving unit of a liquid crystal display device, and more particularly, to a driving unit of a liquid crystal display device and a method of driving the same, in which the size of image data is arranged and processed according to the data width of the memory.

Recently, flat panel displays such as liquid crystal display devices (LCDs), which are easy to manufacture by making them lighter and thinner than CRTs, have been developed in various fields. It is put to practical use.

A liquid crystal display device is a device for displaying a desired image by bonding two substrates together, injecting a liquid crystal having an anisotropic dielectric constant, and then controlling an amount of light transmitted through the substrate by applying an electric field to the liquid crystal.

Such liquid crystal display devices are currently being used not only for notebook computers and desktop computers but also for various measuring devices. Initially, still images have been implemented through liquid crystal displays, but as the multimedia environment expands, more and more moving images are implemented. However, the liquid crystal has a slow response time due to its inherent viscosity or elastic resilience, so there is a limitation in implementing the video. Accordingly, an overdriving method has been proposed as a method for improving the response speed of liquid crystals.

The overdriving method is to increase the response speed of the liquid crystal to obtain a desired light transmittance by applying a larger value to the liquid crystal than the magnitude of the electric field to be originally applied. In order to perform the overdriving method, two frame memories for storing image data of a previous frame and image data of a current frame are required. Likewise, in addition to the overdriving method, two frame memories are basically required for various recently proposed image processing methods.

As described above, a driving unit of a general liquid crystal display device to which two frame memories are applied will be described with reference to the accompanying drawings.

1 is a view illustrating a driving unit of a liquid crystal display device to which two frame memories according to the related art are applied.

Referring to FIG. 1, a driving unit of a liquid crystal display device includes first and second memories 20 and 30 storing image data in units of frames, and the first or second memories 20 and 30 through a memory interface 12. And a timing controller 10 for writing the image data or reading the image data written to the first or second memories 20 and 30.

The first memory 20 and the second memory 30 have a capacity of several megabytes (Mbytes) or more as a frame memory, and because they are large in volume, they cannot be integrated in the timing controller 10, but are separately provided to the outside. It is operated through the control unit 10 and the electrical wiring.

The memory controller 12 is provided in the timing controller 10. The memory interface 12 controls the clock signal CLK, the first and second address signals ADR1 and ADR2, and the first memory 20 and the second memory 30 under the control of the timing controller 10. First and second control signals CTR1 and CTR2 are output.

One of the first and second control signals CTR1 and CRT2 is a signal indicating a storage operation, and the other is a signal indicating a read operation. Since the first and second control signals CTR1 and CRL2 are applied to the first memory 20 and the second memory 30, only one of the first memory 20 and the second memory 30 is an image. Data DATA will be saved.

In order to perform the image processing in the timing controller 10, the first memory 20 and the second memory 30 must be stored in addition to storing new image data DATA and reading previously stored image data DATA. ) Must be used at the same time.

The timing controller 10 applies a first address signal ADR1 and a first control signal CTR1 to the first memory 20 through the memory interface 12, and to the second memory 30. The second address signal ADR2 and the second control signal CTR2 are applied. At this time, when the first control signal CTR1 instructs the storage of the image data DATA and the second control signal CTR2 instructs the reading of the image data DATA, the memory interface 12 Image data DATA is stored at an address of the first memory 20 indicated by the first address signal ADR1, and image data stored from an address of the second memory 30 indicated by the second address signal ADR2. Read (DATA). All of these operations are performed in synchronization with the clock signal CLK simultaneously applied to the first and second memories 20 and 30.

The image data DATA of the second memory 30 read through the memory interface 12 is image processed by the timing controller 10 and the image data of the current frame as the image data of the previous frame.

When new frame image data is input to the timing controller 10 again after one frame has elapsed, previous frame image data stored in the first memory 20 is read by the memory interface 12, and the first frame image data is read. The new frame image data is stored in the two memories 30. That is, the first control signal CTR1 and the second control signal CTR2 alternately indicate storage and reading, and thus the first memory 20 and the second memory 30 operate alternately.

As described above, two memories 20 and 30 are applied to the driving unit of the liquid crystal display. The first memory 20 and the second memory 30 are external memories having a capacity of several megabytes or more, and have a certain volume due to their large capacity, so it is difficult to integrate them into the timing controller 10. . Therefore, it is usually provided separately from the timing controller 10.

When the timing controller 10 is connected to two external memories to process an image, the volume of the liquid crystal display is inevitably larger than that of using one external memory. do. Therefore, as a configuration different from that of FIG. 1, the timing controller 110 to which only one external memory is applied has been proposed, which will be described below with reference to FIG. 2.

2 is a view showing a driving unit of a liquid crystal display device to which one frame memory according to the related art is applied.

Referring to FIG. 2, the driving unit of the liquid crystal display device stores or reads image data in the external memory 140 through a memory interface 112 and an external memory 140 for storing or outputting image data DATA10. The timing controller 110 is configured.

In the driving unit of the LCD shown in FIG. 2, only one external memory 140 is provided, but an internal memory 114 is provided in the timing controller 110.

The timing controller 110 reads out previous frame image data DATA10 stored in the external memory 140 through the memory interface 112 and stores the previous frame image data DATA10 in the internal memory 114.

As described above, since there is only one external memory 140, the timing controller 110 cannot simultaneously store and read the image data DATA10. Therefore, the previous frame image data DATA10 is temporarily stored in the internal memory 114, and then the new frame image data DATA10 is stored in the external memory 140. That is, the storage and reading process is sequentially performed with only one external memory 140 having the internal memory 114. Of course, the address signal ADR10, the control signal CTR10 and the clock signal CLK10 have the same function as in FIG.

The timing controller 110 to which one external memory 140 is applied as described above should have twice the operation speed as the timing controller to which two external memories are applied. That is, since storage and reading are sequentially performed using one external memory 140, one operation of storing / reading is performed at the same time as the driving unit of FIG. To do this, the storage speed and reading speed should be twice as fast. In order to increase the operation speed, the pulse of the clock signal CLK10 should be generated twice as fast and applied to the external memory 140. However, when the frequency is doubled, the electromagnetic wave generated from the timing controller 110 increases, resulting in an increase in electromagnetic interference (EMI).

As a result, when the driving unit is configured as shown in FIG. 2, the number of external memories can be reduced to one, but the function of the circuit increases due to the increased electromagnetic waves, which impairs the functions of other circuits, thereby deteriorating the circuit function. It may cause malfunction.

On the other hand, although not shown in the drawings, in the driving units of Figs. 1 and 2, there are a plurality of wirings connecting the external memory and the memory interface to transfer the image data. The number of wirings is connected corresponding to the data width of the external memory. This data width corresponds to the unit storage capacity that can be stored simultaneously at one time. For example, if the external memory is 32 bits x 2M, 32 bits is both a data width and a unit storage space, and there are 2M unit storage spaces. 32 image data transfer wirings between the external memory and the memory interface should be provided corresponding to the data width.

The data width of the external memory is made up of 8 bits, 16 bits and 32 bits. However, since 24-bit image data is mainly composed of 8-bit red (R) data, 8-bit green (G) data, and 8-bit blue (B) data, the image data has an external memory having a data width of 32 bits. Will be used.

Since the data width of the external memory and the bits of the image data do not coincide, the external memory is wasted without using 8 bits of storage space each time the image data is stored. Therefore, there is a problem that the use efficiency of the memory is lowered.

SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to match a bit of image data with a data width of a memory, thereby maximizing memory use efficiency, and a driving method of the liquid crystal display device. To provide.

The driving unit of the liquid crystal display device for achieving the object of the present invention as described above and the storage means for storing the data bit by bit corresponding to the data width; Timing control unit for rearranging the image data input from the outside so as to correspond to the data width of the storage means and storing the image data in the storage means or rearranging the image data read from the storage means to return to the initial number of bits and then image processing It is configured to include.

In addition, the driving method of the liquid crystal display according to the present invention comprises the steps of rearranging new image data transmitted from the outside equal to the data width of the storage means; Reading previous image data already stored in the storage means; Storing the rearranged new image data in the storage means; Returning the previous image data to the number of bits before rearranging the previous image data; And comparing the new image data with the previous image data to perform image processing.

The decrease in memory usage efficiency occurs because the data width of the memory and the bits of the image data do not coincide. Accordingly, if the bit of the image data is matched with the data width of the memory, the storage space in the memory can be utilized 100%, thereby maximizing the use efficiency of the memory. A driving unit and a driving method of the liquid crystal display device for improving the use efficiency of such a memory will be described with reference to the accompanying drawings.

3 is a view showing a driving unit of the liquid crystal display according to the present invention.

Referring to FIG. 3, the driving unit of the liquid crystal display device includes a memory 240 for storing data and a second bit having the same number of bits as the data width of the first image data DATA100 transmitted from the outside. The timing control unit 210 rearranges the image data DATA200 to store the data in the memory 240 or reads the second image data DATA200 stored in the memory 240 and rearranges the image data to the first image data DATA100. It is configured to include).

The timing controller 210 rearranges the number of bits of the first image data DATA100 input from the outside to correspond to the data width of the memory 240 or reads the second image data DATA200 from the memory 240. ) Is a data arranging unit 215 for rearranging the first image data DATA100 and a memory interface 212 transferring second image data DATA200 between the data arranging unit 215 and the memory 240. It is configured to include.

The data arranging unit 215 may rearrange the first image data DATA100 to the second image data DATA200 or rearrange the second image data DATA200 to the first image data DATA100. That is, bidirectional driving in which rearrangement is possible in any of the first image data DATA100 and the second image data DATA200 is performed.

The first image data DATA100 is generally 24 bits, and the memory 240 is a device having a data width of 32 bits and a unit storage space.

The memory 240 has a data width capable of simultaneously transmitting or receiving 32 bits of data, and simultaneously stores data equal to the data width at one time.

Synchronus Dynamic Random Access Memory (SDRAM) may be used for the memory 240.

Accordingly, the storage space of the memory 240 is rearranged by rearranging the first image data DATA100 to 32-bit second image data DATA200 corresponding to the 32-bit unit storage space of the memory 240. 100% available.

Meanwhile, the memory interface 212 provided in the timing controller 210 is controlled by the timing controller 210 to store the second image data DATA200 in the memory 240 or to store the second image data ( The operation of reading the DATA200 and transmitting it to the data arranging unit 215 is performed.

Meanwhile, the driving of the memory interface 212 will be described in more detail as follows.

The memory interface 212 outputs an address signal ADR20, a control signal CTR20, and a clock signal 20 to the memory 240. The control signal CTR20 is a signal for determining the operation state of the memory 240, and the storage state or the read state of the memory 240 is selectively determined according to the control signal CTR20. For example, when the high potential control signal CTR20 is applied, the memory 240 is in a storage state, and when the low potential control signal CTR20 is applied, the memory 240 is in a readable state. Can be set to

The control signal CTR20 makes the memory 240 a storage state or a readable state, and stores the second image data DATA200 in the memory 240 or reads the already stored second image data DATA200. In this case, it is necessary to designate a specific address to store or read the second image data DATA200 among the many storage spaces of the memory 240. The signal for performing such a function is the address signal ADR20.

Finally, the clock signal CLK20 is a signal having a periodic pulse. Even when the address signal ADR20 and the control signal CTR20 are applied to the memory 240, it is the clock signal CLK20 that determines the actual driving timing. The storage or read operation of the memory interface 212 is performed in synchronization with the pulse of the clock signal CLK20. That is, the clock signal CLK20 is an important signal for determining the operation speed of the timing controller 210.

The driving unit of the liquid crystal display shown in FIG. 3 has a structure having one memory 240 outside the timing controller 210. Of course, a structure in which two memories are applied is also possible.

As described above, when only one memory 240 for storing image data is provided outside the timing controller 210, the image data cannot be stored and read simultaneously. Therefore, the storing and reading are sequentially performed in accordance with the clock signal CLK20. I can only do it. Therefore, the data arranging unit 215 must also have a function of temporarily storing the first image data DATA100 or the second image data DATA200. That is, when the first image data DATA100 is input, the first image data DATA100 should be stored until the second image data DATA20 is read from the memory 240.

As described above, when only one memory 240 for storing the second image data DATA200 is provided, the frequency of the clock signal CLK20 is increased when two memories are included to simultaneously store and read image data. The speed should be increased by setting 2 times bigger.

However, when the first image data DATA100 is rearranged to the second image data DATA200 by the data arranging unit 215 and stored in the memory 240, the frequency of the clock signal CLK20 is maintained. It can be reduced to reduce the operating speed, will be described in detail with reference to FIG.

4 is a diagram illustrating an example of rearrangement driving of the data arranging unit in the driving unit of the liquid crystal display according to the present invention.

Referring to Fig. 4, image data R1 to B4 are input to the data arranging unit 215 in 24 bits and output in 32 bits.

The image data R1 to B4 is 24-bit data composed of 8-bit red image data R1 to R4, 8-bit green image data G1 to G4, and 8-bit blue image data B1 to B4. to be.

The image data R1 to B4 are continuously input in series from an external system such as a graphic card. That is, red image data R1 to R4, 8-bit green image data G1 to G4, and 8-bit blue image data B1 to B4 are sequentially input to the timing controller, and the image data R1 to B4. ) Is transferred to the data arranging unit 215.

As shown in Fig. 4, the data arranging unit 215 sequentially stores the image data R1 to B4 in 24-bit order from the image data R1 to B1 in the first column to the image data R4 to B4 in the fourth column. ) Is entered.

By the way, the data arranging unit 215 cuts the image data R1 to B4 which are continuously input by the data width of the preset memory. Since the data width of the memory is 32 bits, the new first column of image data (including red image data R2 of the image data R1 to B1 in the first column and the image data R2 to B2 in the second column) The output is classified into R1 to R2).

Then, the green and blue image data G2 and B2 among the image data R2 to B2 in the second row to be input, and the red and green image data R3 and G3 among the image data R3 to B3 in the third column to be input. And output as image data G2 to G3 of the second second column.

In this manner, the data arranging unit 215 rearranges and sequentially outputs 24-bit image data R1 to B4 in 32-bit units so as to be equal to the data width of the memory. Therefore, the 32-bit image data R1 to B4 stored in the memory at the same time can be stored at the same time so that the frequency of the clock signal in the timing controller using one external memory can be lowered from 2 times to 1.5 times. have.

As such, when the frequency of the clock signal is reduced, the operating speeds of the timing controller and the memory can be lowered, thereby reducing the electromagnetic interference (EMI). Therefore, malfunction of the driving circuit due to electromagnetic interference can be reduced.

The frequency of the clock signal can be reduced as the number of bits of the image data input from the outside is smaller than the data width of the memory, so that the image data must be rearranged in a larger width. Accordingly, the operation speed can be lowered, and the electromagnetic interference effect is smaller.

The data arranging unit 215 may rearrange and output the image data even when the number of bits of the image data is larger than the data width of the memory. For example, when 48 bits of image data are input and the data width of the memory is 32 bits, the 48 bits of image data can be rearranged and output by 32 bits to match the data width of the memory.

As described above, the driving unit and the driving method of the liquid crystal display according to the present invention rearrange the number of bits corresponding to the data width of the memory for storing image data input from the outside, so that the storage space of the memory can be maximized. Therefore, the memory usage efficiency can be maximized.

In addition, since the frequency of the clock signal can be reduced in the process of rearranging the image data in accordance with the data width of the memory, the operation speed can be reduced to prevent malfunction of the circuit due to electromagnetic interference.

Claims (20)

Storage means for storing data by bits corresponding to the data width; And Timing control unit for rearranging the image data input from the outside so as to correspond to the data width of the storage means and storing the image data in the storage means or rearranging the image data read from the storage means to return to the initial number of bits and then image processing The driving unit of the liquid crystal display device comprising a. The method of claim 1, wherein the timing controller A data arranging unit for rearranging the number of bits of the image data input from the outside to match the data width of the storage means or rearranging the image data read from the storage means to the number of bits initially inputted; And And a memory interface for transferring image data between the data arranging unit and the storage unit. The driving unit of claim 2, wherein the memory interface selectively performs a storage or reading operation according to a control signal applied to the memory. 3. The driving unit of claim 2, wherein the memory interface applies an address signal specifying an address of a memory to store or read image data to the memory. 3. The driving unit of claim 2, wherein the memory is stored or read in response to a clock signal applied from the memory interface. The driving unit of claim 5, wherein an operating speed of the memory interface and the memory is determined according to a frequency of a clock signal. 6. The driving unit of claim 5, wherein the frequency of the clock signal is smaller as the data width of the storage means is larger than the number of bits of image data input from the outside. 3. The driving unit of claim 2, wherein the data arranging unit further includes an image data storing function. 3. The driving unit of claim 2, wherein when the new image data is input, the data arranging unit reads old image data from the storage unit and stores the new image data in the storage unit. The driving unit of claim 1, wherein the storage unit is a synchronous dynamic random access memory (SDRAM). 2. The driving unit of claim 1, wherein the number of bits of the image data is smaller than the data width of the storage means. 2. The driving unit of claim 1, wherein the number of bits of the image data is larger than a data width of the storage means. 2. The driving unit of claim 1, wherein the number of bits of the image data is 24 bits, and the data width of the storage means is 32 bits. At least one storage means having a data width of a first bit; And A timing controller for rearranging the second bit image data into the first bit image data and storing the second bit image data in the storage means or reading the first bit image data stored in the storage means and rearranging the second bit image data to the second bit image data. The driving unit of the liquid crystal display device comprising a. 15. The driving unit of claim 14, wherein the timing controller further includes a data arranging unit for rearranging and outputting the image data to either one of first and second bits. 15. The liquid crystal display driver of claim 14, wherein the first bit is larger than the second bit. 15. The liquid crystal display driver of claim 14, wherein the first bit is less than the second bit. 15. The liquid crystal display driver of claim 14, wherein the first bit is 32 bits and the second bit is 24 bits. Rearranging new image data transmitted from the outside equal to the data width of the storage means; Reading previous image data already stored in the storage means; Storing the rearranged new image data in the storage means; Returning the previous image data to the number of bits before rearranging the previous image data; And And comparing the new image data with previous image data to perform image processing. 20. The driving method of claim 19, wherein the number of bits of the new image data transmitted from the outside and the previous image data returned from the outside are the same.

Images