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KR20060128489A - Method for manufacturing semiconductor device using recess gate process - Google Patents

Method for manufacturing semiconductor device using recess gate process Download PDF

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Publication number
KR20060128489A
KR20060128489A KR1020050049981A KR20050049981A KR20060128489A KR 20060128489 A KR20060128489 A KR 20060128489A KR 1020050049981 A KR1020050049981 A KR 1020050049981A KR 20050049981 A KR20050049981 A KR 20050049981A KR 20060128489 A KR20060128489 A KR 20060128489A
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hard mask
forming
film
semiconductor device
polysilicon
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KR1020050049981A
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Korean (ko)
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남기원
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주식회사 하이닉스반도체
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Publication of KR20060128489A publication Critical patent/KR20060128489A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method for manufacturing a semiconductor device using a recess gate process is provided to reduce a process procedure and to restrain particle sources by simultaneously etching a hard mask and an irregular ARC. A pad oxide layer(23) is formed on an upper portion of a semiconductor substrate(21). A hard mask and a nitride irregular ARC(25) are sequentially layered on the pad oxide layer to form a hard mask barrier layer(100). The pad oxide layer and a recess channel forming region of the semiconductor substrate are etched by using the hard mask barrier layer as an etching barrier to form a recess channel. A gate oxide layer is formed on a surface of the recess channel. A gate is formed on the gate oxide layer to be buried into a part of the recess channel.

Description

리세스게이트공정을 이용한 반도체소자의 제조 방법{METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING RECESS GATE PROCESS}Method of manufacturing semiconductor device using recess gate process {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING RECESS GATE PROCESS}

도 1a 및 도 1b는 종래기술에 따른 리세스게이트기술을 이용한 반도체소자의 제조 방법을 간략히 도시한 도면,1A and 1B schematically illustrate a method of manufacturing a semiconductor device using a recess gate technology according to the related art;

도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체소자의 제조 방법을 도시한 공정 단면도.2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 반도체 기판 22 : 소자분리막21 semiconductor substrate 22 device isolation film

23 : 패드산화막 24 : 하드마스크폴리실리콘23: pad oxide film 24: hard mask polysilicon

25 : 난반사방지막 26 : RG 마스크25: antireflection film 26: RG mask

27 : 리세스채널27: recess channel

100 : 하드마스크 배리어막100: hard mask barrier film

본 발명은 반도체 제조 기술에 관한 것으로,특히 리세스게이트 공정을 이용한 반도체소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a semiconductor device using a recess gate process.

최근에, 서브 100nm급 DRAM을 제조할 때 채널 길이가 짧아 소자의 리프레시 특성이 악화되는데, 이를 극복하기 위하여 활성영역을 수십nm 정도 리세스(Recess)시켜 리세스에 게이트의 일부를 매립시키는 리세스 게이트(Recess Gate; R-gate) 기술이 제안되었다.Recently, when fabricating a sub-100nm DRAM, the channel length is short, and the refresh characteristics of the device are deteriorated. To overcome this problem, a recess recessing the active region by several tens of nm fills a portion of the gate in the recess. Recess Gate (R-gate) technology has been proposed.

도 1a 및 도 1b는 종래기술에 따른 리세스게이트기술을 이용한 반도체소자의 제조 방법을 간략히 도시한 도면이다.1A and 1B schematically illustrate a method of manufacturing a semiconductor device using a recess gate technology according to the related art.

도 1a에 도시된 바와 같이, 반도체 기판(11)의 소정 영역에 STI(Shallow Trench Isolation) 공정을 이용하여 트렌치 구조의 소자분리막(12)을 형성한다. As shown in FIG. 1A, a device isolation film 12 having a trench structure is formed in a predetermined region of the semiconductor substrate 11 by using a shallow trench isolation (STI) process.

다음으로, 반도체 기판(11) 상부에 패드산화막(13)을 형성한다. 이때, 패드산화막(13)은 소자분리막(12) 공정시 사용한 패드산화막일 수 있다.Next, a pad oxide film 13 is formed over the semiconductor substrate 11. In this case, the pad oxide layer 13 may be a pad oxide layer used in the device isolation layer 12 process.

이어서, 패드산화막(13) 상에 하드마스크폴리실리콘(14)을 형성한 후, 하드마스크폴리실리콘(14) 상에 OBARC(Organic Bottom Anti Reflective Coating layer, 15)를 형성하고, OBARC(15) 상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 RG 마스크(16)를 형성한다.Subsequently, after forming the hard mask polysilicon 14 on the pad oxide film 13, an organic bottom anti reflective coating layer (OBARC) 15 is formed on the hard mask polysilicon 14, and on the OBARC 15 A photoresist film is applied to the film and patterned by exposure and development to form an RG mask 16.

도 1b에 도시된 바와 같이, RG 마스크(16)를 식각배리어로 OBARC(15), 하드마스크폴리실리콘(14)을 식각한 후, RG 마스크(16)를 스트립하고 세정공정을 진행한다. 이때, RG 마스크(16) 스트립시 OBRAC(15)도 동시에 제거된다.As shown in FIG. 1B, after etching the OBARC 15 and the hard mask polysilicon 14 using the RG mask 16 as an etching barrier, the RG mask 16 is stripped and a cleaning process is performed. At this time, the OBRAC 15 is also removed at the same time when the RG mask 16 is stripped.

이어서, 하드마스크폴리실리콘(14)을 식각배리어로 하여 패드산화막(13)과 반도체기판(11)을 소정 깊이로 실리콘리세스식각하여 리세스채널(17)을 형성한다. 이때, 하드마스크폴리실리콘(14)은 리세스채널(17) 형성을 위한 반도체기판(11)의 식각공정시 모두 소모되어 제거된다.Subsequently, the recess channel 17 is formed by etching the pad oxide layer 13 and the semiconductor substrate 11 to a predetermined depth using the hard mask polysilicon 14 as an etching barrier. At this time, the hard mask polysilicon 14 is consumed and removed during the etching process of the semiconductor substrate 11 to form the recess channel 17.

전술한 바와 같이 종래기술은 리세스채널 형성을 위해 OBARC 식각, 하드마스크폴리실리콘 식각, RG 마스크 스트립 및 세정 및 실리콘리세스식각의 다단계 공정(세번의 서로 다른 식각 챔버 사용)을 이용하고 있다.As described above, the prior art uses a multi-step process (using three different etch chambers) of OBARC etching, hardmask polysilicon etching, RG mask strip and cleaning and silicon recess etching to form the recess channel.

그러나, 종래기술은 다단계 공정에 의해 리세스채널을 형성하므로 웨이퍼 무빙(Wafer moving) 등에 따른 파티클 소스 및 생산성 저하를 초래한다.However, in the related art, the recess channel is formed by a multi-step process, resulting in particle source and productivity degradation due to wafer moving.

또한, 하드마스크폴리실리콘(14)은 실리콘리세스식각동안 충분히 하드마스크 역할을 수행하고 하부의 패드산화막(13)에 대한 과도한 어택이 발생하지 않도록 해야 하지만 실리콘리세스식각공정 조건에 대한 선택비 부족으로 하드마스크폴리실리콘의 손실이 과도하게 발생할 경우 활성영역 어택이 발생하는 문제가 있다.In addition, the hard mask polysilicon 14 should serve as a hard mask sufficiently during the silicon recess etching and prevent excessive attack on the pad oxide layer 13 below, but lacks the selectivity for the silicon recess etching process conditions. As a result, excessive loss of hard mask polysilicon may cause active area attack.

이를 방지하고자 하드마스크폴리실리콘의 두께를 증가시키는 경우에는 하드마스크폴리실리콘의 식각에 대한 포토 마진 부족으로 하드마스크폴리실리콘의 프로파일 변형을 초래한다.In order to prevent the increase of the thickness of the hard mask polysilicon, the lack of photo margin for etching of the hard mask polysilicon causes the profile deformation of the hard mask polysilicon.

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로, 파티클소스를 제거하고, 하드마스크폴리실리콘의 두께 부족을 개선하며, 실리콘리세스 식각후 발생되는 패드산화막의 손실을 방지할 수 있는 반도체소자의 제조 방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, removes the particle source, improves the lack of thickness of the hard mask polysilicon, and can prevent the loss of the pad oxide film generated after silicon recess etching Its purpose is to provide a method for manufacturing a semiconductor device.

상기 목적을 달성하기 위한 본 발명의 반도체소자의 제조 방법은 반도체 기판 상부에 패드산화막을 형성하는 단계, 상기 패드산화막 상에 하드마스크와 산소가 함유된 질화막계 난반사방지막의 순서로 적층된 하드마스크배리어막을 형성하는 단계, 상기 하드마스크배리어막을 식각배리어로 상기 패드산화막과 상기 반도체기판의 리세스채널예정지역을 식각하여 리세스채널을 형성하는 단계, 상기 리세스채널의 표면 상에 게이트산화막을 형성하는 단계, 및 상기 게이트산화막 상에 상기 리세스채널에 일부가 매립되는 형태의 게이트를 형성하는 단계를 포함하는 것을 특징으로 하며, 상기 하드마스크배리어막을 형성하는 단계는 상기 패드산화막 상에 상기 하드마스크로 폴리실리콘을 형성하는 단계, 상기 폴리실리콘 상에 상기 산소가 함유된 질화막계 난반사방지막을 형성하는 단계, 상기 산소가 함유된 질화막계 난반사방지막 상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 마스크를 형성하는 단계, 상기 마스크를 식각배리어로 상기 산소가 함유된 질화막계 난반사방지막과 폴리실리콘을 동일 챔버에서 식각하는 단계, 및 상기 마스크를 스트립하는 단계를 포함하는 것을 특징으로 하며, 상기 산소가 함유된 질화막계 난반사방지막은 SiON으로 형성하는 것을 특징으로 한다.The method of manufacturing a semiconductor device of the present invention for achieving the above object is a hard mask barrier formed by forming a pad oxide film on an upper surface of a semiconductor substrate, a hard mask and an anti-reflective coating film containing oxygen on the pad oxide film in order; Forming a layer, forming a recess channel by etching the pad oxide layer and a region of a recess channel of the semiconductor substrate using the hard mask barrier layer as an etch barrier, and forming a gate oxide layer on a surface of the recess channel And forming a gate in which a portion of the recess channel is buried on the gate oxide layer, and forming the hard mask barrier layer by using the hard mask on the pad oxide layer. Forming polysilicon, and nitriding the oxygen-containing nitride on the polysilicon Forming an anti-reflective coating based on the oxygen, applying a photoresist on the oxygen-containing antireflective coating containing oxygen, and patterning the photo-reflective coating with exposure and development to form a mask; And etching the polysilicon in the same chamber, and stripping the mask, wherein the oxygen-containing nitride antireflection film is formed of SiON.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 2a 내지 도 2e는 본 발명의 실시예에 따른 반도체소자의 제조 방법을 도시한 공정 단면도이다.2A through 2E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 2a에 도시된 바와 같이, 반도체 기판(21)의 소정 영역에 STI(Shallow Trench Isolation) 공정을 이용하여 트렌치 구조의 소자분리막(22)을 형성한다. As shown in FIG. 2A, a device isolation film 22 having a trench structure is formed in a predetermined region of the semiconductor substrate 21 by using a shallow trench isolation (STI) process.

다음으로, 반도체 기판(21) 상부에 패드산화막(23)을 형성한다. 이때, 패드산화막(23)은 소자분리막(22) 공정의 STI 공정시 사용한 패드산화막일 수 있다.Next, a pad oxide film 23 is formed over the semiconductor substrate 21. In this case, the pad oxide layer 23 may be a pad oxide layer used in the STI process of the device isolation layer 22.

이어서, 패드산화막(23) 상에 하드마스크폴리실리콘(24)을 형성한 후, 하드마스크폴리실리콘(24) 상에 포토마스크작업을 위한 난반사를 억제하며, 하드마스크폴리실리콘(24)의 식각 공정에서도 일정 비율의 식각율이 나오는 난반사방지막(25)을 증착한다. 예컨대, 질화막 계열의 난반사방지막(25)을 형성한다. 이러한 질화막 계열의 난반사방지막(25)은 OBARC와 동일하게 포토마스크작업시 난반사를 억제할 수 있다.Subsequently, after the hard mask polysilicon 24 is formed on the pad oxide film 23, the diffuse reflection for the photomask operation is suppressed on the hard mask polysilicon 24, and the etching process of the hard mask polysilicon 24 is performed. Evaporation of the anti-reflective film 25 that comes out of a certain ratio of the etch rate. For example, the diffuse reflection prevention film 25 of the nitride film series is formed. The nitride film-based diffuse reflection prevention layer 25 can suppress the diffuse reflection during the photomask work in the same manner as the OBARC.

상기 난반사방지막(25)은 Si3N4 계열의 순수 질화막이 아니라 산소가 일부 함유된 SiON 계열의 질화막을 사용하며, 난반사방지막(25)은 100Å∼900Å의 두께로 형성한다.The anti-reflection film 25 is not a pure nitride film of Si 3 N 4 series but using a SiON-based nitride film containing some oxygen, the anti-reflection film 25 is formed to a thickness of 100 ~ 900Å.

다음으로, 난반사방지막(25) 상에 감광막을 도포하고 노광 및 현상으로 패터 닝하여 RG 마스크(26)를 형성한다.Next, a photoresist film is coated on the diffuse reflection prevention film 25 and patterned by exposure and development to form an RG mask 26.

도 2b에 도시된 바와 같이, RG 마스크(26)를 식각배리어로 난반사방지막(25)과 하드마스크폴리실리콘(24)을 동일 챔버에서 식각한다. 이때, SiON 계열의 질화막으로 형성한 난반사방지막(25)은 불소 계열의 가스로 식각하고, 하드마스크폴리실리콘(24)은 염소계열의 가스를 이용하여 식각한다.As shown in FIG. 2B, the anti-reflection film 25 and the hard mask polysilicon 24 are etched in the same chamber using the RG mask 26 as an etching barrier. In this case, the diffuse reflection prevention film 25 formed of the SiON-based nitride film is etched with fluorine-based gas, and the hard mask polysilicon 24 is etched with chlorine-based gas.

위와 같이, 난반사방지막(25)으로 SiON 계열의 질화막을 형성하면, 동일 챔버에서 하드마스크폴리실리콘(24)까지 동시에 식각할 수 있어 파티클소스를 억제한다.As described above, when the SiON-based nitride film is formed of the diffuse reflection prevention film 25, the hard mask polysilicon 24 can be simultaneously etched in the same chamber to suppress the particle source.

도 2c에 도시된 바와 같이, RG 마스크(26)를 스트립하고 세정공정을 진행한다. 이때, RG 마스크(26)의 스트립후에도 난반사방지막(25)은 제거되지 않고 잔류한다.As shown in FIG. 2C, the RG mask 26 is stripped and a cleaning process is performed. At this time, even after the strip of the RG mask 26, the anti-reflective coating 25 is left without being removed.

이처럼, RG 마스크(26)의 스트립후에 잔류하는 난반사방지막(25)은 최초 두께를 유지하면서 하드마스크폴리실리콘(24)과 동일하게 후속 실리콘리세스식각공정시 하드마스크 역할을 수행한다.As such, the anti-reflective film 25 remaining after the strip of the RG mask 26 serves as a hard mask during the subsequent silicon recess etching process similarly to the hard mask polysilicon 24 while maintaining the initial thickness.

이하, RG 마스크 스트립후 잔류하는 하드마스크폴리실리콘(24)과 난반사방지막(25)의 적층을 '하드마스크배리어막(100)'이라고 약칭하기로 한다.Hereinafter, the stack of the hard mask polysilicon 24 and the diffuse reflection prevention film 25 remaining after the RG mask strip will be abbreviated as 'hard mask barrier film 100'.

도 2d에 도시된 바와 같이, 하드마스크배리어막(100)을 식각배리어로 하여 리세스채널예정지역을 실리콘리세스식각으로 식각하여 리세스채널(27)을 형성한다. 이때, 실리콘리세스식각공정은 HBr, Cl2 및 O2의 혼합가스를 사용하여 진행하는데, SiON 계열의 질화막으로 형성한 난반사방지막(25)과 하드마스크폴리실리콘(24)은 상기한 혼합가스에 대해 소정 비율의 식각율을 가져 실리콘리세스식각공정 완료후에 모두 소모된다.As shown in FIG. 2D, the recess channel 27 is etched by the silicon recess etching using the hard mask barrier layer 100 as an etching barrier to form the recess channel 27. At this time, the silicon recess etching process is performed using a mixed gas of HBr, Cl 2 and O 2, the anti-reflective film 25 and the hard mask polysilicon 24 formed of the SiON-based nitride film is the mixed gas It has a predetermined ratio of etch rate and is consumed after completion of the silicon recess etching process.

상기 실리콘리세스식각공정시 하드마스크폴리실리콘(24)과 난반사방지막(25)은 모두 소모되어 제거되지만, 난반사방지막(25)의 두께만큼 하부의 패드산화막(23)과 반도체기판(21)에 대한 공정마진이 증가하게 된다. 즉, 단순히 하드마스크폴리실리콘을 식각배리어로 하여 실리콘리세스식각을 진행하는 것에 비해 하드마스크폴리실리콘(24)과 난반사방지막(25)의 적층을 식각배리어로 실리콘리세스식각을 진행하는 경우가 공정마진이 증가한다.While the hard mask polysilicon 24 and the antireflection film 25 are all consumed and removed during the silicon recess etching process, the pad oxide film 23 and the semiconductor substrate 21 on the lower portion of the pad oxide film 23 are disposed as thick as the antireflection film 25. Process margins will increase. In other words, the silicon recess etching process is performed in which the hard mask polysilicon 24 and the antireflection film 25 are laminated using the etching barrier as compared to the silicon recess etching process using the hard mask polysilicon as the etching barrier. Margins increase

도 2e에 도시된 바와 같이, 패드산화막(23)을 제거한 후, 전면에 게이트임계전압(즉 문턱전압)을 조절하기 위한 이온주입공정시 반도체기판(21)을 보호하기 위해 스크린산화막을 형성한다. 이어서, 웰 및 채널 형성을 위한 이온주입 공정을 순차적으로 실시한 후 게이트산화막(28), 도핑된 폴리실리콘(29), 텅스텐실리사이드(30), 게이트하드마스크층(31)을 순차적으로 형성하여 게이트층을 구성한 후 게이트마스크 및 식각공정을 실시하여 리세스채널(27)에 일부가 매립되는 형태의 게이트를 형성한다.As shown in FIG. 2E, after the pad oxide film 23 is removed, a screen oxide film is formed on the front surface to protect the semiconductor substrate 21 during the ion implantation process for adjusting the gate threshold voltage (ie, threshold voltage). Subsequently, the ion implantation process for well and channel formation is sequentially performed, and then the gate oxide layer 28, the doped polysilicon 29, the tungsten silicide 30, and the gate hard mask layer 31 are sequentially formed. After forming the gate mask and the etching process is performed to form a gate of a portion of the recess channel 27 is embedded.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 하드마스크폴리실리콘과 난반사방지막을 한번에 동시에 식각하므로써 공정을 단순화시켜 파티클소스를 억제할 수 있는 효과가 있다.The present invention described above has the effect of reducing the particle source by simplifying the process by simultaneously etching the hard mask polysilicon and the diffuse reflection prevention film at once.

또한, 본 발명은 활성영역 어택에 대한 공정마진을 증가시켜 반도체소자의 신뢰성을 향상시킬 수 있는 효과가 있다.In addition, the present invention has the effect of improving the reliability of the semiconductor device by increasing the process margin for the active area attack.

Claims (6)

반도체 기판 상부에 패드산화막을 형성하는 단계;Forming a pad oxide film on the semiconductor substrate; 상기 패드산화막 상에 하드마스크와 산소가 함유된 질화막계 난반사방지막의 순서로 적층된 하드마스크배리어막을 형성하는 단계; Forming a hard mask barrier film stacked on the pad oxide film in the order of a hard mask and an oxygen-based antireflective film containing oxygen; 상기 하드마스크배리어막을 식각배리어로 상기 패드산화막과 상기 반도체기판의 리세스채널예정지역을 식각하여 리세스채널을 형성하는 단계;Forming a recess channel by etching the pad channel layer and a recess channel scheduled region of the semiconductor substrate using the hard mask barrier layer as an etch barrier; 상기 리세스채널의 표면 상에 게이트산화막을 형성하는 단계; 및Forming a gate oxide film on a surface of the recess channel; And 상기 게이트산화막 상에 상기 리세스채널에 일부가 매립되는 형태의 게이트를 형성하는 단계Forming a gate having a portion buried in the recess channel on the gate oxide layer 를 포함하는 반도체소자의 제조 방법.Method for manufacturing a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 하드마스크배리어막을 형성하는 단계는,Forming the hard mask barrier film, 상기 패드산화막 상에 상기 하드마스크로 폴리실리콘을 형성하는 단계;Forming polysilicon on the pad oxide layer using the hard mask; 상기 폴리실리콘 상에 상기 산소가 함유된 질화막계 난반사방지막을 형성하는 단계;Forming a nitride-based diffuse reflection prevention film containing the oxygen on the polysilicon; 상기 산소가 함유된 질화막계 난반사방지막 상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 마스크를 형성하는 단계;Forming a mask by applying a photoresist film on the nitride-based diffuse reflection prevention film containing oxygen and patterning the pattern by exposure and development; 상기 마스크를 식각배리어로 상기 산소가 함유된 질화막계 난반사방지막과 폴리실리콘을 동일 챔버에서 식각하는 단계; 및Etching the oxygen-containing nitride anti-reflective coating film and the polysilicon in the same chamber using the mask as an etching barrier; And 상기 마스크를 스트립하는 단계Stripping the mask 를 포함하는 것을 특징으로 하는 반도체소자의 제조 방법.Method of manufacturing a semiconductor device comprising a. 제2항에 있어서,The method of claim 2, 상기 산소가 함유된 질화막계 난반사방지막은, The nitride-based diffuse reflection prevention film containing oxygen, SiON으로 형성하는 것을 특징으로 하는 반도체소자의 제조 방법.A method of manufacturing a semiconductor device, characterized in that formed by SiON. 제3항에 있어서,The method of claim 3, 상기 산소가 함유된 질화막계 난반사방지막은, The nitride-based diffuse reflection prevention film containing oxygen, 100Å∼900Å의 두께로 형성하는 것을 특징으로 하는 반도체소자의 제조 방법.A method of manufacturing a semiconductor device, characterized in that it is formed in a thickness of 100 kV to 900 kV. 제2항에 있어서,The method of claim 2, 상기 산소가 함유된 질화막계 난반사방지막은 불소 계열의 가스로 식각하는 것을 특징으로 하는 반도체소자의 제조 방법.The oxygen-containing nitride antireflection film containing oxygen is etched with a fluorine-based gas manufacturing method of a semiconductor device. 제2항에 있어서,The method of claim 2, 상기 폴리실리콘은 염소계열의 가스를 이용하여 식각하는 것을 특징으로 하는 반도체소자의 제조 방법.The polysilicon is etched using a chlorine-based gas.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI704674B (en) * 2019-09-04 2020-09-11 華邦電子股份有限公司 Semiconductor device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI704674B (en) * 2019-09-04 2020-09-11 華邦電子股份有限公司 Semiconductor device and manufacturing method thereof

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