KR20060078675A - A liquid crystal display device and a method for fabricating the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display and a method of manufacturing the same, which can minimize the resistance of a transmission line and are advantageous in compacting. field; Pixel electrodes formed in the pixel areas; A plurality of transmission lines composed of at least two layers, each insulating layer being interposed between the layers, and each adjacent layer having a structure connected to each other through the insulating layer; And a driver transferring a signal to the gate line and the data line through the transmission line.

LCD, Transmission Line, Display, Non-Display, Resistance

Description

A liquid crystal display device and a method for manufacturing the same

1 is a block diagram of a conventional liquid crystal display device

2 is a configuration diagram of a liquid crystal display device according to a first embodiment of the present invention.

3 is a diagram illustrating a first configuration of the display unit and the non-display unit of FIG. 2.

4A to 4F are process cross-sectional views taken along lines I-I, II-II, III-III, and IV-IV of FIG.

FIG. 5 is a diagram illustrating a second configuration of the display unit and the non-display unit of FIG. 2.

6A to 6E are process cross-sectional views taken along lines I-I, II-II, III-III, and IV-IV of FIG.

FIG. 7 is a third configuration diagram illustrating the display part and the non-display part of FIG. 2.

8A to 8E are process cross-sectional views taken along lines I-I, II-II, III-III, and IV-IV of FIG.

9 is a configuration diagram of a liquid crystal display according to a second embodiment of the present invention.

10 is a diagram illustrating a first configuration of the display unit and the non-display unit of FIG. 9.

11A to 11F are process cross-sectional views taken along line I-I, II-II, III-III, and IV-IV of FIG.                 

FIG. 12 is a diagram illustrating a second configuration of the display unit and the non-display unit of FIG. 9.

13A to 13E are process cross-sectional views taken along lines I-I, II-II, III-III, and IV-IV of FIG.

* Explanation of symbols on the main parts of the drawings

200: substrate 200a: display unit

200b: non-display portion 201: gate transmission line

202: data transmission line 241, 242: output pin

250: gate driver 260: data driver

GL: Gate Line DL: Data Line

P: pixel area T: thin film transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a method for manufacturing the same, in which a transmission line is formed to have a vertical stacked structure composed of at least two layers, thereby minimizing resistance difference between the transmission lines. .

In recent years, research on flat panel display devices has been actively conducted. Among them, liquid crystal display devices (LCDs), field emission display devices (FEDs), electro-luminescence display devices (ELDs), and PDPs (PDPs) Plasma Display Pannels).                         

Among them, LCD is the most widely used as a substitute for CRT (Cathode Ray Tube) for the use of mobile image display device because of the excellent image quality, light weight, thinness, and low power consumption, and mobile type such as monitor of notebook computer. In addition, it is being developed in various ways such as a monitor of a television and a computer for receiving and displaying broadcast signals.

As described above, although various technical advances have been made in order for the liquid crystal display device to serve as a screen display device in various fields, the task of improving the image quality as the screen display device has many advantages and disadvantages.

Therefore, in order to use a liquid crystal display device in various parts as a general screen display device, the key to development is how much high definition images such as high definition, high brightness, and large area can be realized while maintaining the characteristics of light weight, thinness, and low power consumption. It can be said.

Such a liquid crystal display device may be broadly divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel, wherein the liquid crystal panel includes a first and second substrates having spaces, and It consists of a liquid crystal layer injected between a 1st board | substrate and a 2nd board | substrate.

Hereinafter, a liquid crystal display according to the related art will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a conventional liquid crystal display device.

As shown in FIG. 1, a conventional liquid crystal display device includes a plurality of gate lines GL arranged in one direction with a predetermined interval on the display portion 100a of the substrate 100, and the gate lines GL. A plurality of data lines DL arranged in one direction with a predetermined interval on the display unit 100a so as to vertically cross each other, and a plurality of data lines defined in a matrix form by the gate lines GL and each data line DL. Pixel electrodes (not shown) formed in each of the plurality of pixel regions P, thin film transistors T formed in the vicinity of each gate line GL and each data line DL, and the gate line A gate transmission line 101 extending from GL to the non-display unit 100b and connected to the output pin 131 of the gate driver 150, and extending from the data line DL to the non-display unit 100b. Connected to the output pin 132 of the driver 160 It includes a data transmission line 102.

The gate driver 150 and the data driver 160 are located at the lower edge of the non-display unit 100b. The gate transmission lines 101 connected to the output pins 131 of the gate driver 150 are connected to the gate lines GL in different directions. That is, when the display unit 100a is divided in half about an arbitrary gate line GL, the gate lines GL positioned at the upper end of the display unit 100a may have lower edges and left sides of the non-display unit 100b. It is connected to the gate transmission lines 101 (hereinafter, referred to as 'first gate transmission lines') passing along the edge. In addition, the gate lines GL positioned at the lower end of the display unit 100a are referred to as gate transfer lines 101 (hereinafter, referred to as 'second gate transfer lines') passing along lower and right edges of the non-display unit 100b. )

Therefore, the first gate transmission lines 101 are inevitably longer than the second gate transmission lines 101, and thus resistance between the first gate transmission line 101 and the second gate transmission line 101 is increased. There will be a difference. Of course, this can be prevented by increasing the line width of the first gate transmission line 101. However, due to the limited area of the non-display portion 100b, there are many restrictions in increasing the line width of the first gate transmission line 101.

Meanwhile, as described above, the gate driver 150 and the data driver 160 are identically configured at the lower edge of the non-display unit 100b and the data transmission line 102 instead of the gate transmission lines 101. May be connected to the data lines DL in different directions, in which some of the data transmission lines 102 may be longer than the remaining data transmission lines 102. There may be a difference in resistance between them.

The present invention has been made to solve the above problems, the transmission is composed of at least two layers, the insulating film is interposed between each layer, each layer adjacent to each other through the insulating film is a vertical laminated structure connected to each other transmission It is an object of the present invention to provide a liquid crystal display and a method of manufacturing the same by forming lines to minimize the difference in resistance between transmission lines.

According to an aspect of the present invention, a liquid crystal display device includes: a plurality of gate lines and data lines arranged to cross each other to define pixel areas of a liquid crystal panel; Pixel electrodes formed in the pixel areas; A plurality of transmission lines composed of at least two layers, each insulating layer being interposed between the layers, and each adjacent layer having a structure connected to each other through the insulating layer; And a driver transferring a signal to the gate line and the data line through the transmission line.

In addition, another liquid crystal display according to the present invention for achieving the above object comprises a plurality of gate lines and data lines arranged to cross each other to define the pixel areas of the liquid crystal panel; Pixel electrodes formed in the pixel areas; A plurality of transmission lines composed of at least two layers, the insulating layers being interposed between the layers, and the adjacent layers being connected to each other by a conductive material passing through the insulating layers; And a driver transferring a signal to the gate line and the data line through the transmission line.

In addition, the manufacturing method of the liquid crystal display device according to the present invention for achieving the above object comprises the steps of preparing a substrate having a display and a non-display; Forming a gate line in one direction on the display unit and forming a first layer of a gate transmission line on the non-display unit and extending from the gate line; Forming a gate insulating film on an entire surface of the substrate including the gate line and the first layer; Forming a first contact hole penetrating the gate insulating film to expose the first layer; Forming a semiconductor layer and an ohmic contact layer on the gate insulating film in order to overlap the gate electrode protruding from the gate line; Forming a source / drain electrode on the ohmic contact layer so as to overlap both edges of the semiconductor layer, and on the gate insulating film on the first layer to be connected to the first layer through the first contact hole; Forming a second layer of lines; Forming a protective layer on an entire surface of the substrate including the source / drain electrodes and the second layer; Forming a second contact hole penetrating the protective layer to expose the drain electrode; And forming a pixel electrode in a pixel area of the display unit to be connected to the drain electrode through the second contact hole.

In addition, another method of manufacturing a liquid crystal display device according to the present invention for achieving the above object comprises the steps of preparing a substrate having a display portion and a non-display portion; Forming a gate line in one direction on the display unit and forming a first layer of a gate transmission line on the non-display unit and extending from the gate line; Forming a gate insulating film on an entire surface of the substrate including the gate line and the first layer; Forming a semiconductor layer and an ohmic contact layer on the gate insulating film in order to overlap the gate electrode protruding from the gate line; Forming a source / drain electrode on the ohmic contact layer to overlap both edges of the semiconductor layer; Forming a protective layer on an entire surface of the substrate including the source / drain electrodes; Forming a first contact hole through the protective layer and the gate insulating layer to expose the drain electrode, and a second contact hole exposing the first layer; And forming a pixel electrode in a pixel area of the display unit to be connected to the drain electrode through the first contact hole, and to be connected to the first layer through the second contact hole. And forming a second layer of the gate transmission line on the layer.

In addition, another method of manufacturing a liquid crystal display device according to the present invention for achieving the above object comprises the steps of preparing a substrate having a display portion and a non-display portion; Forming a gate line in one direction on the display unit and forming a first layer of a transmission line extending from the gate line in the non-display unit; Forming a gate insulating film on an entire surface of the substrate including the gate line and the first layer; Forming a semiconductor layer and an ohmic contact layer on the gate insulating film in order to overlap the gate electrode protruding from the gate line; Forming a source / drain electrode on the ohmic contact layer to overlap both edges of the semiconductor layer, and forming a second layer of the transmission line on the gate insulating layer to overlap the first layer; Forming a protective layer on an entire surface of the substrate including the source / drain electrodes and the second layer; Forming a first contact hole through the protective layer and the gate insulating layer to expose the drain electrode, a second contact hole exposing the first layer, and a third contact hole exposing the second layer; And forming a pixel electrode in the pixel area of the display unit so as to be connected to the drain electrode through the first contact hole, and connecting the first layer and the second layer through the second and third contact holes. Characterized in that it comprises a step of forming a connecting layer.

In addition, another method of manufacturing a liquid crystal display device according to the present invention for achieving the above object comprises the steps of preparing a substrate having a display portion and a non-display portion; Forming a gate line in one direction on the display unit and forming a first layer of a data transmission line on the non-display unit; Forming a gate insulating film on an entire surface of the substrate including the gate line and the first layer; Forming a first contact hole penetrating the gate insulating film to expose the first layer; Forming a semiconductor layer and an ohmic contact layer on the gate insulating film in order to overlap the gate electrode protruding from the gate line; Forming a source / drain electrode on the ohmic contact layer to overlap both edges of the semiconductor layer, and transmitting data on the gate insulating film on the first layer to be connected to the first layer through the first contact hole; Forming a second layer of lines; Forming a protective layer on an entire surface of the substrate including the source / drain electrodes and the second layer; Forming a second contact hole penetrating the protective layer to expose the drain electrode; And forming a pixel electrode in a pixel area of the display unit to be connected to the drain electrode through the second contact hole.

Another liquid crystal display device manufacturing method according to the present invention for achieving the above object comprises the steps of preparing a substrate having a display portion and a non-display portion; Forming a gate line in one direction on the display unit and forming a first layer of a data transmission line on the non-display unit; Forming a gate insulating film on an entire surface of the substrate including the gate line and the first layer; Forming a semiconductor layer and an ohmic contact layer on the gate insulating film in order to overlap the gate electrode protruding from the gate line; Forming a source / drain electrode on the ohmic contact layer to overlap both edges of the semiconductor layer; Forming a protective layer on an entire surface of the substrate including the source / drain electrodes; Forming a first contact hole through the protective layer and the gate insulating layer to expose the drain electrode, and a second contact hole exposing the first layer; And forming a pixel electrode in a pixel area of the display unit to be connected to the drain electrode through the first contact hole, and to be connected to the first layer through the second contact hole. And forming a second layer of the data transmission line on the layer.

Hereinafter, a liquid crystal display according to a first embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a liquid crystal display according to a first embodiment of the present invention.

As shown in FIG. 2, the liquid crystal display according to the first exemplary embodiment of the present invention includes a plurality of gate lines GL arranged in one direction at predetermined intervals on the display unit 200a of the substrate 200, and The plurality of data lines DL arranged in one direction with a predetermined interval on the display unit 200a to vertically cross the gate lines GL, and the gate lines GL and each data line DL. A pixel electrode (not shown) formed in each of the plurality of pixel regions P defined in a matrix form, and the thin film transistor T formed near the intersection of each of the gate lines GL and each of the data lines DL. ), A gate transfer line 201 extending from the gate line GL to the non-display portion 200b and connected to an output pin 241 of the gate driver 250, and the non-display portion from the data line DL. Extended to 200b to exit the data driver 260. It includes the 202 data d to be connected to the pin 242.

Here, the gate driver 250 and the data driver 260 are located at the lower edge of the non-display portion 200b. The gate transmission lines 201 connected to the output pins 241 of the gate driver 250 are connected to the gate lines GL in different directions. That is, when the display unit 200a is divided in half with respect to an arbitrary gate line GL, the gate lines GL positioned at the top of the display unit 200a may have the lower edge and the left side of the non-display unit 200b. It is connected to the gate transmission lines 201 (hereinafter, referred to as 'first gate transmission lines') passing along the edge. In addition, the gate lines GL positioned at the bottom of the display unit 200a may be referred to as gate transfer lines 201 (hereinafter referred to as 'second gate transfer lines') passing along lower and right edges of the non-display unit 200b. )

Therefore, the length of the first gate transmission line 201 is longer than that of the second gate transmission line 201, and thus the first gate transmission line 201 is not formed between the first gate transmission line 201 and the second gate transmission line 201. Resistance difference may occur.

In order to prevent such a difference in resistance, in the liquid crystal display according to the first exemplary embodiment of the present invention, the first gate transmission line 201 includes first and second transmission layers.

Here, an insulating film is formed between the first transport layer and the second transport layer, and a plurality of contact holes penetrating the insulating film are formed in the insulating film, and the first transport layer and the second transport layer are formed in the contact. It is electrically connected to each other through the hole.                     

As described above, since the first gate transmission line 201 consists of two transmission layers, the first gate transmission line 201 according to the present invention has a larger area than the conventional first gate transmission line 201. Will have

Therefore, the first gate transmission line 201 of the present invention has less resistance than the prior art. In addition, since the first transfer layer 201a and the second transfer layer 201b of the first gate transfer line 201 of the present invention are vertically stacked in the vertical direction, the non-display unit in which the gate transfer line 201 is formed is formed. The area of 200b can be maintained as it is.

Here, the first transmission layer and the second transmission layer constituting the first gate transmission line 201 may have a structure as follows. If this is explained in more detail as follows. After that, unless otherwise stated, the gate transmission line 201 means the first gate transmission line 201.

3 is a diagram illustrating a first configuration of the display unit and the non-display unit of FIG. 2.

Referring to FIG. 3, a gate line GL and a data line DL perpendicular to each other are formed on the display unit 200a of the substrate 200, and are surrounded by the gate line GL and the data line DL. The pixel electrode PXL is formed in the pixel region P defined. In addition, a gate transfer line 201 extending from the gate line GL and a data transfer line 202 extending from the data line DL are formed in the non-display portion 200b of the substrate 200. . Here, the gate transmission line 201 is composed of a first transmission layer 201a and a second transmission layer 201b, and the first transmission layer 201a is made of the same material as the gate line GL. The second transport layer 201b is made of the same material as the data line DL.

In addition, a gate insulating film is formed between the first transfer layer 201a and the second transfer layer 201b, and the gate insulating layer connects between the first transfer layer 201a and the second transfer layer 201b. The gate pad contact hole and the first transfer contact hole C31 are formed therein.

Hereinafter, the manufacturing method of the liquid crystal display according to the present invention configured as described above will be described in detail.

4A to 4F are process cross-sectional views taken along lines I-I, II-II, III-III, and IV-IV of FIG. 3.

First, as shown in FIG. 4A, a substrate 200 having a display unit 200a and a non-display unit 200b is prepared. Here, the display unit 200a has a plurality of pixel areas P. FIG.

As shown in FIG. 4A, a metal layer is deposited on the entire surface of the substrate 200, and patterned through a photo and etching process to form a gate line GL on the display unit 200a of the substrate 200. The gate electrode GE and the first storage electrode ST1 are formed, and the gate pad electrode 231 and the first transfer layer 201a are formed in the non-display portion 200b of the substrate 200.

Here, the gate line GL is formed to be arranged in one direction at a predetermined interval, and the gate electrode GE is integrally formed with the gate line GL, and the pixel region P is formed from the gate line GL. It is formed to protrude.                     

The first storage electrode ST1 is a part of the gate line GL of another pixel region P adjacent to the pixel region P. That is, the gate line GL positioned between one pixel region P and the other pixel region P serves as a gate line GL for driving the thin film transistor T of the one pixel region P. At the same time, it serves as the first storage electrode ST1 of the other pixel region P.

The first transfer layer 201a is integrally formed with the gate line GL, extends from the gate line GL, and is formed on the non-display portion 200b, and the first transfer layer ( A gate pad electrode 231 is formed at the end of 201a. Here, the first transfer layer 201a and the gate pad electrode 231 are integrally formed.

Next, oxidation is performed on the entire surface of the substrate 200 including the gate line GL, the gate electrode GE, the first storage electrode ST1, the gate pad electrode 231, and the first transfer layer 201a. An insulating material such as silicon (SiOx) or silicon nitride (SiNx) is deposited to form a gate insulating layer GI.

Subsequently, as illustrated in FIG. 4B, a semiconductor material such as intrinsic amorphous silicon and an impurity semiconductor material such as amorphous silicon to which impurities are added are successively deposited on the entire surface of the substrate 200 including the gate insulating layer GI. The semiconductor layer 281 and the ohmic contact layer 282 are formed on the gate insulating layer GI on the upper side of the gate electrode GE.

Next, as shown in FIG. 4C, the gate insulating layer GI is etched to expose a portion of the gate pad electrode 231 and the gate pad contact hole C33 and the first transfer layer 201a. A first transmission contact hole C31 exposing a part is formed.

Subsequently, as shown in FIG. 4D, a metal layer such as chromium or molybdenum is deposited on the entire surface of the substrate 200 including the semiconductor layer 281 and the ohmic contact layer 282, and then, a photo and etching process is performed. By patterning, the data line DL, the source / drain electrodes SE and DE, the ohmic contact layer 282, and the second storage electrode ST2 are formed on the display portion 200a of the substrate 200. The data transfer line 202, the data pad electrode 232, and the second transfer layer 201b are formed on the non-display portion 200b of the substrate 200.

Here, the data lines DL are formed to be arranged in one direction with a predetermined interval, and are formed to vertically cross the gate line GL.

The source / drain electrodes SE and DE are formed to overlap both edges of the semiconductor layer 281. In this case, while the source / drain electrodes SE and DE are formed, the portion of the ohmic contact layer 282 formed in the portion corresponding to the channel region of the thin film transistor T is removed, and the ohmic contact layer 282 is divided into two portions. Separated into dogs. That is, one of the separated ohmic contact layers 282 is formed between the source electrode SE and one edge of the semiconductor layer 281, and the other is the drain electrode DE and the semiconductor layer 281. Is formed between the other edges. The source electrode SE is integrally formed with the data line DL and protrudes from the data line DL to be formed in the pixel area P.

The second storage electrode ST2 is formed on the gate insulating layer GI on the upper side of the first storage electrode ST1.                     

The data transmission line 202 extends from the data line DL and is formed in the non-display portion 200b, and the data pad electrode 232 is formed at an end of the data transmission line 202. The data transmission line 202 and the data pad electrode 232 are integrally formed.

The second transfer layer 201b is formed on the gate insulating layer GI on the upper side of the first transfer layer 201a. At this time, the end 201c of the second transfer layer 201b is the gate pad. It is formed on the gate insulating film GI on the upper side of the electrode 231.

In this case, the end 201c of the second transfer layer 201b is connected to the end of the first transfer layer 201a, that is, the gate pad electrode 231 through the gate pad contact hole C33.

As described above, the first transfer layer 201a and the second transfer layer 201b are interposed between the gate insulating layer GI and the gate pad contact hole C33 and the first transfer contact hole C31. By being connected to each other, a gate transmission line 201 formed of the first transmission layer 201a and the second transmission layer 201b is formed.

On the other hand, since the second transmission layer 201b is made of the same material as the data line DL and the data transmission line 202, the second transmission layer 201b and the data transmission line 202 are mutually different. The second transfer layer 201b is not formed on the gate insulating layer GI corresponding to the crossing portion. Therefore, the second transport layer 201b has the same shape as the first transport layer 201a and is only disconnected in the portion, as shown in FIG. 3.                     

Although not shown in the drawings, the disconnected portion of the second transfer layer 201b is used for the transparent conductive film ITO (Indium Tin Oxide) in the process of forming the pixel electrode PXL, which will be described later (FIG. 4F). It may be connected to each other. Of course, prior to the process of connecting the disconnected portion, the process of forming a contact hole exposing the disconnected portion (FIG. 4E) should be preceded first. In this case, the contact hole exposing the disconnected portion is formed at the same time in the process of forming the drain contact hole (C38) to be described later.

Next, as illustrated in FIG. 4E, the substrate including the source / drain electrodes SE and DE, the second storage electrode ST2, the data pad electrode 232, and the second transfer layer 201b may be formed. A protective layer 290 is formed by depositing an organic insulating layer on the entire surface of the substrate 200, and etching the same to expose a portion of the drain electrode DE to expose the drain contact hole C38 and the second storage electrode ST2. Exposing a portion of the storage contact hole C39 exposing a portion, a second transfer contact hole C32 exposing a portion of the end 201c of the second transfer layer 201b, and a portion of the data pad electrode 232. The data pad contact hole C34 is formed.

Subsequently, as shown in FIG. 4F, a transparent conductive film (ITO; Indium Tin Oxide) is formed on the entire surface of the substrate 200 including the protective layer 290, and patterned through photo and etching processes. The pixel electrode PXL is formed on the display portion 200a of the substrate 200, and the gate pad terminal 261 and the data pad terminal 262 are formed on the non-display portion 200b of the substrate 200.

The display electrode 200a may be connected to the drain electrode DE and the second storage electrode ST2 through the drain contact hole C38 and the storage contact hole C39. It is formed in the pixel region P of. The gate pad terminal 261 is connected to the end 201c of the second transfer layer 201b through the second transfer contact hole C32, and the data pad terminal 262 is connected to the data pad contact. It is connected to the data pad electrode 232 through a hole C34.

In addition, the gate transmission line 201 may have a structure as follows.

5 is a diagram illustrating a second configuration of the display unit and the non-display unit of FIG. 2.

Referring to FIG. 5, a gate line GL and a data line DL perpendicular to each other are formed on the display unit 200a of the substrate 200, and are surrounded by the gate line GL and the data line DL. The pixel electrode PXL is formed in the pixel region P defined. In addition, a gate transfer line 201 extending from the gate line GL and a data transfer line 202 extending from the data line DL are formed in the non-display portion 200b of the substrate 200. . Here, the gate transmission line 201 is composed of a first transmission layer 501a and a second transmission layer 501b, and the first transmission layer 501a is made of the same material as the gate line GL. The second transfer layer 501b is made of the same material as the pixel electrode PXL.

In addition, a gate insulating film and a protective layer are formed between the first transfer layer 501a and the second transfer layer 501b, and the first transfer layer 501a and the second transfer layer ( A gate pad contact hole C51 and a transfer contact hole C53 are formed to connect the 501b.

The manufacturing method of the liquid crystal display according to the second exemplary embodiment of the present invention configured as described above will be described in detail as follows.

6A to 6E are process cross-sectional views taken along lines I-I, II-II, III-III, and IV-IV of FIG. 5.

First, as shown in FIG. 6A, a substrate 200 having a display unit 200a and a non-display unit 200b is prepared. Here, the display unit 200a has a plurality of pixel areas P. FIG.

As shown in FIG. 6A, a metal layer is deposited on the entire surface of the substrate 200, and patterned through a photo and etching process to form a gate line GL on the display unit 200a of the substrate 200. The gate electrode GE and the first storage electrode ST1 are formed, and the gate pad electrode 531 and the first transfer layer 501a are formed in the non-display portion 200b of the substrate 200.

Here, the gate line GL is formed to be arranged in one direction at a predetermined interval, and the gate electrode GE is integrally formed with the gate line GL, and the pixel region P is formed from the gate line GL. It is formed to protrude.

The first storage electrode ST1 is a part of the gate line GL of another pixel region P adjacent to the pixel region P. That is, the gate line GL positioned between one pixel region P and the other pixel region P serves as a gate line GL for driving the thin film transistor T of the one pixel region P. At the same time, it serves as the first storage electrode ST1 of the other pixel region P.

The first transfer layer 501a is integrally formed with the gate line GL, extends from the gate line GL, and is formed in the non-display portion 200b, and the first transfer layer A gate pad electrode 531 is formed at the end of 501a. The first transfer layer 501a and the gate pad electrode 531 are integrally formed.

Next, oxidation is performed on the entire surface of the substrate 200 including the gate line GL, the gate electrode GE, the first storage electrode ST1, the gate pad electrode 531, and the first transfer layer 501a. An insulating material such as silicon (SiOx) or silicon nitride (SiNx) is deposited to form a gate insulating layer GI.

Subsequently, as illustrated in FIG. 6B, a semiconductor material such as intrinsic amorphous silicon and an impurity semiconductor material such as amorphous silicon to which impurities are added are successively deposited on the entire surface of the substrate 200 including the insulating film, and these are photo-deposited. And patterning through an etching process to form a semiconductor layer 581 and an ohmic contact layer 582 on the gate insulating layer GI on the upper side of the gate electrode GE.

Next, as illustrated in FIG. 6C, a metal layer such as chromium or molybdenum is deposited on the entire surface of the substrate 200 including the semiconductor layer 581 and the ohmic contact layer 582, and the photo and etching process may be performed. Patterning through the substrate 200 to form the data line DL, the source / drain electrodes SE and DE, the ohmic contact layer 582, and the second storage electrode ST2 on the display unit 200a of the substrate 200. The data transmission line 202 and the data pad electrode 532 are formed on the non-display portion 200b of the substrate 200.

Here, the data lines DL are arranged in one direction with a predetermined interval, and are formed to vertically cross the gate lines GL.                     

The source / drain electrodes SE and DE are formed to overlap both edges of the semiconductor layer 581. In this case, while the source / drain electrodes SE and DE are formed, the portion of the ohmic contact layer 582 formed in the portion corresponding to the channel region of the thin film transistor T is removed, and the ohmic contact layer 582 is divided into two portions. Separated into dogs. That is, one of the separated ohmic contact layers 582 is formed between the source electrode SE and one edge of the semiconductor layer 581, and the other is the drain electrode DE and the semiconductor layer 581. Is formed between the other edges. The source electrode SE is integrally formed with the data line DL and is formed to protrude from the data line DL into the pixel region P.

The second storage electrode ST2 is formed on the gate insulating layer GI on the upper side of the first storage electrode ST1.

The data transmission line 202 extends from the data line DL and is formed in the non-display portion 200b, and a data pad electrode 532 is formed at an end of the data transmission line 202. The data transmission line 202 and the data pad electrode 532 are integrally formed.

Next, as illustrated in FIG. 6D, the data line DL, the source / drain electrodes SE and DE, the second storage electrode ST2, the data transfer line 202, and the data pad electrode 532 are illustrated. Forming a protective layer 590 by depositing an organic insulating layer on the entire surface of the substrate 200 including the drain, and etching the same to expose a part of the drain electrode DE, and the second storage electrode. The storage contact hole C59 exposing a part of the ST2 and the data pad contact hole C52 exposing a part of the data pad electrode 532 are formed. The protective layer 590 and the gate insulating layer GI are etched to form a gate pad contact hole C51 exposing a portion of the gate pad electrode 531 and a portion of the first transfer layer 501a. A transmission contact hole C53 for exposing is formed.

Subsequently, as shown in FIG. 6E, a transparent conductive film (ITO; Indium Tin Oxide) is formed on the entire surface of the substrate 200 including the protective layer 590, and patterned through a photo and etching process. The pixel electrode PXL is formed on the display portion 200a of the substrate 200, and the gate pad terminal 561, the data pad terminal 562, and the second transfer layer are formed on the non-display portion 200b of the substrate 200. 501b is formed.

The display unit 200a may be connected to the drain electrode DE and the second storage electrode ST2 through the drain contact hole C58 and the storage contact hole C59. It is formed in the pixel region P of. The gate pad terminal 561 is connected to the gate pad electrode 531 through the gate pad contact hole C51, and the data pad terminal 562 is connected to the data pad contact hole C52. It is connected to the data pad electrode 532.

The second transport layer 501b is on the passivation layer 590 above the first transport layer 501a so as to be connected to the first transport layer 501a through the transport contact hole C53. Is formed. The second transfer layer 501b and the gate pad terminal 561 are integrally formed.

As such, the first transfer layer 501a and the second transfer layer 501b have the gate insulating film GI and the protective layer 590 interposed therebetween, and the gate insulating layer GI and the protective layer 590 may be provided. The gate transmission line 201 including the first transmission layer 501a and the second transmission layer 501b is formed by being connected to each other through the gate pad contact hole C51 and the transmission contact hole C53.

Here, the second transport layer 501b has the same shape as the first transport layer 501a.

In addition, the gate transmission line 201 may have a structure as follows.

FIG. 7 is a third configuration diagram illustrating the display part and the non-display part of FIG. 2.

Referring to FIG. 7, a gate line GL and a data line DL perpendicular to each other are formed on the display unit 200a of the substrate 200, and are surrounded by the gate line GL and the data line DL. The pixel electrode PXL is formed in the pixel region P defined. In addition, a gate transfer line 201 extending from the gate line GL and a data transfer line 202 extending from the data line DL are formed in the non-display portion 200b of the substrate 200. .

Here, the gate transmission line 201 is a connection layer connecting the first transmission layer 701a, the second transmission layer 701b, and the first transmission layer 701a and the second transmission layer 701b ( 777, wherein the first transfer layer 701a is made of the same material as the gate line GL, and the second transfer layer 701b is made of the same material as the data line DL. The connection layer 777 is made of the same material as the pixel electrode PXL. The connection layer 777 may be formed through a first transmission contact hole C71 exposing the first transport layer 701a and a second transmission contact hole C72 exposing the second transport layer 701b. The first transport layer 701a and the second transport layer 701b are connected to each other.

Hereinafter, the manufacturing method of the liquid crystal display according to the present invention configured as described above will be described in detail.

8A to 8E are process cross-sectional views taken along lines I-I, II-II, III-III, and IV-IV of FIG. 7.

First, as shown in FIG. 8A, a substrate 200 having a display portion 200a and a non-display portion 200b is prepared. Here, the display unit 200a has a plurality of pixel areas P. FIG.

As shown in FIG. 8A, a metal layer is deposited on the entire surface of the substrate 200, and patterned through a photo and etching process to form a gate line GL on the display unit 200a of the substrate 200. The gate electrode GE and the first storage electrode ST1 are formed, and the gate pad electrode 731 and the first transfer layer 701a are formed in the non-display portion 200b of the substrate 200.

Here, the gate lines GL are formed to be arranged in one direction with a predetermined interval. The gate electrode GE is integrally formed with the gate line GL and protrudes from the gate line GL into the pixel region P.

The first storage electrode ST1 is a part of the gate line GL of another pixel region P adjacent to the pixel region P. That is, the gate line GL positioned between one pixel region P and the other pixel region P serves as a gate line GL for driving the thin film transistor T of the one pixel region P. FIG. At the same time, it serves as the first storage electrode ST1 of the other pixel region P.

The first transfer layer 701a is integrally formed with the gate line GL, extends from the gate line GL, and is formed in the non-display portion 200b, and the first transfer layer ( A gate pad electrode 731 is formed at the end of 701a. The first transfer layer 701a and the gate pad electrode 731 are integrally formed.

Next, oxidation is performed on the entire surface of the substrate 200 including the gate line GL, the gate electrode GE, the first storage electrode ST1, the gate pad electrode 731, and the first transfer layer 701a. An insulating material such as silicon (SiOx) or silicon nitride (SiNx) is deposited to form a gate insulating layer GI.

Subsequently, as shown in FIG. 8B, a semiconductor material such as intrinsic amorphous silicon and an impurity semiconductor material such as amorphous silicon to which impurities are added are successively deposited on the entire surface of the substrate 200 including the gate insulating layer GI. The semiconductor layer 781 and the ohmic contact layer 782 are formed on the gate insulating layer GI on the upper side of the gate electrode GE by patterning them through a photo and etching process.

Next, as shown in FIG. 8C, a metal layer such as chromium or molybdenum is deposited on the entire surface of the substrate 200 including the semiconductor layer 781 and the ohmic contact layer 782, and the photo and etching processes are performed. Patterning through the substrate 200 to form the data line DL, the source / drain electrodes SE and DE, the ohmic contact layer 782, and the second storage electrode ST2 on the display unit 200a of the substrate 200. The data transfer line 202, the data pad electrode 732, and the second transfer layer 701b are formed on the non-display portion 200b of the substrate 200.

Here, the data lines DL are arranged in one direction with a predetermined interval and are formed to vertically cross the gate line GL.

The source / drain electrodes SE and DE are formed to overlap both edges of the semiconductor layer 781. In this case, while the source / drain electrodes SE and DE are formed, the portion of the ohmic contact layer 782 formed in the portion corresponding to the channel region of the thin film transistor T is removed, and the ohmic contact layer 782 is divided into two portions. Separated into dogs. That is, one of the separated ohmic contact layers 782 is formed between the source electrode SE and one edge of the semiconductor layer 781, and the other is the drain electrode DE and the semiconductor layer 781. Is formed between the other edges. The source electrode SE is integrally formed with the data line DL and is formed to protrude from the data line DL to the pixel region P.

The second storage electrode ST2 is formed on the gate insulating layer GI on the upper side of the first storage electrode ST1.

The data transmission line 202 extends from the data line DL and is formed in the non-display portion 200b, and a data pad electrode 732 is formed at the end of the data transmission line 202. The data transmission line 202 and the data pad electrode 732 are integrally formed.

The second transfer layer 701b is formed on the gate insulating layer GI on the upper side of the first transfer layer 701a. In this case, the second transfer layer 701b is the data transfer line 202. The second transfer layer 701b is not formed on the gate insulating layer GI at the portion where the second transfer layer 701b and the data transfer line 202 cross each other. Therefore, the second transport layer 701b has the same shape as the first transport layer 701a, and is only disconnected at the intersecting portion, as shown in FIG. In addition, the second transport layer 701b does not completely cover the first transport layer 701a so that a first transport contact hole C71 may be formed in the first transport layer 701a.

Next, as illustrated in FIG. 8D, the data line DL, the source / drain electrodes SE and DE, the second storage electrode ST2, the data pad electrode 732, and the second transfer layer 701b are shown. The organic insulating layer is deposited on the entire surface of the substrate 200 including the first passivation layer to form a passivation layer 790, and then etched to expose a portion of the drain electrode DE to expose a portion of the drain electrode DE. The storage contact hole C79 exposing a part of the electrode ST2, the data pad contact hole C75 exposing a part of the data pad electrode 732, and the part of the second transfer layer 701b are exposed. The second transmission contact hole C72 is formed. The protective layer 790 and the gate insulating layer GI are etched to expose a portion of the gate pad contact hole C74 exposing a portion of the gate pad electrode 731 and a portion of the first transfer layer 701a. A first transmission contact hole C71 for exposing is formed.

Subsequently, as shown in FIG. 8E, a transparent conductive film (ITO; Indium Tin Oxide) is formed on the entire surface of the substrate 200 including the protective layer 790 and patterned through a photo and etching process. A pixel electrode PXL is formed on the display portion 200a of the substrate 200, and a gate pad terminal 761, a data pad terminal 762, and a connection layer are formed on the non-display portion 200b of the substrate 200. 777 is formed.

The display electrode 200a may be connected to the drain electrode DE and the second storage electrode ST2 through the drain contact hole C78 and the storage contact hole C79. It is formed in the pixel region P of.

The gate pad terminal 761 is connected to the gate pad electrode 731 through the gate pad contact hole C74, and the data pad terminal 762 is connected to the data pad contact hole C75 through the gate pad contact hole C74. It is connected to the data pad electrode 732.

The connection layer 777 is connected to the first transmission layer 701a and the second transmission layer 701b through the first and second transmission contact holes C71 and C72.

As such, the first and second transfer layers 701a and 701b are formed on the gate insulating layer GI and the protective layer 790 with the protective layer 790 interposed therebetween. By connecting to each other through the transmission contact holes (C71, C72), a gate transmission line 201 consisting of the first transmission layer 701a and the second transmission layer 701b is formed.

As illustrated in FIG. 7, the gate pad terminal 761 may be connected to the second transfer layer 701b through a second transfer contact hole C72.

Meanwhile, as in the first to third embodiments described above, the gate transmission line 201 may be formed of two layers, but the data transmission line 202 may be formed of two layers.

Hereinafter, a liquid crystal display according to a second embodiment of the present invention will be described in detail.

9 is a configuration diagram of a liquid crystal display according to a second embodiment of the present invention.

As shown in FIG. 9, the liquid crystal display according to the second exemplary embodiment of the present invention includes a plurality of gate lines GL arranged in one direction at predetermined intervals on the display unit 200a of the substrate 900, and The plurality of data lines DL arranged in one direction with a predetermined interval on the display portion 900a to perpendicularly cross the gate lines GL, and the gate lines GL and each data line DL. A pixel electrode (not shown) formed in each of the plurality of pixel regions P defined in a matrix form, and the thin film transistor T formed near the intersection of each of the gate lines GL and each of the data lines DL. ), A gate transfer line 901 extending from the gate line GL to the non-display portion 900b and connected to an output pin 941 of the gate driver 950, and the non-display portion from the data line DL. Extended to 900b to exit the data driver 960. It includes a data transmission line 902 connected to the pin 942.

The gate driver 950 and the data driver 960 are positioned at the lower edge of the non-display unit 900b. The data transmission lines 902 connected to the output pins 942 of the data driver 950 are connected to the data lines DL in different directions. That is, when the display unit 900a is divided in half with respect to the data line DL, the data lines DL positioned on the upper portion of the display unit 900a may have lower and left edges of the non-display unit 900b. It is connected to the data transmission line 902 (hereinafter referred to as 'first data transmission line') passing along. The data lines DL positioned at the lower end of the display unit 900a may be referred to as data transmission lines 902 (hereinafter, referred to as 'second data transmission lines') passing along lower and right edges of the non-display unit 900b. And notation).

Therefore, the first data transmission line 902 has a longer length than the second data transmission line 902, whereby a resistance difference between the first data transmission line 902 and the second data transmission line 902 is increased. May occur.

In order to prevent such a difference in resistance, in the liquid crystal display according to the second exemplary embodiment of the present invention, the first data transmission line 901 includes first and second transmission layers.

Here, an insulating film is formed between the first transport layer and the second transport layer, and a plurality of contact holes penetrating the insulating film are formed in the insulating film, so that the first transport layer and the second transport layer are the insulating film. Are electrically connected to each other via contact holes.

As described above, since the first data transmission line 902 consists of two transmission layers, the first data transmission line 902 according to the present invention has a larger area than the conventional first data transmission line. .

Therefore, the first data transmission line 902 of the present invention has less resistance than the prior art. In addition, since the first transmission layer and the second transmission layer of the first data transmission line 902 of the present invention are vertically stacked in the vertical direction, the non-display unit 900b in which the first data transmission line 902 is formed is formed. The area can be kept as it is.                     

Here, the first data transmission line 902 may have a structure as follows. If this is explained in more detail as follows. After that, unless otherwise stated, the data transmission line 902 refers to the first data transmission line 902.

FIG. 10 is a first configuration diagram of the display unit and the non-display unit of FIG. 9.

Referring to FIG. 10, a gate line GL and a data line DL that are perpendicular to each other are formed on the display portion 900a of the substrate 900, and are surrounded by the gate line GL and the data line DL. The pixel electrode PXL is formed in the pixel region P defined. A gate transfer line 901 extending from the gate line GL and a data transfer line 902 extending from the data line DL are formed in the non-display portion 900b of the substrate 900. .

Here, the data transmission line 902 is composed of a first transport layer 902a and a second transport layer 902a, 902b, and the first transport layer 902a is made of the same material as the gate line GL. The second transport layer 902b is made of the same material as the data line DL. In addition, a gate insulating layer is formed between the first transfer layer 902a and the second transfer layer 902b, and the gate insulating layer is used to connect the first transfer layer 902a and the second transfer layer 902b. First and second transmission contact holes are formed.

Hereinafter, the manufacturing method of the liquid crystal display according to the present invention configured as described above will be described in detail.

11A to 11E are process cross-sectional views taken along lines I-I, II-II, III-III, and IV-IV of FIG. 10.                     

First, as shown in FIG. 11A, a substrate 900 having a display portion 900a and a non-display portion 900b is prepared. Here, the display unit 900a has a plurality of pixel areas P. FIG.

As shown in FIG. 11A, a metal layer is deposited on the entire surface of the substrate 900, and patterned through a photo and etching process to form a gate line GL on the display portion 900a of the substrate 900. A gate electrode GE and a first storage electrode ST1 are formed, and a gate transfer line 901, a gate pad electrode 931, and a first transfer layer 902a are formed on the non-display portion 900b of the substrate 900. ), And an end 902c of the first transport layer.

Here, the gate lines GL are formed to be arranged in one direction with a predetermined interval. The gate electrode GE is integrally formed with the gate line GL and protrudes from the gate line GL into the pixel region P.

The first storage electrode ST1 is a part of the gate line GL of another pixel region P adjacent to the pixel region P. That is, the gate line GL positioned between one pixel region P and the other pixel region P serves as a gate line GL for driving the thin film transistor T of the one pixel region P. At the same time, it serves as the first storage electrode ST1 of the other pixel region P.

The gate transfer line 901 is integrally formed with the gate line GL and extends from the gate line GL to be formed in the non-display portion 900b.

A gate pad electrode 931 is formed at the end of the gate transfer line 901. The gate transfer line 901 and the gate pad electrode 931 are integrally formed.

On the other hand, since the first transfer layer 902a is made of the same material as the gate transfer line 901, a substrate (a part of the portion where the first transfer layer 902a and the gate transfer line 901 cross each other) The first transport layer 902a is not formed on 900. Accordingly, as shown in FIG. 10, the first transport layer 902a is disconnected at the crossing portion. Here, the end 902c of the first transfer layer 902a is formed in a region corresponding to the data pad electrode 932 which will be described later.

Next, the gate line GL, the gate electrode GE, the first storage electrode ST1, the gate transfer line 901, the gate pad electrode 931, the first transfer layer 902a, and the first transfer. An insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is deposited on the entire surface of the substrate 900 including the end 902c of the layer 902a to form a gate insulating layer GI.

Subsequently, as shown in FIG. 11B, a semiconductor material such as intrinsic amorphous silicon and an impurity semiconductor material such as amorphous silicon to which impurities are added are successively deposited on the entire surface of the substrate 900 including the gate insulating film GI. The semiconductor layer 981 and the ohmic contact layer 982 are formed on the gate insulating layer GI on the upper side of the gate electrode GE by patterning them through photo and etching processes.

Next, as illustrated in FIG. 11C, the gate insulating layer GI is etched to form a first transfer contact hole C91 exposing a portion of the first transfer layer 902a. In this case, a second transmission contact hole C92 exposing a part of the end 902c is formed at the end 902c of the first transport layer 902a.

Subsequently, as illustrated in FIG. 11D, a metal layer, such as chromium or molybdenum, is deposited on the entire surface of the substrate 900 including the semiconductor layer 981 and the ohmic contact layer 982, and then subjected to a photo and etching process. By patterning, the data line DL, the source / drain electrodes SE and DE, the ohmic contact layer 982, and the second storage electrode ST2 are formed on the display portion 900a of the substrate 900. The data pad electrode 932 and the second transfer layer 902b are formed on the non-display portion 900b of the substrate 900.

Here, the data lines DL are arranged in one direction with a predetermined interval, and are formed to vertically cross the gate lines GL.

The source / drain electrodes SE and DE are formed to overlap both edges of the semiconductor layer 981. Here, when the source / drain electrodes SE and DE are formed, the ohmic contact layer 982 is formed while the portion of the ohmic contact layer 982 formed in the portion corresponding to the channel region of the thin film transistor T is removed. It is separated into two. That is, one of the separated ohmic contact layers 982 is formed between the source electrode SE and one edge of the semiconductor layer 981, and the other is the drain electrode DE and the semiconductor layer 981. Is formed between the other edges. The source electrode SE is integrally formed with the data line DL and is formed to protrude from the data line DL to the pixel region P.

The second storage electrode ST2 is formed on the gate insulating layer GI on the upper side of the first storage electrode ST1.                     

The second transfer layer 902b extends from the data line DL and is formed in the non-display portion 900b, and a data pad electrode 932 is formed at an end of the second transfer layer 902b. . The second transfer layer 902b and the data pad electrode 932 are integrally formed.

In this case, the second transport layer 902b is connected to the first transport layer 902a through the first and second transport contact holes C91 and C92, and is provided at an end of the second transport layer 902b. The formed data pad electrode 932 is connected to the end 902c of the first transfer layer 902a through the second transfer contact hole C92.

As such, the first and second transfer contact holes C91 and the first and second transfer layers 902a and 902b are formed in the gate insulating layer GI with the gate insulating layer GI interposed therebetween. By connecting to each other via C92, a data transmission line 902 including the first transport layer 902a and the second transport layer 902b is formed.

Here, the first transport layer 902a and the second transport layer 902b have the same shape. However, as described above, the first transfer layer 902a is disconnected at a portion where the first transfer layer 902a and the gate transfer line 901 cross each other.

Next, as illustrated in FIG. 11E, the substrate including the source / drain electrodes SE and DE, the second storage electrode ST2, the data pad electrode 932, and the second transfer layer 902b may be formed. A protective layer 990 is formed by depositing an organic insulating layer on the entire surface of the substrate 900, and etching the same, to expose a portion of the drain electrode DE to expose the drain contact hole C98 and the second storage electrode ST2. A storage contact hole C99 exposing a portion thereof and a data pad contact hole C95 exposing a portion of the data pad electrode 932 are formed. The protective layer 990 and the gate insulating layer GI are etched to form a gate pad contact hole C94 exposing a part of the gate pad electrode 931.

Subsequently, as shown in FIG. 11F, a transparent conductive film (ITO; Indium Tin Oxide) is formed on the entire surface of the substrate 900 including the protective layer 990, and patterned through a photo and etching process. The pixel electrode PXL is formed on the display portion 900a of the substrate 900, and the gate pad terminal 961 and the data pad terminal 962 are formed on the non-display portion 900b of the substrate 900.

The pixel electrode PXL is connected to the drain electrode DE and the second storage electrode ST2 through the drain contact hole C98 and the storage contact hole C99. It is formed in the pixel region P.

The gate pad terminal 961 is connected to the gate pad electrode 931 through the gate pad contact hole C94, and the data pad terminal 962 is connected to the data pad contact hole C95. The data pad electrode 932 is connected.

In addition, the data transmission line 902 may have a structure as follows.

FIG. 12 is a second configuration diagram of the display unit and the non-display unit of FIG. 9.

Referring to FIG. 12, a gate line GL and a data line DL that are perpendicular to each other are formed on the display portion 900a of the substrate 900, and are surrounded by the gate line GL and the data line DL. The pixel electrode PXL is formed in the pixel region P defined. A gate transfer line 901 extending from the gate line GL and a data transfer line 902 extending from the data line DL are formed in the non-display portion 900b of the substrate 900. .

Here, the data transmission line 902 is composed of a first transport layer 1202a and a second transport layer 1202b. The first transport layer 1202a is made of the same material as the data line DL. The second transfer layer 1202b is made of the same material as the pixel electrode PXL. In addition, a gate insulating film and a protective layer are formed between the first transfer layer 1202a and the second transfer layer 1202b, and the first transfer layer 1202a and the second transfer layer ( A transmission contact hole C200 and a data pad contact hole C145 for connecting the 1202b are formed.

The manufacturing method of the liquid crystal display according to the exemplary embodiment of the present invention configured as described above will be described in detail.

13A to 13E are process cross-sectional views taken along lines I-I, II-II, III-III, and IV-IV of FIG. 12.

First, as shown in FIG. 13A, a substrate 900 having a display portion 900a and a non-display portion 900b is prepared. Here, the display unit 900a has a plurality of pixel areas P. FIG.

As shown in FIG. 13A, a metal layer is deposited on the entire surface of the substrate 900, and patterned through a photo and etching process to form a gate line GL on the display portion 900a of the substrate 900. The gate electrode GE and the first storage electrode ST1 are formed, and the gate transfer line 901 and the gate pad electrode 1231 are formed in the non-display portion 900b of the substrate 900.

Here, the gate line GL is formed to be arranged in one direction with a predetermined interval. The gate electrode GE is integrally formed with the gate line GL and protrudes from the gate line GL into the pixel region P.

The first storage electrode ST1 is a part of the gate line GL of another pixel region P adjacent to the pixel region P. That is, the gate line GL positioned between one pixel region P and the other pixel region P serves as a gate line GL for driving the thin film transistor T of the one pixel region P. At the same time, it serves as the first storage electrode ST1 of the other pixel region P.

The gate transfer line 901 is integrally formed with the gate line GL, extends from the gate line GL, and is formed in the non-display portion 900b, and the gate transfer line 901. The gate pad electrode 1231 is formed at the end of the gate pad electrode 1231. The gate transfer line 901 and the gate pad electrode 1231 are integrally formed.

Next, silicon oxide is formed on the entire surface of the substrate 900 including the gate line GL, the gate electrode GE, the first storage electrode ST1, the gate transfer line 901, and the gate pad electrode 1231. An insulating material such as (SiOx) or silicon nitride (SiNx) is deposited to form a gate insulating film GI.

Subsequently, as shown in FIG. 13B, a semiconductor material, such as intrinsic amorphous silicon, and an impurity semiconductor material, such as amorphous silicon, to which impurities are added, are continuously formed on the entire surface of the substrate 900 including the gate insulating film GI. The semiconductor layer 1281 and the ohmic contact layer 1282 are formed on the gate insulating layer GI on the upper side of the gate electrode GE by depositing and patterning them through a photo and etching process.

Subsequently, as shown in FIG. 13C, a metal layer, such as chromium or molybdenum, is deposited on the entire surface of the substrate 900 including the semiconductor layer 1281 and the ohmic contact layer 1282, and a photo and etching process is performed. Patterning to form the data line DL, the source / drain electrodes SE and DE, the ohmic contact layer 1282, and the second storage electrode ST2 on the display portion 900a of the substrate 900. The first transfer layer 1202a and the data pad electrode 1232 are formed in the non-display portion 900b of the substrate 900.

Here, the data lines DL are arranged in one direction with a predetermined interval and are formed to vertically cross the gate line GL.

The source / drain electrodes SE and DE are formed to overlap both edges of the semiconductor layer 1281. In this case, while the source / drain electrodes SE and DE are formed, the portion of the ohmic contact layer 1282 formed in the portion corresponding to the channel region of the thin film transistor T is removed, thereby allowing the ohmic contact layer 1282 to have two portions. Separated into dogs. That is, one of the separated ohmic contact layers 1282 is formed between the source electrode SE and one edge of the semiconductor layer 1281, and the other is the drain electrode DE and the semiconductor layer 1281. Is formed between the other edges. The source electrode SE is integrally formed with the data line DL and is formed to protrude from the data line DL to the pixel region P.                     

The second storage electrode ST2 is formed on the gate insulating layer GI on the upper side of the first storage electrode ST1.

The first transfer layer 1202a extends from the data line DL and is formed in the non-display portion 900b, and a data pad electrode 1232 is formed at an end of the first transfer layer 1202a. . The first transfer layer 1202a and the data pad electrode 1232 are integrally formed.

Next, as illustrated in FIG. 13D, the data line DL, the source / drain electrodes SE and DE, the second storage electrode ST2, the first transfer layer 1202a, and the data pad electrode 1232 are provided. A drain contact hole C198 and the second storage to form a protective layer 1290 by depositing an organic insulating layer on the entire surface of the substrate 900, and etching the same to expose a portion of the drain electrode DE. Data exposing a portion of the storage contact hole C199 exposing a portion of the electrode ST2, a transfer contact hole C200 exposing a portion of the first transfer layer 1202a, and a portion of the data pad electrode 1232. The pad contact hole C145 is formed. The protective layer 1290 and the gate insulating layer GI are etched to form a gate pad contact hole C144 exposing a part of the gate pad electrode 1231.

Subsequently, as illustrated in FIG. 13E, a transparent conductive film is formed on the entire surface of the substrate 900 including the protective layer 1290, and patterned through a photo and etching process to display the display portion of the substrate 900. The pixel electrode PXL is formed at 900a, and the gate pad terminal 1261, the data pad terminal 1262, and the second transfer layer 1202b are formed at the non-display portion 900b of the substrate 900.                     

The pixel electrode PXL may be connected to the drain electrode DE and the second storage electrode ST2 through the drain contact hole C198 and the storage contact hole C199. It is formed in the pixel region P.

The gate pad terminal 1261 is connected to the gate pad electrode 1231 through the gate pad contact hole C144, and the data pad terminal 1262 is connected to the data pad contact hole C145 through the gate pad contact hole C144. It is connected to the data pad electrode 1232.

The second transport layer 1202b is connected to the first transport layer 1202a through the transport contact hole C200.

As such, the first transport layer 1202a and the second transport layer 1202b are connected to each other through a transmission contact hole C200 formed in the protection layer 1290 with the protection layer 1290 interposed therebetween. In addition, a data transmission line 902 including the first transport layer 1202a and the second transport layer 1202b is formed.

The data pad terminal 1262 is integrally formed with the second transport layer 1202b. Meanwhile, the second transport layer 1202b has the same shape as the first transport layer 1202a.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

 As described above, the liquid crystal display device and the manufacturing method thereof according to the present invention have the following effects.

Each transmission line of the liquid crystal display according to the present invention includes at least two transmission layers connected to each other through a contact hole penetrating through an insulating layer.

Therefore, since each transmission line in the present invention has a larger area than the conventional transmission line, the resistance of each transmission line can be reduced.

In addition, since each transport layer constituting the transmission line is vertically stacked, the area of the conventional non-display portion can be maintained as it is.

That is, by using the transmission line of the structure according to the present invention, it is possible to prevent the distortion of the signal flowing along the transmission line, it is possible to reduce the size of the liquid crystal display device.

Claims (21)

A plurality of gate lines and data lines arranged to cross each other to define pixel areas of the liquid crystal panel; Pixel electrodes formed in the pixel areas; A plurality of transmission lines composed of at least two layers, each insulating layer being interposed between the layers, and each adjacent layer having a structure connected to each other through the insulating layer; And And a driver for transmitting signals to the gate line and the data line through the transmission line. The method of claim 1, And the transmission line is a gate transmission line for transmitting a gate signal from a gate drive IC to the gate line. The method of claim 2, And one layer of the gate transmission line is made of the same material as the gate line, and the other layer is made of the same material as the data line. The method of claim 2, And one layer of the gate line is made of the same material as the gate line, and the other layer is made of the same material as the pixel electrode. The method of claim 1, And said transmission line is a data transmission line for transferring a data signal from a data drive IC to said data line. The method of claim 5, And one layer of the data transmission line is made of the same material as the gate line, and the other layer is made of the same material as the data line. The method of claim 5, One layer of the data transmission line is made of the same material as the data line, and the other layer is made of the same material as the pixel electrode. A plurality of gate lines and data lines arranged to cross each other to define pixel areas of the liquid crystal panel; Pixel electrodes formed in the pixel areas; A plurality of transmission lines composed of at least two layers, the insulating layers being interposed between the layers, and the adjacent layers being connected to each other by a conductive material passing through the insulating layers; And And a driver for transmitting signals to the gate line and the data line through the transmission line. The method of claim 8, And wherein the conductive material is the same material as the pixel electrode. The method of claim 8, And the transmission line is a gate transmission line for transmitting a gate signal from a gate drive IC to the gate line. The method of claim 10, And one layer of the gate transmission line is made of the same material as the gate line, and the other layer is made of the same material as the data line. Preparing a substrate having a display unit and a non-display unit; Forming a gate line in one direction on the display unit and forming a first layer of a gate transmission line on the non-display unit and extending from the gate line; Forming a gate insulating film on an entire surface of the substrate including the gate line and the first layer; Forming a first contact hole penetrating the gate insulating film to expose the first layer; Forming a semiconductor layer and an ohmic contact layer on the gate insulating film in order to overlap the gate electrode protruding from the gate line; Forming a source / drain electrode on the ohmic contact layer to overlap both edges of the semiconductor layer, and gate transfer on the gate insulating film on the first layer to be connected to the first layer through the first contact hole Forming a second layer of lines; Forming a protective layer on an entire surface of the substrate including the source / drain electrodes and the second layer; Forming a second contact hole penetrating the protective layer to expose the drain electrode; And And forming a pixel electrode in a pixel area of the display unit so as to be connected to the drain electrode through the second contact hole. The method of claim 12, And the first layer is made of the same material as the gate line, and the second layer is made of the same material as the source / drain electrode. Preparing a substrate having a display unit and a non-display unit; Forming a gate line in one direction on the display unit and forming a first layer of a gate transmission line on the non-display unit and extending from the gate line; Forming a gate insulating film on an entire surface of the substrate including the gate line and the first layer; Forming a semiconductor layer and an ohmic contact layer on the gate insulating film in order to overlap the gate electrode protruding from the gate line; Forming a source / drain electrode on the ohmic contact layer to overlap both edges of the semiconductor layer; Forming a protective layer on an entire surface of the substrate including the source / drain electrodes; Forming a first contact hole through the protective layer and the gate insulating layer to expose the drain electrode, and a second contact hole exposing the first layer; And Protection on the first layer to form a pixel electrode in the pixel region of the display portion to be connected to the drain electrode through the first contact hole, and to be connected to the first layer through the second contact hole. And forming a second layer of the gate transfer line on the layer. The method of claim 14, And the first layer is made of the same material as the gate line, and the second layer is made of the same material as the pixel electrode. Preparing a substrate having a display unit and a non-display unit; Forming a gate line in one direction on the display unit and forming a first layer of a transmission line extending from the gate line in the non-display unit; Forming a gate insulating film on an entire surface of the substrate including the gate line and the first layer; Forming a semiconductor layer and an ohmic contact layer on the gate insulating film in order to overlap the gate electrode protruding from the gate line; Forming a source / drain electrode on the ohmic contact layer to overlap both edges of the semiconductor layer, and forming a second layer of the transmission line on the gate insulating layer to overlap the first layer;  Forming a protective layer on a front surface of the substrate including the source / drain electrodes and the second layer; Forming a first contact hole through the protective layer and the gate insulating layer to expose the drain electrode, a second contact hole exposing the first layer, and a third contact hole exposing the second layer; And Forming a pixel electrode in the pixel area of the display unit to be connected to the drain electrode through the first contact hole, and connecting the first layer and the second layer through the second and third contact holes. A method of manufacturing a liquid crystal display device comprising the step of forming a connection layer. The method of claim 16, The first layer is made of the same material as the gate line, the second layer is made of the same material as the data line, and the connection layer is made of the same material as the pixel electrode. Manufacturing method. Preparing a substrate having a display unit and a non-display unit; Forming a gate line in one direction on the display unit and forming a first layer of a data transmission line on the non-display unit; Forming a gate insulating film on an entire surface of the substrate including the gate line and the first layer; Forming a first contact hole penetrating the gate insulating film to expose the first layer; Forming a semiconductor layer and an ohmic contact layer on the gate insulating film in order to overlap the gate electrode protruding from the gate line; Forming a source / drain electrode on the ohmic contact layer to overlap both edges of the semiconductor layer, and transmitting data on the gate insulating film on the first layer to be connected to the first layer through the first contact hole; Forming a second layer of lines; Forming a protective layer on an entire surface of the substrate including the source / drain electrodes and the second layer; Forming a second contact hole penetrating the protective layer to expose the drain electrode; And And forming a pixel electrode in a pixel area of the display unit so as to be connected to the drain electrode through the second contact hole. The method of claim 18, And the first layer is made of the same material as the gate line, and the second layer is made of the same material as the source / drain electrode. Preparing a substrate having a display unit and a non-display unit; Forming a gate line in one direction on the display unit and forming a first layer of a data transmission line on the non-display unit; Forming a gate insulating film on an entire surface of the substrate including the gate line and the first layer; Forming a semiconductor layer and an ohmic contact layer on the gate insulating film in order to overlap the gate electrode protruding from the gate line; Forming a source / drain electrode on the ohmic contact layer to overlap both edges of the semiconductor layer; Forming a protective layer on an entire surface of the substrate including the source / drain electrodes; Forming a first contact hole through the protective layer and the gate insulating layer to expose the drain electrode, and a second contact hole exposing the first layer; And On the protective layer on the first layer to form a pixel electrode in the pixel area of the display unit to be connected to the drain electrode through the first contact hole and to be connected to the first layer through the second contact hole. And forming a second layer of the data transmission line in the second step. The method of claim 20, And the first layer is made of the same material as the gate line, and the second layer is made of the same material as the pixel electrode.

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