KR20060075832A - Flash memory device with stable auto read function regardless of external voltage and method for controlling auto read of the flash memory device - Google Patents

Abstract

The present invention relates to a flash memory device having a stable automatic read function independent of an external voltage and an automatic read control method thereof. The flash memory device according to the present invention provides a first reset signal when an external voltage becomes a first set voltage. Generating an external power-up reset circuit; An internal power-up reset circuit for generating a second reset signal when the internal voltage becomes a second set voltage; A timer for outputting an automatic read control signal when a predetermined time elapses from the time when the second reset signal is received; An automatic read circuit for generating a read control signal in response to the automatic read control signal; And a control circuit for generating a control signal to the internal circuit such that data corresponding to the first page is automatically read from the memory cell array of the internal circuit in response to the read control signal and stored in the page buffer. According to the present invention, when the internal voltage reaches a stable operating voltage level, the flash memory device can perform the automatic read operation stably regardless of the external voltage by controlling the automatic read operation.

Power-Up Reset, Auto Readout

Description

Flash memory device with stable auto read function regardless of external voltage and method for controlling auto read of the flash memory device}

1 is a block diagram of a conventional flash memory device.

2 is a block diagram of a flash memory device according to the present invention.

FIG. 3 is a graph of an external voltage and an internal voltage for explaining an operation of the flash memory device shown in FIG. 2.

FIG. 4 is a timing diagram of main signals related to the operation of the flash memory device shown in FIG. 2.

FIG. 5 is a detailed circuit diagram of the external and internal power-up reset circuits shown in FIG. 2.

6A and 6B are graphs of output voltages for explaining the operation of the external and internal power-up reset circuits shown in FIG.

<Explanation of symbols for main parts of drawing>

100: flash memory device 110: external power-up reset circuit

120: internal voltage generator 130: internal power-up reset circuit                 

140: timer 150: automatic read circuit

160: control circuit 170: internal circuit

The present invention relates to a flash memory device, and more particularly, to a flash memory device having an automatic read function.

In general, a flash memory device is used to store data in a mobile digital electronic device such as a digital camera or an MP3 player. Flash memory devices typically generate and use internal voltages from external voltages. In addition, a flash memory device having an automatic read function includes a power-up reset circuit and an automatic read control circuit. The power-up reset circuit senses when the external voltage rises above a set voltage level, that is, when the flash memory device is turned on, and generates a reset signal. The automatic read control circuit controls internal circuits of the flash memory device such that data corresponding to the first page of the memory cell array is automatically read and stored in the page buffer in response to the reset signal. In addition, all circuits within the flash memory device are initialized by the reset signal.

On the other hand, some of the circuits inside the flash memory device use the internal voltage as its operating voltage. Since the internal voltage is generated based on the external voltage, the level of the external voltage is increased to the set voltage level, and the internal voltage is raised to the set voltage level only after a predetermined time has elapsed. However, as shown in FIG. 1, in the conventional flash memory device 10, a reset signal RESET is generated when the power-up reset circuit 11 detects that the external voltage VDD_EX rises to a set voltage level. In addition, the automatic read circuit 12 operates in response to the reset signal RESET. Therefore, before the internal voltage rises to the set voltage level, the automatic readout circuit 12 generates the automatic readout signal ATRE to the control circuit 13, and causes the control circuit 13 to perform the automatic readout operation. do. Therefore, there is a problem that the flash memory device 10 operates abnormally. As a result, abnormal data may be read from the flash memory device 10.

Accordingly, an aspect of the present invention is to provide a flash memory device having a stable automatic read function regardless of an external voltage by controlling to perform an automatic read operation based on a change in an internal voltage.

Another object of the present invention is to provide an automatic read control method capable of automatically reading data stably regardless of an external voltage by controlling to perform an automatic read operation based on a change in an internal voltage.

According to another aspect of the present invention, there is provided a flash memory device including an external power-up reset circuit configured to generate a first reset signal when an external voltage becomes a first set voltage; An internal power-up reset circuit for generating a second reset signal when the internal voltage becomes a second set voltage; A timer for outputting an automatic read control signal when a predetermined time elapses from the time when the second reset signal is received; An automatic read circuit for generating a read control signal in response to the automatic read control signal; And a control circuit for generating a control signal to the internal circuit such that data corresponding to the first page is automatically read from the memory cell array of the internal circuit in response to the read control signal and stored in the page buffer.

According to another aspect of the present invention, there is provided an automatic read control method of a flash memory device, the method comprising: generating a first reset signal when an external voltage becomes a first set voltage; Generating a second reset signal when the internal voltage becomes a second set voltage; Outputting an automatic read control signal when a predetermined time elapses from the time when the second reset signal is generated; And generating a read control signal in response to the automatic read control signal, and automatically reading data corresponding to the first page from the memory cell array of the flash memory device and storing the read data in the page buffer.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

2 is a block diagram of a flash memory device according to the present invention. Referring to FIG. 2, the flash memory device 100 includes an external power-up reset circuit 110, an internal voltage generator 120, an internal power-up reset circuit 130, a timer 140, and an automatic read circuit 150. ), Control circuit 160, and internal circuit 170. The external power-up reset circuit 110 receives an external voltage VDDE and generates a first reset signal RST1 when the external voltage VDDE becomes a first set voltage. The internal voltage generator 120 generates an internal voltage VDDI based on the external voltage VDDE. The internal power-up reset circuit 130 receives the internal voltage VDDI and generates a second reset signal RST2 when the internal voltage VDDI becomes a second set voltage. The timer 140 outputs the automatic read control signal ARCTL when a predetermined time elapses from the time when the second reset signal RST2 is received. Preferably, the set time is a time taken until the internal voltage VDDI is sufficiently increased to reach a stable operating voltage level.

The automatic read circuit 150 generates a read control signal ATRD in response to the automatic read control signal ARCTL. The control circuit 160 automatically reads data corresponding to the first page from the memory cell array (not shown) of the internal circuit 170 in response to the read control signal ATRD, thereby providing a page buffer. The control signal CTL is generated in the internal circuit 170 to be stored in (not shown). Here, since the automatic reading operation of the flash memory device can be understood by those skilled in the art, a detailed description thereof will be omitted. Further, for the sake of simplicity, the components of the corresponding flash memory device associated with the automatic read operation are also not shown in FIG. 2.                     

FIG. 3 is a graph of an external voltage and an internal voltage for explaining an operation of the flash memory device shown in FIG. 2. Referring to FIG. 3, as the flash memory device is powered on, the external voltage VDDE is gradually increased at 0V. At this time, the internal voltage VDDI is also gradually increased in proportion to the external voltage VDDE. When the external voltage VDDE becomes V2 at the time point T1, the external power-up reset circuit 110 detects this and generates the first reset signal RST1. However, at this time point T1, the internal voltage VDDI is too low as V1. Thereafter, when the internal voltage VDDI becomes V2 at the time point T2, the internal power-up reset circuit 130 detects this and generates a second reset signal RST2. Although the internal voltage VDDI is high, V2 is an insufficient voltage level for the flash memory device 100 to operate normally. Therefore, the timer 140 waits until the time T3 is reached from the time point T2 when the second reset signal RST2 is received, and the automatic read control signal ARCTL is applied to the time point T3. Will print. Therefore, since the flash memory device 100 performs an automatic read operation after the internal voltage VDDI is sufficiently increased, the flash memory device 100 may operate more stably.

FIG. 4 is a timing diagram of main signals related to the operation of the flash memory device shown in FIG. 2. Referring to FIG. 4, after the time D1 elapses from the time point at which the external power-up reset circuit 110 generates the first reset signal RST1 (that is, the time point at which it is disabled), the internal power-up reset circuit 130 is performed. ) Disables the second reset signal RST2. After that, when the time D2 elapses, the timer 140 enables the automatic read control signal ARCTL.

FIG. 5 is a detailed circuit diagram of the external and internal power-up reset circuits shown in FIG. 2. Referring to FIG. 5, the configuration and specific operation of the external power-up reset circuit 110 and the internal power-up reset circuit 130 are substantially the same except for input / output signals. That is, in the case of the external power-up reset circuit 110, the external voltage VDDE is input and the first reset signal RST1 is output, whereas in the case of the internal power-up reset circuit 130, the internal voltage VDDI is output. ) Is input, and the second reset signal RST2 is output. In FIG. 5, the operation of the external power-up reset circuit 110 will be described. The external power-up reset circuit 110 includes resistors R1 and R2, an NMOS transistor NM, a PMOS transistor PM, and an inverter 111. The gate and the drain of the NMOS transistor NM are connected to a node N1, and the source thereof is connected to ground. The resistor R1 is connected between the node N1 and the external voltage VDDE. A gate of the PMOS transistor PM is connected to the node N1, a drain thereof is connected to a node N2, and the external voltage VDDE is input to a source thereof. The resistor R2 is connected between the node N2 and the ground. The inverter 111 inverts the signal VO2 received from the node N2, and outputs the inverted signal as the first reset signal RST1.

Next, the operation of the external power-up reset circuit 110 will be described. When the external voltage VDDE is gradually increased at 0V, since the NMOS transistor NM is diode connected, the voltage VO1 generated at the node N1 is equal to that shown in FIG. 6A. Likewise, it gradually increases to the voltage Vb level, and then maintains the voltage Vb level. In addition, the PMOS transistor PM has a time point at which the value obtained by subtracting the voltage VO1 generated at the node N1 from the external voltage VDDE becomes larger than the threshold voltage Vth of the PMOS transistor PM. It is turned on when (Ta). As a result, the voltage VO2 is generated at the node N2, and the voltage VO2 increases proportionally as the external voltage VDDE increases. Thereafter, the inverter 111 initially outputs the first reset signal RST1 to a high level, and inverts the first reset signal RST1 to a low level at the time Ta.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, when the internal voltage reaches a stable operating voltage level based on the change in the internal voltage, the flash memory device is stably automatically and independently controlled by performing an automatic read operation. A read operation may be performed.

Claims (4)

An external power-up reset circuit for generating a first reset signal when the external voltage becomes a first set voltage; An internal power-up reset circuit for generating a second reset signal when the internal voltage becomes a second set voltage; A timer for outputting an automatic read control signal when a predetermined time elapses from the time point at which the second reset signal is received; An automatic read circuit for generating a read control signal in response to the automatic read control signal; And And a control circuit for generating a control signal to the internal circuit so that data corresponding to the first page is automatically read from the memory cell array of the internal circuit in response to the read control signal and stored in the page buffer. The method of claim 1, And an internal voltage generator configured to generate the internal voltage based on the external voltage. The method of claim 1, And a time point at which the internal power-up reset circuit generates the second reset signal and a time point at which the external power-up reset circuit generates the first reset signal are different. In the automatic read control method of a flash memory device, Generating a first reset signal when the external voltage becomes a first set voltage; Generating a second reset signal when the internal voltage becomes a second set voltage; Outputting an automatic read control signal when a predetermined time elapses from the time when the second reset signal is generated; And Generating a read control signal in response to the auto read control signal, and automatically reading data corresponding to a first page from a memory cell array of the flash memory device and storing the read data in a page buffer.

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