KR20060073702A - Data integrated circuit and light emitting display device using the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data integrated circuit and a light emitting display device using the same, comprising: a voltage digital-to-analog converter for generating a gray scale voltage in response to data; The pixel current supplied to the first capacitor is increased or decreased by receiving a feedback of pixel current flowing through the pixels in response to the gray scale voltage, and the voltage level applied to the first capacitor is varied according to the increase or decrease of the current amount to supply the pixels. The present invention provides a data integrated circuit having a voltage adjusting block in which a voltage level of a gray scale voltage is variable.

Accordingly, since the grayscale voltage is changed by receiving the pixel current from each of the pixels, the image having the desired luminance can be displayed regardless of the variation of the transistors included in each of the pixels.

Organic EL, Data Drive, Feedback

Description

Data integrated circuit and light emitting display device using the same {DATA DRIVER AND LIGHT EMITTING DISPLAY FOR THE SAME}

1 illustrates a conventional light emitting display device.

2 is a diagram illustrating a light emitting display device according to an exemplary embodiment of the present invention.

FIG. 3 is a diagram illustrating a first embodiment of the data integrated circuit shown in FIG. 2.

FIG. 4 is a diagram illustrating a second embodiment of the data integrated circuit shown in FIG. 2.

5 is a view showing in detail the voltage adjusting block employed in the light emitting display device according to the present invention.

FIG. 6 is a circuit diagram illustrating a second embodiment of the pixel illustrated in FIG. 5.

FIG. 7 is a waveform diagram of a voltage adjusting block and a signal input to a pixel shown in FIG. 5.

*** Explanation of symbols on main parts of drawings ***

10,110: scan driver 20,120: data driver

30,130: image display unit 40,140: pixel

50,150: timing controller 129: data integrated circuit

200: shift register portion 210: sampling latch portion

220: holding latch portion 230: voltage digital to analog converter

240: current digital-analog converter 250: voltage regulator

251: current increasing unit 252: comparison unit

253 control unit 260 buffer unit

270 level shifter

The present invention relates to a data integrated circuit and a light emitting display using the same, and more particularly, to a data integrated circuit and a light emitting display using the same to display an image having a desired brightness.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. The flat panel display includes a liquid crystal display, a field emission display, a plasma display panel, a light emitting display, and the like.

Among the flat panel display devices, the light emitting display device is a self-light emitting device that generates light by recombination of electrons and holes. Such a light emitting display device has an advantage in that it has a fast response speed and is driven with low power consumption. In general, a light emitting display device emits light from a light emitting device by supplying a current corresponding to the data signal to the light emitting device using a transistor formed for each pixel.

1 illustrates a conventional light emitting display device. Referring to FIG. 1, a conventional light emitting display device includes an image display unit 30 including pixels 40 formed in an area partitioned by scan lines S1 to Sn and data lines D1 to Dm; Controlling the scan driver 10 for driving the scan lines S1 to Sn, the data driver 20 for driving the data lines D1 to Dm, the scan driver 10 and the data driver 20 The timing control part 50 is provided.

The timing controller 50 generates a data drive control signal DCS and a scan drive control signal SCS in response to the synchronization signals supplied from the outside. The data drive control signal DCS generated by the timing controller 50 is supplied to the data driver 20, and the scan drive control signal SCS is supplied to the scan driver 10. The timing controller 50 supplies the data Data supplied from the outside to the data driver 20.

The scan driver 10 receives the scan drive control signal SCS from the timing controller 50. The scan driver 10 receiving the scan driving control signal SCS generates a scan signal and sequentially supplies the generated scan signal to the scan lines S1 to Sn.

The data driver 20 receives the data drive control signal DCS from the timing controller 50. The data driver 20 receiving the data driving control signal DCS generates a data signal and supplies the generated data signal to the data lines D1 to Dm in synchronization with the scan signal.

The image display unit 30 receives the first power source Vdd and the second power source Vss from the outside and supplies them to the pixels 40. Each of the pixels 40 supplied with the first power source Vdd and the second power source Vss from the first power source Vdd to the second power source Vss via the light emitting element OLED in response to the data signal. By controlling the flowing current, light corresponding to the data signal is generated.

That is, in the conventional light emitting display device, each of the pixels 40 generates light having a predetermined luminance in response to a data signal. However, in the related art, light having a desired luminance may not be generated due to a nonuniform threshold voltage of a transistor included in each of the pixels 40. In the related art, there is no method of measuring and controlling the current flowing in each of the pixels 40 in response to the data signal.

Accordingly, an object of the present invention is to provide a data integrated circuit and a light emitting display device using the same, capable of displaying an image having a desired brightness.

As a technical means for achieving the above object, the first aspect of the present invention is a voltage digital-analog converter for generating a gradation voltage in response to data, a current digital-analog converter for generating a gradation current in response to the data; The pixel current flowing through the pixels in response to the gray voltage is fed back to increase or decrease the amount of current charged in the first capacitor, and according to the increase or decrease of the amount of current, the voltage level applied to the first capacitor is varied and supplied to the pixels. It is to provide a data integrated circuit having a voltage adjusting block whose voltage level of the gray level voltage is variable.

According to a second aspect of the present invention, there is provided an image display unit including a plurality of scan lines, a plurality of data lines, a plurality of feedback lines, and a plurality of pixels connected to the plurality of scan lines, the plurality of data lines, and the plurality of feedback lines. A scan driver for sequentially supplying scan signals to the scan lines of the plurality of data lines; and a data driver connected to the plurality of data lines and feedback lines, and for supplying a gray voltage to the plurality of data lines as data signals. A light emitting display device including a data integrated circuit according to the first aspect is provided.

According to a third aspect of the present invention, there is provided a method of generating a gradation voltage and a gradation current corresponding to data, supplying the gradation voltage to a plurality of pixels, and receiving feedback of the pixel current flowing in the pixels in response to the gradation voltage. And varying the voltage level applied to the first capacitor according to the increase or decrease of the amount of current charged in one capacitor to vary the voltage level supplied to the pixels. To provide.

According to a fourth aspect of the present invention, there is provided a method of generating a gradation voltage and a gradation current corresponding to data, transferring the gradation voltage to a data line during a first period of one horizontal period, and a first period of the first horizontal period. Comparing the pixel current flowing through the pixels with the grayscale current in response to the grayscale voltage during the second period except for the second period, and increasing or decreasing the amount of current charged in the first capacitor in response to the comparison result. The present invention provides a method of driving a light emitting display device, the method including varying a voltage level applied to the first capacitor to supply a voltage level to the pixels.

Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings.

2 is a diagram illustrating a light emitting display device according to an exemplary embodiment of the present invention. Referring to FIG. 2, a light emitting display device according to an exemplary embodiment of the present invention includes pixels formed in regions partitioned by scan lines S1 to Sn, data lines D1 to Dm, and feedback lines F1 to Fm. An image display unit 130 including 140, a scan driver 110 for driving the scan lines S1 to Sn, a data driver 120 for driving the data lines D1 to Dm, and a scan. A timing controller 150 for controlling the driver 110 and the data driver 120 is provided.

The image display unit 130 includes pixels 140 connected to the scan lines S1 to Sn, the data lines D1 to Dm, and the feedback lines F1 to Fm. The scan lines S1 to Sn are formed in a horizontal direction to supply scan signals to the pixels 140. The data lines D1 to Dm are formed in the vertical direction to supply data signals to the pixels 140. The feedback lines F1 to Fm supply the pixel current supplied from the pixels 140 to the data driver 120 in response to the data signal.

To this end, the feedback lines F1 to Fm are formed in the same direction (that is, the vertical direction) with the data lines D1 to Dm. The feedback lines F1 to Fm receive current from the pixels 140 to which the current data signal is supplied. In other words, the pixel current generated in the pixels 140 currently receiving the scan signal is supplied to the data driver 120 via the feedback lines F1 to Fm.

On the other hand, the pixels 140 are supplied with the first power source Vdd and the second power source Vss from the outside. Each of the pixels 140 supplied with the first power source Vdd and the second power source Vss has a second power source via the light emitting element from the first power source Vdd in response to a data signal from the data line D. FIG. Control the current flowing to (Vss). The pixels 140 supply a current (pixel current) flowing to the light emitting device to the feedback line F when the data signal is supplied to the data line D. FIG.

The timing controller 150 generates a data drive control signal DCS and a scan drive control signal SCS in response to external synchronization signals. The data driving control signal DCS generated by the timing controller 150 is supplied to the data driver 120, and the scan driving control signal SCS is supplied to the scan driver 110. The timing controller 150 supplies the data Data supplied from the outside to the data driver 120.

The scan driver 110 receives the scan driving control signal SCS from the timing controller 150. The scan driver 110 supplied with the scan driving control signal SCS generates a scan signal and sequentially supplies the generated scan signal to the scan lines S1 to Sn.

The data driver 120 receives the data drive control signal DCS from the timing controller 150. The data driver 120 receiving the data driving control signal DCS generates a data signal and supplies the generated data signal to the data lines D1 to Dm in synchronization with the scan signal. Here, the data driver 120 supplies a predetermined gray scale voltage to the data lines D as a data signal.

The data driver 120 receives the pixel current from each of the pixels 140 via the feedback lines F1 to Fm. The data driver 120 receiving the pixel current checks whether the current value of the pixel current corresponds to the data. For example, when the pixel current to flow in the pixel 140 corresponding to the number of bits (or gradation value) of the data (Data) is 10 ㎂, the data driver 120 checks whether the pixel current supplied to it is 10 ㎂ do.

Here, when the desired current is not supplied from each of the pixels 140, the data driver 120 changes the gray voltage so that a desired current flows from each of the pixels 140. To this end, the data driver 120 includes at least one data integrated circuit 129 including i (i is a natural number) channels. In FIG. 2, two data integrated circuits 129 are shown for convenience of description.

FIG. 3 is a diagram illustrating a first embodiment of the data integrated circuit shown in FIG. 2. Referring to FIG. 3, the data integrated circuit 129 may include a shift register unit 200 for sequentially generating sampling signals, and a sampling latch unit 210 for sequentially storing data in response to the sampling signals. The data data of the sampling latch unit 210 may be temporarily stored, and the stored data may be stored in a voltage digital-to-analog converter (hereinafter referred to as a "VDAC unit") 230 and a current digital-to-analog converter. Holding latch 220 for supplying to the 240 (hereinafter referred to as " IDAC unit "), VDAC unit 230 for generating a gradation voltage Vdata corresponding to the gradation value of data Data, and data Changing the gray scale voltage Vdata in response to the IDAC unit 240 generating the gray scale current Idata corresponding to the gray scale value of Data and the pixel current Ipixel supplied from the feedback lines F1 to Fj. The voltage adjusting block 250 and the gray scale voltage Vdata supplied from the voltage adjusting block 250. And a buffer unit 260 for supplying to the data lines (D1 to Dj).

The shift register unit 200 receives a source shift clock SSC and a source start pulse SSP from the timing controller 150. The shift register unit 200 supplied with the source shift clock SSC and the source start pulse SSP generates j sampling signals sequentially while shifting the source start pulse SSP every one period of the source shift clock SSC. do. To this end, the shift register unit 200 includes j shift registers 2001 to 200j.

The sampling latch unit 210 sequentially stores data Data in response to sampling signals sequentially supplied from the shift register 200. Here, the sampling latch unit 210 includes j sampling latches 2101 to 210j to store j data. Each of the sampling latches 2101 to 210j has a size corresponding to the number of bits of the data. For example, when the data are k bits, each of the sampling latches 2101 to 210j is set to a size of k bits.

The holding latch unit 220 receives data from the sampling latch unit 210 and stores the data when the source output enable signal SOE is input. The holding latch unit 220 supplies data stored therein to the VDAC unit 230 and the IDAC unit 240 when the source output enable signal SOE is input. To this end, the holding latch unit 220 includes j holding latches 2201 to 220j set to k bits.

The VDAC unit 230 generates a gray voltage Vdata corresponding to a bit value (that is, a gray value) of the data Data, and supplies the generated gray voltage Vdata to the voltage adjusting block 250. Here, the VDAC unit 230 generates j gray voltages Vdata corresponding to j data Data supplied from the holding latch unit 220.

The IDAC unit 240 generates a gradation current Idata corresponding to the bit value of the data, and supplies the generated gradation current Idata to the voltage adjusting block 250. Here, the IDAC unit 240 generates j gradation currents Idata corresponding to j data Data supplied from the holding latch unit 220.

The voltage adjustment block 250 is supplied with a gray voltage Vdata, a gray current Idata, and a pixel current Ipixel. The voltage adjusting block 250 supplied with the gradation voltage Vdata, the gradation current Idata, and the pixel current Ipixel compares the current difference between the gradation current Idata and the pixel current Ipixel, and compares the current difference with each other. Correspondingly, the gradation voltage Vdata is adjusted. Ideally, the voltage adjusting block 250 adjusts the voltage value of the gray voltage Vdata so that the gray current Idata and the pixel current Ipixel can be set to the same value. To this end, the voltage adjusting block 250 includes j voltage adjusting units 2501 to 250j.

The buffer unit 260 supplies the gray voltage Vdata supplied from the voltage adjusting block 250 to the j data lines D1 to Dj. To this end, the buffer unit 260 is provided with j buffers (2601 to 260j).

Meanwhile, in the present invention, as shown in FIG. 4, the level shifter unit 270 may be further included between the holding latch unit 220, the VDAC unit 230, and the IDAC unit 240. The level shifter unit 270 increases the voltage level of the data Data supplied from the holding latch unit 220 and supplies it to the VDAC unit 230 and the IDAC unit 240. When data having a high voltage level is supplied to the data integrated circuit 129 from an external system, a manufacturing cost increases because circuit components corresponding to the voltage level need to be installed. Therefore, the data Data having a low voltage level is supplied from the outside of the data integrated circuit 129, and the data Data having the low voltage level is boosted by the level shifter 270 to a high voltage level.

5 is a view showing in detail the voltage adjusting block employed in the light emitting display device according to the present invention. In FIG. 5, for convenience of description, the pixel connected to the j th voltage adjusting unit 250j and the j th voltage adjusting unit 250j will be described. Referring to FIG. 5, the voltage adjusting unit 250j includes the voltage adjusting unit 250j of the present invention including the current increasing unit 251, the comparing unit 252, the control unit 253, the first capacitor C1, and the first switching. The device SW1 includes a pixel, and the pixel 140 includes a pixel circuit and a light emitting device OLED, and the pixel circuit includes first to fifth transistors M5 and a second capacitor C2.

Referring to the voltage adjusting unit 250j, the first switching device SW1 is provided between the VDAC and the current increasing and decreasing unit 251. The switching device SW1 is turned on or turned off under the control of the controller 253. In practice, the first switching device SW1 is turned on only during the data signal supply period (first period) during one horizontal period as shown in FIG. 7, and is turned off during the other feedback period (second period).

The current increasing unit 251 includes second to fifth switching elements SW2 to SW5, and the second switching element SW2, the fourth switching element SW4, and the fifth switching element SW5 are P MOS transistors. The third switching device SW3 is implemented with an N MOS transistor.

The second to fifth switching elements SW5 are arranged to be connected to a source and a drain, respectively, the gate of the second switching element SW2 and the gate of the third switching element SW3 are connected to each other, and the fourth switching element SW4 is connected. The gate of and the gate of the fifth switching device (SW5) is connected. In addition, the gate of the second switching element SW2 and the gate of the third switching element SW3 are connected to the output terminal of the comparing unit 252, and according to the output signal of the comparing unit, the second switching element SW2 and the third switching element. The switching operation of (SW3) is determined.

The switching signal line CSW is connected to the gate of the fourth switching element SW4 and the gate of the fifth switching element SW5 to receive the switching signal csw through the switching signal line CSW. The switching signal line transmits a switching signal from the controller 253 and determines the on / off operation of the fourth switching device SW4 and the fifth switching device SW5.

The first power source Vdd is connected to one end of the second switching device SW2, the second power source Vss is connected to one end of the third switching device SW3, and the first power source Vdd is connected to the first power source Vdd. The voltage is higher than the second power source Vss so that a current flows from the first power source Vdd to the second power source Vss.

The comparator 252 receives the gradation current Idata from the IDAC unit 240 and the pixel current Ipixel from the pixel 140. Here, the pixel current Ipixel is supplied from the pixel 140 to which the current data signal is supplied. The comparison unit 252, which receives the pixel current Ipixel and the gradation current Idata, compares the gradation current Idata and the pixel current Ipixel, and supplies a control signal corresponding to the result of the current increase / decrease unit 251. To pass on. In this case, the control signal output from the comparator 252 may have various voltage values according to the difference between the gradation current Idata and the pixel current Ipixel. That is, if the difference between the gradation current Idata and the pixel current Ipixel is large, the absolute value of the voltage level of the control signal becomes large. If the difference between the gradation current Idata and the pixel current Ipixel is small, the voltage level of the control signal is small. The absolute value of is reduced so that the amount of current flowing through the second switching device SW2 and the third switching device SW3 varies according to the magnitude of the voltage level of the control signal.

The controller 253 turns on the first switching device SW1 during the data signal supply period during one horizontal period 1H, and turns off the first switching device SW1 during the feedback period.

In addition, the control unit 253 transfers the switching signal csw through the switching signal line CSW to control the fourth switching element SW4 and the fifth switching element SW5 of the current increase / decrease unit 251 to thereby switch the first switch. When the device SW1 is turned on, the fourth switching device SW4 and the fifth switching device SW5 are turned off so that the gray voltage received through the VDAC is transferred to the first node N1. When the first switching device SW1 is turned off, the fourth switching device SW4 and the fifth switching device SW5 are turned on so that the second switching device SW2 and the third switching device SW3 are turned on. Make a current path between them.

The first capacitor C1 is connected to the first node N1, stores the gray voltage supplied from the VDAC 230 through the current increasing unit 251, and the current flows in by the second switching device SW2. Or the current charged by the third switching device SW3 flows toward the second power source Vss so that the gray voltage stored in the first capacitor C1 is changed.

The gray voltage is transmitted to the buffer 260j to increase the current driving capability of the gray voltage to the pixel 140. In this case, the first capacitor C1 may be a parasitic capacitor C1 of the data line.

Referring to the pixel, the first transistor M1 has a source connected to the pixel power source ELVdd, a drain connected to the second node N2, and a gate connected to the third node N3 so that the pixel current Ipixel. And a gray value of the pixel current Ipixel according to the voltage of the third node N3.

The second transistor M2 has a source connected to the second node N2, a drain connected to the comparator 252, a gate connected to the first scan line S1, and a pixel current formed by the first transistor M1. (Ipixel) is transferred to the comparator 252 so that the comparator 252 compares the pixel current Ipixel and the gradation current Idata.

The third transistor M3 has a source connected to the second node N2, a drain connected to the light emitting device OLED, and a gate connected to the second scan line S2 and input through the second scan line S2. When the size of the pixel current Ipixel flowing through the second node N2 is equal to that of the gradation current Idata when the switching operation is performed by the second scan signal s2, the light is transferred to the light emitting device OLED. OLED) to emit light. The second scan signal s2 becomes an on signal when the first scan signal s1 is an off signal and an off signal when the first scan signal s1 is an on signal.

Accordingly, the pixel current Ipixel is fed back when the first scan signal s1 is the on signal and the pixel current Ipixel is transferred to the light emitting device OLED when the second scan signal s2 is the on signal.

The fourth transistor M4 switches the voltage passing through the buffer 260j to the third node N3 according to the scan signal and transfers the voltage to the third node N3 from the first transistor M1. To generate current. In this case, the gate of the fourth transistor M4 is connected to the first scan line S1 to perform a switching operation according to the first scan signal s1.

In addition, the source and the drain are connected to the fourth transistor M4, and the gate is connected to the fifth transistor M5 having the second scan line S2 connected thereto, thereby reducing the error of the switching operation.

In addition, as illustrated in FIG. 6, the pixel may be configured by implementing the first to fifth transistors M5 as N-MOS transistors.

FIG. 7 is a waveform diagram of a voltage adjusting block and a signal input to a pixel shown in FIG. 5. Referring to FIG. 7, the operation of the voltage adjusting block and the pixel of FIG. 5 will be described in detail. First, the controller 256 turns on the first switching device SW1 during the data signal supply period during one horizontal period 1H. Let's do it. When the first switching device SW1 is turned on, the gray voltage Vdata supplied from the VDAC unit 230 is supplied to the data line Dj through the buffer 260j. The gray voltage Vdata supplied to the data line Dj is supplied to the pixel 140 selected by the scan signal as a data signal. The pixel 140 receiving the data signal supplies the pixel current Ipixel corresponding to the data signal to the feedback line Fj.

Thereafter, the control unit 256 turns off the first switching device SW1 during the feedback period during one horizontal period 1H. When the first switching device SW1 is turned off, the first node N1 is floated. At this time, the first node N1 maintains the voltage of the gray voltage Vdata by the first capacitor C1. In this case, the first capacitor C1 may be implemented as a parasitic capacitor of a data line.

During the feedback period, the comparator 252 receives the gradation current Idata and the pixel current Ipixel supplied from the IDAC unit 240. Here, the gradation current Idata is an ideal current value that should actually flow in the pixel 140 in response to the data, and the pixel current Ipixel is a current value that actually flows in the pixel 140. The comparator 252 supplied with the pixel current Ipixel and the gradation current Idata compares the pixel current Ipixel and the gradation current Idata and generates a control signal in response to the comparison result to generate a current increase / decrease unit 251. ).

The control signal is transmitted to the gates of the second switching device SW2 and the third switching device SW3 of the current increasing unit 251, and according to the voltage of the control signal, the second switching device SW2 or the third switching device. One of the switching elements SW3 is turned on, and the data line is connected through the second switching element SW2 according to the magnitude of the voltage applied to the gates of the second switching element SW2 and the third switching element SW3. The amount of current delivered to the controller and the amount of current flowing out of the data line through the third switching device SW3 are determined.

At this time, when the current is transferred to the data line or the current flows out of the data line, a change in the amount of current charged in the first capacitor C1 occurs and a predetermined voltage value stored in the first capacitor C1 is changed. Will change. This changed voltage is supplied to the pixel 140 via the buffer 260j.

In addition, during the feedback period, the control unit 256 transfers the switching signal csw through the switching signal line CSW according to the signal output from the comparator 252, so that the fourth switching device SW4 of the current increase / decrease unit 251 is provided. And the fifth switching device SW5. The switching signal csw repeats the on / off operation during the feedback period to prevent the gray voltage from being changed by the first power source Vdd or the second power source Vss when the first switching device SW1 is turned on. And transfer it to the first capacitor C1.

Then, the pixel 140 generates the pixel current Ipixel corresponding to the predetermined voltage transmitted by the first capacitor C1. Referring to the operation of the pixel, firstly, the fourth transistor M4 is turned on by the first scan signal s1 so that the first transistor M1 generates a pixel current Ipixel and flows to the second node N2. Let's go. The amount of the pixel current Ipixel is determined by the voltage transmitted to the third node N3 of the first transistor M1. At this time, the second transistor M2 is turned on by the first scan signal s1, and the third transistor M3 is turned off by the second scan signal s2 to compare the pixel current Ipixel. Feedback to 252. When the pixel current Ipixel and the gradation current Idata are the same through a feedback process, a voltage for allowing the pixel current to flow in the second capacitor C2 is stored, and the third scan signal s2 causes a third voltage. The transistor M3 is turned on so that the pixel current Ipixel flows to the light emitting device OLED so that the pixel current having the same magnitude as the gray scale current is the light emitting device OLED regardless of the threshold voltage of the first transistor M1. Will flow into.

In fact, in the present invention, the pixel current Ipixel flowing in the pixel 140 is controlled to be approximately equal to the gradation current Idata while repeating this process during the feedback period.

While preferred embodiments of the present invention have been described using specific terms, such descriptions are for illustrative purposes only and it is understood that various changes and modifications may be made without departing from the spirit and scope of the following claims. You must lose.

A data integrated circuit and a light emitting display device using the same according to the present invention compare a gradation current corresponding to data with a pixel current flowing in a pixel, and in response to the comparison result, the gradation voltage so that the pixel current is changed to a current value similar to the gradation current. By changing the (data signal), an image of desired luminance can be displayed. In particular, in the present invention, since the gradation voltage is changed by receiving a pixel current from each of the pixels, an image having a desired luminance can be displayed regardless of non-uniformity of transistors included in each of the pixels.

Claims (26)

A voltage digital-analog converter configured to generate grayscale voltages in correspondence with the data; A current digital-analog converter configured to generate a gradation current corresponding to the data; And The pixel current flowing through the pixels in response to the gray voltage is fed back to increase or decrease the amount of current charged in the first capacitor, and the voltage level applied to the first capacitor is changed to be supplied to the pixels according to the increase or decrease of the amount of current. And a voltage adjusting block at which the voltage level of the gray scale voltage is variable. The method of claim 1, And the first capacitor is at least one capacitor of a parasitic capacitor of a data line and a capacitor connected separately. The method of claim 1, The voltage adjusting block compares the pixel current with the gradation current and increases or decreases the voltage stored in the first capacitor in response to the comparison result. The method of claim 1, A latch unit configured to input the data into the voltage digital-analog converter and the current digital-analog converter in response to a sampling signal; And And a shift register unit which sequentially generates the sampling signal and transfers the sampling signal to the latch unit. The method of claim 4, wherein The latch portion A sampling latch unit for sequentially storing the data corresponding to the sampling signal; And a holding latch unit for storing the data stored in the sampling latch unit and simultaneously supplying the stored data to the voltage digital-analog converter and the current digital-analog converter. The method of claim 5, And a level shifter unit for raising a voltage level of the data stored in the holding latch unit and supplying the voltage level to the voltage digital-analog converter and the current digital-analog converter. The method of claim 3, wherein The voltage adjusting block includes j voltage adjusting units for controlling j (j is a natural number) gray voltages. The method of claim 7, wherein The voltage adjusting unit A first switching element disposed between the voltage digital-analog converter and a first node; A comparator for comparing the pixel current with the gradation current; A current increasing / decreasing unit which increases or decreases the amount of current supplied to the first capacitor under the control of the comparing unit; And And a control unit for controlling the switching element. The method of claim 8, And the control unit turns on the first switching device for a first period of one horizontal period, and turns off the switching device for a second period except the first period. The method of claim 9, And the gray voltage is transmitted to the first capacitor during the first period, and the pixel current is supplied to the comparison unit during the second period. The method of claim 8, The current increase and decrease portion A second switching element having a first electrode connected to a first power source, a second electrode connected to a first node, and a gate connected to an output terminal of the comparator; And A first switching electrode connected to a second power source, a second electrode connected to the first node, and a gate connected to the output terminal of the comparator; The second switching device and the third switching device are turned on at different times by the output of the comparator, the second switching device delivers current to the data line, and the third switching device is connected to the data line. Data integrated circuit that reduces the charged current. The method of claim 11, When the first switching device is turned on, the second switching device and the third switching device are opened, and when the first switching device is turned off, the second switching device and the third switching device are shorted. And a data integration circuit for transmitting the gray voltage to the first node. The method of claim 11, And the first capacitor receives and charges a current received by the first switching device, and reduces the current charged in the first capacitor through the second switching device. The method of claim 8, And the comparing unit compares the amount of current between the gradation current and the pixel current to generate a control signal in which a voltage value is determined according to a difference in the amount of current between the gradation current and the pixel current. The method of claim 11, The control unit is a data integrated circuit for transmitting a switching signal transmitted to the fourth and fifth switching device. The method of claim 15, By the switching signal, the fourth and fifth switching elements repeat the on-off operation during the first horizontal period to adjust the amount of current input through the first switching element and to adjust the amount of current reduced through the second switching element. Data integrated circuit to make. An image display unit including a plurality of scan lines, a plurality of data lines, a plurality of feedback lines, and a plurality of pixels connected to the plurality of scan lines, the plurality of data lines, and the plurality of feedback lines; A scan driver for sequentially supplying scan signals to the plurality of scan lines; And A data driver connected to the plurality of data lines and the feedback lines and for supplying a gray scale voltage to the plurality of data lines as a data signal; The data driving unit includes a data integrated circuit according to any one of claims 1 to 16. The method of claim 17, The pixel is Light emitting element; A first transistor configured to receive a third power source and flow a pixel current according to a voltage applied to the gate; A second transistor selectively receiving the pixel current by a first scan signal and transferring the pixel current to the comparison unit; A third transistor configured to selectively flow the pixel current to the light emitting element by a second scan signal; The fourth transistor configured to selectively transfer the gray voltage output from the buffer unit to the gate of the first transistor according to the scan signal; And And a second capacitor that maintains the voltage transmitted to the gate of the first transistor for a predetermined time. The method of claim 18, And a fifth transistor connected between the fourth transistor and the gate of the first transistor and transferring a voltage transferred through the fourth transistor to the gate of the first transistor. The method of claim 18, And the second scan signal is in inverse relationship with the first scan signal. The method of claim 18, The second capacitor And a pixel for storing the voltage such that the pixel current has the same amount of current. Generating a gray voltage and a gray current corresponding to the data; Supplying the gray voltage to a plurality of pixels; And The pixel current flowing through the pixels in response to the gray voltage is fed back to increase or decrease the amount of current charged in the first capacitor, and the voltage level applied to the first capacitor is changed to be supplied to the pixels according to the increase or decrease of the amount of current. And varying a voltage level of the gray level voltage. The method of claim 22, And controlling the voltage value of the gray voltage to increase or decrease the voltage value so that the pixel current and the gray current become the same or similar. Generating a gray voltage and a gray current in response to the data; Transferring the gray voltage to a data line during a first period of one horizontal period; Comparing the gradation current with a pixel current flowing in the pixels in response to the gradation voltage during a second period except the first period of the one horizontal period; And In response to the comparison result, the amount of current charged in the first capacitor is increased or decreased, so that the voltage level of the gray voltage applied to the first capacitor is varied according to the increase or decrease of the amount of current to vary the voltage level supplied to the pixels. A method of driving a light emitting display device comprising the steps. The method of claim 24, In the step of comparing the pixel current and the gradation current, a control signal is generated by comparing the gradation current and the pixel current, and the voltage value of the control signal varies depending on the gradation current and the voltage value of the pixel current. Method of driving display device. The method of claim 25, In the step of adjusting the voltage value supplied to the pixels, And transmitting a current to the data line when the voltage of the control signal is high and reducing a current charged in the data line when the voltage of the control signal is low.

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