KR20060064262A - Wiring for display device, thin film transistor array panel comprising the wiring and method for manufacturing the same - Google Patents

Abstract

A display device wiring comprising a first metal layer made of aluminum alloy (Al-alloy) and a second metal layer made of pure aluminum (Al-alloy), a substrate, a first metal layer formed on the substrate and made of aluminum alloy; A gate line including a second metal layer made of pure aluminum, a gate insulating film formed on the gate line, a semiconductor layer formed in a predetermined region on the gate insulating film, and formed on the gate insulating film and the semiconductor layer, A thin film transistor array panel including a data line, a drain electrode facing the source electrode at a predetermined interval, and a pixel electrode connected to the drain electrode, and a method of manufacturing the same.

Wiring, low resistance, aluminum, hillock, aluminum alloy

Description

Wiring for display device, thin film transistor array panel comprising the wiring and method for manufacturing the same}

1 is a layout view illustrating a structure of a thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along line II-II ',

3A, 4A, 5A, and 6A are layout views of a thin film transistor array panel sequentially showing a method of manufacturing the thin film transistor array panel illustrated in FIGS. 1 and 2 according to an embodiment of the present invention.

3B is a cross-sectional view taken along the line IIIb-IIIb 'of FIG. 3A,

4B is a cross-sectional view taken along the line IVb-IVb ′ of FIG. 4A;

5B is a cross-sectional view taken along the line Vb-Vb ′ of FIG. 5A;

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ of FIG. 6A;

Figure 7 (a) is a picture showing the heel lock (hillock) occurred in the gate line in the case of the conventional method, (b) (c) (d) shows a remarkably improved effect of the heel lock in accordance with the present invention It is a photograph.                 

* Explanation of symbols for main parts of the drawings

      110: insulated substrate 121: gate line

124: gate electrode 135: cover layer

140: gate insulating film 150: intrinsic amorphous silicon layer

160: impurity amorphous silicon layer 171: data line

173: source electrode 175: drain electrode

177: conductor for holding capacitor 180: protective film

181, 182, 185, 187, 189: contact hole 190: pixel electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device wiring, a thin film transistor array panel including the wiring, and a manufacturing method thereof.

Liquid crystal display is one of the most widely used flat panel displays. It consists of two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween. The display device is applied to rearrange the liquid crystal molecules of the liquid crystal layer to control the amount of light transmitted.

Among the liquid crystal display devices, a field generating electrode is provided in each of two display panels. Among these, the main structure is a structure in which a plurality of pixel electrodes are arranged in a matrix form on one display panel, and one common electrode covers the entire surface of the display panel on another display panel. The display of an image in such a liquid crystal display is performed by applying a separate voltage to each pixel electrode. To this end, a thin film transistor, which is a three-terminal element for switching a voltage applied to a pixel electrode, is connected to each pixel electrode, and a gate line for transmitting a signal for controlling the thin film transistor and a data line for transferring a voltage to be applied to the pixel electrode are provided. It is formed in each display panel. The thin film transistor serves as a switching element that transfers or blocks an image signal transmitted through a data line to a pixel electrode according to a scan signal transmitted through a gate line. Such a thin film transistor also serves as a switching element for individually controlling each light emitting element in an active organic light emitting diode (AM-OLED) which is a self-luminous element.

In such a thin film transistor, chromium (Cr) is mainly used as a material for a gate line including a gate electrode, a data line including a source electrode, and a drain electrode.

However, as the area of the display device becomes larger and larger, the lengths of the gate lines and the data lines become longer, and thus the wirings need to be formed of a material having a low specific resistance. However, since chromium has a high specific resistance, there is a limit to use in a large area liquid crystal display.

Therefore, in order to overcome the above problem, although aluminum (Al) having a low specific resistance is known as a suitable metal to be applied to a large area liquid crystal display device, a hillock phenomenon occurs when wiring is formed of aluminum (Al). Because of this, there is a limit to apply in actual process.

Accordingly, the present invention has been made to solve the above problems, and provides a display device wiring, a thin film transistor array panel including the wiring, and a method of manufacturing the same, which can prevent the hillock phenomenon while maintaining low resistance.

The wiring for a display device according to the present invention includes a first metal layer made of aluminum alloy (Al-alloy) and a second metal layer made of pure aluminum (pure-Al).

In addition, the thin film transistor array panel according to the present invention includes a substrate, a gate line formed on the substrate and including a first metal layer made of aluminum alloy (Al-alloy) and a second metal layer made of pure aluminum (pure-Al), A gate insulating film formed on the gate line, a semiconductor layer formed on a predetermined region on the gate insulating film, a data line formed on the gate insulating film and the semiconductor layer and including a source electrode and facing the source electrode at predetermined intervals; And a pixel electrode connected to the drain electrode.

In addition, the first metal layer is preferably made of an aluminum alloy containing aluminum (Al) and neodymium (Nd).

In addition, the method of manufacturing a thin film transistor array panel according to the present invention may include forming a gate line including a first metal layer made of aluminum alloy and a second metal layer made of pure aluminum on a substrate; Sequentially forming a gate insulating film and a semiconductor layer on the gate line, forming a data line including a source electrode and a drain electrode facing the source electrode at a predetermined interval on the gate insulating film and the semiconductor layer, and Forming a pixel electrode connected to the drain electrode.

In addition, the forming of the gate insulating film and the semiconductor layer is preferably performed at a temperature of 200 to 300 degrees.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right over" but also when there is another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Hereinafter, the structure of a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view illustrating a structure of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line II-II ′ of the thin film transistor array panel of FIG. 1.                     

As shown in FIGS. 1 and 2, a plurality of gate lines 121 are formed on the insulating substrate 110 to transfer gate signals. The gate line 121 extends in the horizontal direction, and a part of each gate line 121 forms a plurality of gate electrodes 124. In addition, another portion of each gate line 121 protrudes downward to form a plurality of expansions 127.

The gate line 121 is formed on the lower metal layers 124p, 127p and 129p made of aluminum alloy and the lower metal layers 124p, 127p and 129p and made of pure aluminum. (124q, 127q, 129q) (hereinafter referred to as "pure aluminum layer"). The pure aluminum layers 124q, 127q, and 129q serve to maintain a low resistivity, and the lower metal layers 124p, 127p, and 129p are formed under the pure aluminum layers 124q, 127q, and 129q to form gate lines ( 121) to prevent the occurrence of hillock (hillock).

Generally, aluminum (Al) is known to have a significantly lower specific resistance than other metals such as chromium (Cr), titanium (Ti), and molybdenum (Mo). Due to the problem of hillock, it is difficult to apply it in actual process. The hillock that occurs in the aluminum layer causes stress between the aluminum and the substrate having different thermal expansion coefficients due to high temperature heating and cooling of about 300 degrees or more, and the migration of atoms in the aluminum layer is solved. This means that the protrusion is formed. Figure 7 (a) shows a number of hillocks (1) that occur when exposed to high temperature of about 320 ℃ in a subsequent process after forming a pure aluminum layer.

Therefore, conventionally, other metals having relatively high resistivity are used as they are or in the form of aluminum alloys (Al-alloy) in which other metals such as niodymium (Nd) are added to aluminum (Al). However, aluminum alloys such as aluminum-niodymium (Al-Nd) also have a high specific resistance of about 30 to 40% compared to pure aluminum (Al), thereby greatly reducing the advantages as a wiring having low specific resistance.

In order to solve this problem, the present invention further includes a lower metal layer made of an aluminum alloy under the pure aluminum layer. In this case, the aluminum alloy layer may reduce the stress generated between the substrate 110 having a different thermal expansion coefficient and the pure aluminum layer on the upper portion, thereby reducing the occurrence of hillock.

In addition, in this case, since the lower metal layer is formed to have a thickness sufficiently thinner than that of the pure aluminum layer, it is possible to remarkably reduce the resistivity compared to the case of forming a wiring using only an aluminum alloy layer.

7 (b) shows that when the lower metal layer made of aluminum-neodymium is formed under the pure aluminum layer, hillock is significantly reduced than that of FIG. 7 (a) made of pure aluminum only.

Side surfaces of the lower metal layers 124p, 127p, and 129p and the pure aluminum layers 124q, 127q, and 129q are inclined, respectively, and the inclination angle is about 30 to 80 degrees with respect to the surface of the substrate 110.

A gate insulating layer 140 made of silicon nitride (SiNx) or the like is formed on the gate line 121.

A plurality of linear semiconductor layers 151 made of hydrogenated amorphous silicon or the like are formed on the gate insulating layer 140. The linear semiconductor layer 151 extends in the vertical direction, from which a plurality of extensions 154 extend toward the gate electrode 124. Further, the linear semiconductor layer 151 increases in width near the point where the linear semiconductor layer 151 meets the gate line 121 to cover a large area of the gate line 121.

A plurality of linear ohmic contacts 161 made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration on the semiconductor layer 151 and a plurality of island-type ohmic contacts. Layers 163 and 165 are formed. The islands of ohmic contact 163 and 165 are paired and positioned on the protrusion 154 of the semiconductor layer 151. Side surfaces of the semiconductor layer 151 and the ohmic contact layers 161, 163, and 165 are also inclined, and the inclination angle is 30 to 80 ° with respect to the substrate 110.

A plurality of data lines 171 and a plurality of drain electrodes including a source electrode 173 on the ohmic contacts 161, 163, and 165 and the gate insulating layer 140, respectively. 175, a plurality of storage capacitor conductors 177 and end portions 179 of data lines are formed.

The data line 171 extends in the vertical direction to cross the gate line 121 and transmit a data voltage. A plurality of branches extending from the data line 171 toward the drain electrode 175 forms a source electrode 173. The pair of source and drain electrodes 173 and 175 are separated from each other and positioned opposite to each other with respect to the gate electrode 124.

Although the data line 171 and the drain electrode 175 including the source electrode 173 may be formed as a single layer, the data line 171 and the drain electrode 175 may be formed as a double layer or a triple layer in consideration of resistivity and adhesiveness. In this embodiment, the first metal layers 171p, 173p, 175p, 177p, and 179p, the second metal layers 171q, 173q, 175q, 177q, and 179q and the third metal layers 171r, 173r, 175r, 177r, and 179r are formed. It is formed of a triple layer, and the second metal layers 171q, 173q, 175q, 177q, and 179q include aluminum (Al) having a low specific resistance.

The gate electrode 124, the source electrode 173, and the drain electrode 175 together with the protrusion 154 of the semiconductor 151 form a thin film transistor (TFT), and a channel of the thin film transistor The protrusion 154 is formed between the source electrode 173 and the drain electrode 175. The storage capacitor conductor 177 overlaps the extension portion 127 of the gate line 121.

Similarly to the gate line 121, the data line 171, the drain electrode 175, and the storage capacitor conductor 177 are also inclined with respect to the substrate 110 at an angle of about 30 to 80 °.

The island-type ohmic contact layers 163 and 165 exist between the semiconductor layer 154 below and the source electrode 173 and the drain electrode 175 thereon, and serve to lower the contact resistance. The linear semiconductor layer 151 has an exposed portion between the source electrode 173 and the drain electrode 175, and is not covered by the data line 171 and the drain electrode 175, and in most regions, the linear semiconductor layer ( Although the width of the 151 is smaller than the width of the data line 171, as described above, the width of the 151 is increased at the portion where the gate line 121 meets, thereby increasing the insulation between the gate line 121 and the data line 171.

On the data line 171, the drain electrode 175, the storage capacitor conductor 177, and the exposed semiconductor layer 151, an organic material having excellent planarization characteristics and photosensitivity, and plasma chemical vapor deposition ( A passivation layer made of a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F formed by Plasma Enhanced Chemical Vapor Deposition (PECVD), or silicon nitride (SiNx), an inorganic material ( 180 is formed of a single layer or a plurality of layers. For example, when formed of an organic material, a portion of the semiconductor layer 154 between the source electrode 173 and the drain electrode 175 is exposed to prevent the organic material of the passivation layer 180 from contacting the lower portion of the organic layer. An insulating film (not shown) made of silicon nitride (SiNx) or silicon oxide (SiO ₂ ) may be further formed.

The passivation layer 180 includes a plurality of contact holes 181 and 185 respectively exposing the gate portion 129, the drain electrode 175, the storage capacitor conductor 177, and the data portion 179. , 187, 182 are formed.

A plurality of pixel electrodes 190 and a plurality of contact assistants 81 and 82 formed of ITO or IZO are formed on the passivation layer 180.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 and the storage capacitor conductor 177 through the contact holes 185 and 187, respectively, to receive the data voltage from the drain electrode 175 and to maintain the storage capacitor. The data voltage is transmitted to the existing conductor 177.

The pixel electrode 190 to which the data voltage is applied rearranges the liquid crystal molecules of the liquid crystal layer by generating an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied. .

In addition, as described above, the pixel electrode 190 and the common electrode form a liquid crystal capacitor to maintain an applied voltage even after the thin film transistor is turned off. There is another capacitor connected in parallel with the capacitor, which is called the "storage electrode". The storage capacitor is formed by overlapping the pixel electrode 190 and the neighboring gate line 121 (which is referred to as a "previous gate line"), and the like, to increase the capacitance of the storage capacitor, that is, the storage capacitor. In order to increase the overlapped area by providing an extension part 127 extending the gate line 121, a protective film conductor 177 connected to the pixel electrode 190 and overlapping the extension part 127 is provided as a protective film. 180) Place it underneath to bring the distance between the two closer.

When the passivation layer 180 is formed of a low dielectric constant organic material, the aperture ratio may be increased by overlapping the pixel electrode 190 with the neighboring gate line 121 and the data line 171.

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gate line and the end portion 179 of the data line through the contact holes 181 and 182. The contact auxiliary members 81 and 82 compensate for and protect the adhesion between the end portion 129 of the gate line and the end portion 179 of the data line and an external device such as a driving integrated circuit.

Hereinafter, a method of manufacturing the thin film transistor array panel shown in FIGS. 1 and 2 according to an embodiment of the present invention will be described in detail with reference to FIGS. 3A to 6B and FIGS. 1 and 2.

3A, 4A, 5A, and 6A are layout views sequentially illustrating a method of manufacturing the thin film transistor array panel shown in FIGS. 1 and 2 according to an embodiment of the present invention, and FIG. 3B is IIIb- of FIG. 3A. 4B is a cross-sectional view taken along the line IVb-IVb 'of FIG. 4A, FIG. 5B is a cross-sectional view taken along the line Vb-Vb' of FIG. 5A, and FIG. 6B is a VIb of FIG. 6A. This is a cross-sectional view taken along the line -VIb '.

First, as shown in FIGS. 3A and 3B, a metal layer is formed on an insulating substrate 110 such as transparent glass.

The metal layer is here formed by co-sputtering. In the embodiment of the present invention, aluminum-neodymium alloys (Al-Nd) and aluminum (Al) are used as the targets of the cavity sputtering. Initially, no power is applied to the aluminum (Al) target, and only the aluminum-neodymium (Al-Nd) target is applied to form lower metal layers 124p, 127p, and 129p formed of aluminum-neodymium (Al-Nd) on the substrate. do. In this case, the lower metal layers 124p, 127p, and 129p are formed to have a thickness of about 200 to 1000 mW.

Next, after the power applied to the aluminum-neodymium (Al-Nd) target is turned off, the power applied to the aluminum (Al) is applied to form pure aluminum layers 124q, 127q, and 129q. In this case, pure aluminum layers 124q, 127q, and 129q are formed to a thickness of about 2000 to 2500 kPa.

Thereafter, the lower metal layers 124p, 127p, and 129p and the pure aluminum layers 124q, 127q and 129q contain an etching solution containing phosphoric acid (H ₃ PO ₄ ), nitric acid (HNO ₃ ), and acetic acid (CH ₃ COOH), for example. Batch etching is performed using an aluminum etchant containing 63-70% phosphoric acid, 4-8% nitric acid, 16-20% acetic acid and the balance of demineralized water.

 Next, a gate insulating layer 140 made of silicon nitride (SiNx) or the like is formed to cover the entire surface of the gate line 121. The gate insulating layer 140 is formed by chemical vapor deposition (CVD) at a temperature of about 300 ° C. or less.

In general, when the gate line 121 is formed of a pure aluminum layer, since the pure aluminum layer is exposed to a high temperature of about 320 to 370 degrees or more in a subsequent step of forming the gate insulating layer 140, a large amount of hillock is formed. Occurs. Hilllock is that when the aluminum layer formed on the substrate is exposed to a high temperature of about 320 degrees or more in the gate insulating film formation step, stress is generated between the aluminum and the substrate having a different coefficient of thermal expansion by heating and cooling. In order to do so, the migration of atoms in the aluminum layer occurs to form a protrusion. This is one of the reasons why the pure aluminum layer cannot be applied to the actual wiring.

 Figure 7 (a) shows a number of hillocks 1 generated when exposed to high temperature of about 320 ℃ in the subsequent process after forming the pure aluminum layer.

Therefore, in the present invention, in order to prevent the hillock, the gate insulating layer 140 is deposited at a temperature of 300 ° C. or lower, preferably at a temperature of about 230 to 270 ° C.

FIG. 7C shows a gate line made of pure aluminum when the gate insulating film is formed at a temperature of about 250 ° C. FIG. In this case, it can be seen that the hillocks are significantly reduced than in FIG.

In addition, (d) of FIG. 7 is a case where the conditions of (b) and (c) of FIG. 7 are simultaneously applied, and as the gate line 121, the pure aluminum layer and the aluminum-niodymium (Al) under the pure aluminum layer. The case of forming a double layer including a lower metal layer formed of -Nd) and a subsequent step of forming the gate insulating layer 140 at a temperature of about 250 ° C is shown. As shown in (d) of FIG. 7, not only the hillock was significantly reduced than in the case of FIG. 7a, but also the hillock was markedly reduced in comparison with FIGS. 7b and 7c. Can be.

Subsequently, a three-layer film of intrinsic amorphous silicon and an impurity doped amorphous silicon layer is successively stacked on the gate insulating layer 140, and an amorphous silicon layer doped with impurities and an intrinsic amorphous layer The silicon layer is photo-etched to form a linear intrinsic semiconductor layer 151 each including a plurality of protrusions 154 and a plurality of impurity semiconductor patterns 164. In this case, similarly to the gate insulation film 140, the temperature is formed at a temperature of 300 ° C or lower, preferably 230 to 270 ° C.

Subsequently, as shown in FIGS. 5A and 5B, a metal layer is stacked on the amorphous silicon layer 161 doped with impurities by sputtering or the like. The metal layer may be a single layer, but is preferably formed as a double layer or triple layer in consideration of low resistance characteristics and contact characteristics. In this case, the double layer may be formed of a lower metal layer and a pure aluminum layer including an aluminum alloy such as aluminum-neodymium (Al-Nd), and in the case of a triple layer, the first metal layer including molybdenum (Mo), and aluminum (Al). ) And a third metal layer including molybdenum (Mo). The metal layers are all formed in a thickness of about 3000 kPa, and the sputtering temperature is preferably about 150 ° C.

Next, the laminated film is patterned with an etchant to form a source electrode 173, a drain electrode 175, a storage capacitor conductor 177, and an end portion 179 of the data line.

Next, a plurality of protrusions 163 each including a plurality of protrusions 163 are removed by removing portions of the impurity semiconductor layer 161 that are not covered by the source electrode 173, the drain electrode 175, and the storage capacitor conductor 177. The linear ohmic contact layer 161 and the plurality of islands of ohmic contact 165 are completed, while the portion of the intrinsic semiconductor 154 beneath it is exposed. In this case, it is preferable to perform oxygen (O ₂ ) plasma to stabilize the surface of the exposed intrinsic semiconductor 154.

Next, as shown in FIGS. 6A and 6B, an organic material having excellent planarization characteristics and photosensitivity, a-Si: C: O, a formed by plasma enhanced chemical vapor deposition (PECVD) A low dielectric constant insulating material such as -Si: O: F, or silicon nitride (SiNx), which is an inorganic material, is formed in a single layer or a plurality of layers to form a passivation layer. In this case, it is deposited at a temperature of about 250 to 300 ℃.

Next, after the photoresist is coated on the passivation layer 180, the photoresist is irradiated with light through a photomask and developed to form a plurality of contact holes 181, 185, 187, and 182. In this case, in the case of the organic film having photosensitivity, the contact hole may be formed only by a photolithography process, and the gate opening 140 and the passivation layer 180 may be formed under etching conditions having substantially the same etching ratio.

Next, as shown in FIGS. 1 and 2, ITO or IZO is stacked on the substrate by sputtering, and a plurality of pixel electrodes 190 and a plurality of contact assistants 81 and 82 are formed by a photolithography process. .

Although preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the invention.

As described above, by forming a gate line of a double layer made of an aluminum alloy and pure aluminum, and at the same time lowering the formation temperature of the gate insulating film and the semiconductor layer, the hillock phenomenon appearing in the gate line made of aluminum can be prevented. Therefore, pure aluminum can be actually applied to the wiring to fully exhibit the advantages of the low resistance wiring, and at the same time, the production cost and time can be remarkably reduced as compared with the case of using the aluminum alloy.

Claims (12)

A display device wiring comprising a first metal layer made of aluminum alloy (Al-alloy) and a second metal layer made of pure aluminum (pure-Al). The wire of claim 1, wherein the aluminum alloy includes aluminum (Al) and niodymium (Nd). Board, A gate line formed on the substrate, the gate line including a first metal layer made of an aluminum alloy and a second metal layer made of pure aluminum; A gate insulating film formed on the gate line, A semiconductor layer formed in a predetermined region on the gate insulating film, A data line formed on the gate insulating layer and the semiconductor layer and having a drain electrode facing the source electrode at a predetermined interval, and A thin film transistor array panel including a pixel electrode connected to the drain electrode. The thin film transistor array panel of claim 1, wherein the first metal layer is formed of an aluminum alloy including aluminum (Al) and neodymium (Nd). The thin film transistor array panel of claim 1, wherein the second metal layer is thicker than the first metal layer. The thin film transistor array panel of claim 1, wherein the data line and the drain electrode include a metal layer including aluminum (Al). The thin film transistor array panel of claim 1, further comprising an ohmic contact layer doped with impurities on the semiconductor layer. Forming a gate line on the substrate, the gate line including a first metal layer made of an aluminum alloy and a second metal layer made of pure aluminum; Sequentially forming a gate insulating film and a semiconductor layer on the gate line; Forming a data line including a source electrode and a drain electrode facing the source electrode at a predetermined interval on the insulating layer and the semiconductor layer, and A method of manufacturing a thin film transistor array panel, the method comprising: forming a pixel electrode connected to the drain electrode. The thin film transistor array panel of claim 8, wherein the forming of the gate line is performed by sequentially stacking a first metal layer made of an aluminum alloy including aluminum (Al) and neodymium (Nd) and a second metal layer made of pure aluminum. Way. The method of claim 8, wherein the forming of the gate line comprises forming the first metal layer to a thickness of 200 to 1000 kW and the second metal layer to a thickness of 2000 to 2500 kW. The method of claim 8, wherein the forming of the gate insulating layer and the semiconductor layer is performed at a temperature of 200 to 300 degrees. The method of claim 8, further comprising forming an ohmic contact layer doped with impurities after forming the gate insulating layer and the semiconductor layer.

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