KR20060039483A - Method of detecting programmed fuse and programmed fuse detecting circuit for the same - Google Patents

Abstract

Disclosed is a method and circuit for determining whether to program a fuse for latching a voltage of a latch node, switching a latch node and a fuse node, and inverting the voltage of the latch node using an internal power voltage clamped from an external power supply voltage. It is. The method of determining whether or not a fuse is programmed generates an internal power supply voltage by clamping an external power supply voltage, precharges a latch node using the internal power supply voltage, switches using the internal power supply voltage, and flows a current through the fuse. The voltage of the latch node is varied according to whether the program is programmed and the voltage of the latch node is latched using the internal power supply voltage to determine whether the fuse is programmed. Therefore, even when a high voltage is applied from the outside, damage to the fuse can be prevented.

Description

Fuse program determination method and a fuse circuit for determining whether or not to program a fuse {METHOD OF DETECTING PROGRAMMED FUSE AND PROGRAMMED FUSE DETECTING CIRCUIT FOR THE SAME}             

1 is a circuit diagram of a circuit for determining whether a fuse is programmed according to an embodiment of the present invention.

2 is another example of the fuse unit 130 shown in FIG. 1.

FIG. 3 is a timing diagram for describing an operation of a program determining circuit of a fuse illustrated in FIG. 1.

4 is a flowchart illustrating a method of determining whether a fuse is programmed according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

S410: generating the internal power voltage

S420: latch node precharge step

S430: latch node voltage variation step

S440: Step of determining whether the fuse program

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and circuit for determining whether a fuse is programmed, and more particularly, to a method and circuit for determining whether or not a fuse is used for repairing a defect of a semiconductor memory device.

In the manufacture of a semiconductor memory device, if any one of a number of fine cells is defective, the semiconductor device cannot function as a memory device and thus is treated as a defective product. However, in spite of a defect occurring in only some cells in the memory device, it is inefficient in terms of yield to discard the entire device as a defective product. Therefore, when only a part of cells in the memory device are defective, the entire memory device can be used by replacing a defective cell by using a redundancy memory cell pre-installed in the memory device.

A repair operation using a redundancy cell is generally performed by installing spare rows and spare columns for each cell array to replace defective memory cells with defective memory cells in row / column units. For example, if a defective memory cell is found through a test after wafer processing is completed, a program operation for replacing a corresponding address with an address of a spare cell is performed in an internal circuit. Therefore, when an address signal corresponding to a bad line is input in actual use of the semiconductor memory device, the spare line is accessed instead of accessing the bad line.

Fuses are used in programs that replace bad memory cells with spare cells. The fuse programming method includes a blown fuse through an overcurrent, a burned fuse with a laser beam, a method of connecting the joints with a laser beam, and a program with an EPROM. Among them, the method of blowing a fuse with a laser beam is widely used because it is simple, reliable, and less likely to be wrongly programmed, and a polysilicon wire or a metal wire fuse is used.

However, the laser-based approach can not be used when a defective cell is found at the package stage because the repair is performed in the wafer state.

Antifuse can be programmed for fault relief simply at the package level. Antifuse is generally a resistive fuse device that has a high resistance when not programmed and has a low resistance after program operation. Antifuse devices typically have a dielectric such as silicon dioxide (SiO2), silicon nitride, tantalum oxide or silicon dioxide-silicon nitride-silicon dioxide (ONO) sandwiched between two conductors. It is composed of very thin dielectric materials such as composites. The antifuse is programmed in such a way as to break the dielectric between both conductors by applying a high voltage through the antifuse terminals for a sufficient time. Thus, when the antifuse is programmed, the resistance between both terminals of the antifuse becomes small.

In testing a semiconductor memory device, a high VCC test may be performed. In measuring the operating time of the semiconductor memory device, the test is performed at a voltage higher than the operating voltage of the semiconductor memory device to verify whether the semiconductor memory device is normally operated for a long time by a short test. As described above, the test is performed at a voltage higher than the operating voltage of the semiconductor memory device to test whether the semiconductor memory device is normally operated for a long time by a test for a relatively short time.

In the high voltage test, the use of a voltage higher than the operating voltage of the semiconductor memory device can reduce the test time. However, it is impossible to perform the test at a voltage higher than a predetermined level because there is a limit to the voltage that an element in the semiconductor memory device can withstand. Therefore, determining the appropriate level of voltage for high voltage testing is a very important issue.

The antifuse has a property of breaking a dielectric between both conductors when a high voltage is applied between both terminals. Therefore, the dielectric of the antifuse is likely to be destroyed during the high voltage test, which is a limiting factor in raising the voltage for the high voltage test. Therefore, it is necessary to prevent the antifuse from applying too high a voltage during the high voltage test.

      An object of the present invention for solving the above problems is to provide a method for determining whether to program a fuse to limit the voltage applied to the fuse to a predetermined level even when a high voltage is applied from the outside.

Another object of the present invention is to provide a circuit for determining whether a fuse is programmed to limit the voltage applied to the fuse to a predetermined level even when a high voltage is applied from the outside.

The method of determining whether a fuse is programmed to achieve the object of the present invention includes generating an internal power supply voltage by clamping a power supply voltage applied from the outside, even when a high voltage is applied from the outside. It prevents it from becoming abnormal. In addition, precharging the latch node using the internal power supply voltage, switching using the internal power supply voltage to flow a current through the fuse to change the voltage of the latch node according to whether or not the fuse is programmed, and using the internal power supply voltage And latching a voltage of the latch node to determine whether a fuse is programmed.

In accordance with another aspect of the present invention, a circuit for determining whether a fuse is programmed to generate an internal power supply voltage by clamping a power supply voltage supplied from an external device in a voltage clamp unit, and the internal power supply voltage is higher than a predetermined level even when a high voltage is applied from the outside. To prevent it from getting high. The switch unit switches between the fuse node and the latch node using an internal power supply voltage. The fuse unit changes the voltage of the fuse node according to whether the fuse is programmed by a current flowing through the switch unit. The latch unit precharges the latch node using the internal power supply voltage and latches the voltage of the latch node to determine whether the fuse is programmed.

In the method and circuit for determining whether the fuse is programmed, the fuse may be antifuse, but is not limited to antifuse. The method of determining whether the fuse of the present invention is programmed may be applied to all kinds of fuses whose characteristics change as a high voltage is applied to both ends.

In this case, the method of determining whether the fuse is programmed may be used to correct a defect of the semiconductor memory device. However, the present invention is not limited thereto and may be applied to all applications that program using a fuse.

In this case, the method of determining whether the fuse is programmed may be used when a high voltage is applied from the outside. However, it is not necessarily limited to those used in high voltage test.

Therefore, despite the application of a high voltage from the outside, an increase in the voltage applied to the fuse can be suppressed, and damage to the fuse can be prevented.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram of a circuit for determining whether a fuse is programmed according to an embodiment of the present invention.

Referring to FIG. 1, a circuit for determining whether a fuse is programmed according to an embodiment of the present invention includes a voltage clamp unit 110, a switch unit 120, a fuse unit 130, and a latch unit 140.

The voltage clamp unit 110 outputs an internal power supply voltage IVCC by clamping an input voltage. That is, the voltage clamp unit 110 rises along the input voltage to a predetermined level as the input voltage rises, and generates an internal power supply voltage IVCC that is not increased any more and remains constant when the predetermined voltage is reached. At this time, the internal power supply voltage IVCC may increase with an increase rate different from that of the external power supply voltage VCC. In addition, the internal power supply voltage IVCC may be kept constant at the time when the external power supply voltage VCC is constantly maintained, or may be kept constant even before the external power supply voltage VCC is constantly maintained. have. When the power supply voltage applied from the outside is a voltage below a predetermined level, the internal power supply voltage may be equal to the power supply voltage applied from the outside. When the power supply voltage applied from the outside becomes higher than a predetermined level, the internal power supply voltage may be kept constant without increasing along with the external power supply voltage. The voltage clamp unit 110 may be easily implemented using a voltage distribution circuit or a reference voltage generation circuit using a bandgap reference.

The switch unit 120 switches between the fuse node and the latch node using the internal power supply voltage IVCC. The switch unit 120 includes an NMOS transistor 121. In the NMOS transistor 121, a switching signal PRECH is applied to a gate, and a source and a drain are connected to the fuse node n1 and the latch node n2, respectively.

The switching signal PRECH is a signal generated using the internal power supply voltage IVCC. The switching signal PRECH rises as the internal power supply voltage IVCC increases in the initial stage of application of power, and when the internal power supply voltage IVCC reaches a certain level and remains constant, the switching signal PRECH equals the internal power supply voltage IVCC for a predetermined time. Can be kept constant. Therefore, as the switching signal PRECH rises, current may flow from the latch node n2 to the fuse node n1.

The fuse unit 130 varies the voltage of the fuse node n1 according to whether or not the fuse FUSE is programmed by a current flowing through the switch unit 120. For example, the fuse FUSE may be an anti-fuse. That is, when the current flows into the fuse node n1 of the fuse unit 130 through the switch unit 120, when the fuse FUSE is not programmed and has a high resistance value, the voltage of the fuse node n1 increases. Done. When the current flows into the fuse node n1 of the fuse unit 130 through the switch unit 120, when the fuse is programmed and has a low resistance value, the voltage of the fuse node n1 is the ground potential VSS. Stay close to.

The fuse unit 130 includes two NMOS transistors 131 and 132.

When the logic 'high' is applied to the address signal ADDRESS and the logic 'low' is applied to the inverted selection signal / SELECT, the NMOS transistor 131 drops the potential of the fuse node n1 to fuse the fuse. To be programmable. One terminal of the fuse FUSE shown in FIG. 1 is illustrated as being connected to the ground potential VSS, but is connected to a pad during programming to receive a high voltage from the outside.

The NMOS transistor 132 allows the boosted voltage VPP to be applied to the gate to maintain the voltage of the fuse node n1 at a predetermined level despite the high voltage that can be applied from the outside through the pad.

The latch unit 140 precharges the latch node n2 and latches the voltage of the latch node n2 using the internal power supply voltage IVCC. Therefore, the output signal RD is generated, and it is possible to determine whether the fuse FUSE is programmed.

The latch unit 140 includes three PMOS transistors 141, 142, and 143, two NMOS transistors 144 and 145, and an inverter 146.

The latch unit 140 first precharges the latch node n2 as the internal power supply voltage IVCC increases in the initial stage of power application. At this time, the latch signal VCCH remains low while the internal power supply voltage IVCC is rising, and then transitions high when the internal power supply voltage IVCC reaches and maintains a predetermined level. Since the latch signal VCCH is initially low when the power is applied, as the internal power supply voltage IVCC gradually increases, the voltage of the latch node n2 gradually increases to precharge. Thereafter, the voltage of the latch node n2 is determined according to whether the fuse FUSE is programmed, the latch signal VCCH transitions high, and the voltage of the latch node n2 is latched.

When the fuse FUSE is not programmed and has a high resistance value, the latch signal VCCH is low when the internal power supply voltage IVCC starts to rise, so the current path through the PMOS transistor 141 and the PMOS transistor 142 is low. Is formed. In addition, since the switching signal PRECH increases as the internal power supply voltage IVCC increases, current flows to the fuse node n1 through the PMOS transistor 141, the PMOS transistor 142, and the NMOS transistor 121. Since the gate of the NMOS transistor is connected to the boost voltage VPP, a current flows toward the fuse. However, since the fuse is not programmed, the resistance value of the NMOS transistor increases, so that the voltage of the fuse node n1 increases. Since the NMOS transistor 121 connects the fuse node n1 and the latch node n2 by the switching signal PRECH, the voltage of the latch node n2 increases as the voltage of the fuse node n1 increases. Since the latch signal VCCH becomes high when the internal power supply voltage IVCC is stabilized, the PMOS transistor 142 is turned off and the NMOS transistor 144 is turned on. Since the voltage of the latch node n2 rises, the inverter 146 outputs a low, so that the PMOS transistor 143 is turned on and the NMOS transistor 145 is turned off to stabilize the voltage of the latch node n2 high. At this time, since the NMOS transistor 144 is turned on, the inverter 146, the PMOS transistor 143, and the NMOS transistor 145 may be considered to constitute a latch circuit. The series of operations described above are described in a predetermined order for convenience of description, but in practice, operations of the respective parts may be performed in a different order or at the same time.

When the fuse is programmed and has a low resistance value, the latch signal VCCH is low when the internal power supply voltage IVCC starts to rise, thus forming a current path through the PMOS transistor 141 and the PMOS transistor 142. do. In addition, since the switching signal PRECH increases as the internal power supply voltage IVCC increases, current flows to the fuse node n1 through the PMOS transistor 141, the PMOS transistor 142, and the NMOS transistor 121. Since the gate of the NMOS transistor is connected to the boost voltage (VPP), current flows toward the fuse, and the fuse is programmed so that the resistance value is small. No. Since the NMOS transistor 121 connects the fuse node n1 and the latch node n2 by the switching signal PRECH, the voltage of the latch node n2 decreases according to the voltage of the fuse node n1. Since the latch signal VCCH becomes high when the internal power supply voltage IVCC is stabilized, the PMOS transistor 142 is turned off and the NMOS transistor 144 is turned on. Since the voltage of the latch node n2 falls, the inverter 146 outputs high, so that the NMOS transistor 145 is turned on and the PMOS transistor 143 is turned off to stabilize the voltage of the latch node n2 to low. At this time, since the NMOS transistor 144 is turned on, the inverter 146, the PMOS transistor 143, and the NMOS transistor 145 may be considered to constitute a latch circuit. The series of operations described above are described in a predetermined order for convenience of description, but in practice, operations of the respective parts may be performed in a different order or at the same time.

The circuit for determining whether a fuse is programmed as shown in FIG. 1 eventually outputs a low to the output node RD when the fuse FUSE is not programmed, and a high to the output node RD when the fuse FUSE is programmed. do.

The switching signal PRE is generated using the internal power supply voltage IVCC, and a high voltage is applied externally by providing the internal power supply voltage IVCC to the source and inverter 146 of the PMOS transistor 141 shown in FIG. 1. In this case, it is possible to determine whether the fuse is programmed without increasing the resistance value of the switch unit 120 or the trip point that is the point at which the inverter 146 determines the low / high.

2 is another example of the fuse unit 130 shown in FIG. 1.

Referring to FIG. 2, the fuse unit includes an NMOS transistor 132 and a fuse FUSE as shown in FIG. 1. Unlike that illustrated in FIG. 1, the fuse unit illustrated in FIG. 2 receives an address signal ADDRESS and a select signal SELECT through the gates of two NMOS transistors 210 and 220. As shown in FIG. 2, the drain of the NMOS transistor 210 is connected to the ground potential VSS.

When the select signal SELECT and the address signal ADDRESS are applied high, the NMOS transistor 210 and the NMOS transistor 220 are turned on to lower the potential of the fuse node n1 so that the fuse FUSE is programmable. Although one terminal of the fuse FUSE shown in FIG. 2 is illustrated as being connected to the ground potential VSS, it is connected to a pad during programming to receive a high voltage from the outside.

The NMOS transistor 132 allows the boosted voltage VPP to be applied to the gate to maintain the voltage of the fuse node n1 at a predetermined level despite the high voltage that can be applied from the outside through the pad.

The fuse unit may be implemented in various ways in addition to those shown in FIGS. 1 and 2.

FIG. 3 is a timing diagram for describing an operation of a program determining circuit of a fuse illustrated in FIG. 1.

Referring to FIG. 3, the internal power supply voltage IVCC gradually increases along with the external power supply voltage VCC, but does not increase any more and remains constant when a predetermined level is reached. This is because the internal power supply voltage IVCC is a voltage clamped to the external power supply voltage VCC. 3 is a case where the external power supply voltage VCC is a high voltage of a predetermined level or more. When the external power supply voltage VCC is not a high voltage, the internal power supply voltage IVCC is equal to the external power supply voltage VCC. 3 illustrates that the internal power supply voltage IVCC is kept constant at an earlier point than the external power supply voltage VCC, but the internal power supply voltage IVCC and the external power supply voltage VCC are constantly maintained at the same time. It may start to remain.

The latch signal VCCH transitions high when the internal power supply voltage IVCC is stabilized. Therefore, the latch unit shown in FIG. 1 latches the voltage of the latch node.

The switching signal PRECH increases with an increase in the internal power supply voltage IVCC and remains constant when the internal power supply voltage IVCC is kept constant. The switching signal PRECH remains constant for a predetermined time, such as the internal power supply voltage IVCC, and then transitions to a low level after a predetermined time elapses.

The boosted voltage VPP increases as the external power supply voltage VCC or the external power supply voltage IVCC increases, and is boosted when the external power supply voltage VCC or the external power supply voltage IVCC is kept constant. For example, the generated boosted voltage may be 4.1V or more.

Looking at the voltage change of the latch node (n2) First, when the fuse (FUSE) shown in Figure 1 is not programmed, the voltage of the latch node (n2) gradually increases and after the latch signal (VCCH) transitions high It remains high.

When the fuse FUSE shown in FIG. 1 is programmed, the voltage of the latch node n2 appears to rise initially and then remains low after the latch signal VCCH transitions high.                     

4 is a flowchart illustrating a method of determining whether a fuse is programmed according to an embodiment of the present invention.

Referring to FIG. 4, in the method of determining whether a fuse is programmed according to an embodiment of the present invention, an internal power supply voltage is first generated by clamping a power supply voltage applied from the outside (S410).

In this case, the clamping refers to generating an output voltage that rises along the input voltage up to a predetermined level as the input voltage increases, but does not rise any more and remains constant when the predetermined voltage is reached. When the power supply voltage applied from the outside is a voltage below a predetermined level, the internal power supply voltage may be equal to the power supply voltage applied from the outside. When the power supply voltage applied from the outside becomes higher than a predetermined level, the internal power supply voltage may be kept constant without increasing along with the external power supply voltage. Clamping can be easily performed using a voltage distribution circuit, a bandgap reference circuit, a clamp circuit, or the like.

In the method of determining whether the fuse is programmed according to an embodiment of the present invention, the latch node is precharged using the internal power supply voltage (S420). In this case, a latch signal that is activated when the internal power supply voltage increases and stabilizes may be used.

In addition, in the method of determining whether the fuse is programmed according to an embodiment of the present invention, the voltage of the latch node is changed according to whether the fuse is programmed by flowing current through the fuse by switching using the internal power supply voltage (S430). In this case, the fuse may be an antifuse. In this case, the voltage of the latch node may be increased when the fuse is not programmed, and the voltage of the latch node may be decreased when the fuse is programmed.

In addition, the method of determining whether the fuse is programmed according to an embodiment of the present invention determines whether the fuse is programmed by latching the voltage of the latch node using the internal power supply voltage (S440).

Although step S410 is performed before other steps, step S420, step S430, and step S440 may be performed in the order, reverse order, or simultaneously shown in FIG. 4.

In the above embodiment, the fuse is close to a short circuit when programmed, and when it is not programmed to determine whether the fuse is programmed using the example, but the technical concept of the present invention is limited to this. Not. In other words, if the fuse is close to the opening when programmed, and close to the short circuit if not programmed, the scope of the technical concept of the present invention is provided as long as the external power voltage is clamped to the latch, the switch, and the inverter. It cannot be seen as coming off.

As described above, the method for determining whether or not the fuse of the present invention is programmed and the determination circuit are used as a power supply for the latch unit and an inverter using an internal power supply voltage clamped from an external power supply voltage, and are provided to the switch unit. Therefore, even when a high voltage is applied from the outside as in the high voltage test, the voltage applied to the fuse does not become higher than a predetermined level, thereby preventing damage to the fuse. In addition, damage to the fuse eliminates the need to lower the voltage for high voltage testing, enabling effective high voltage testing. In addition, even when the external power supply voltage changes, it is possible to prevent an increase in the resistance value of the switch unit and a change in the trip point at which the inverter determines the low / high.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (8)

Generating an internal power supply voltage by clamping a power supply voltage applied from the outside; Precharging a latch node using the internal power supply voltage; Switching the voltage of the latch node according to whether the fuse is programmed by switching a current by using the internal power supply voltage to flow a current through the fuse; And And determining whether the fuse is programmed by latching a voltage of the latch node using the internal power supply voltage. The method of claim 1, And the internal power supply voltage maintains a constant voltage level even when a high voltage is applied to the power supply voltage during a high voltage test. The method of claim 1, The fuse is a method of determining whether the fuse, characterized in that the anti-fuse. The method of claim 1, The method of determining whether or not the fuse is programmed is used to determine a defect of a semiconductor memory device. A voltage clamp unit configured to generate an internal power supply voltage by clamping a power supply voltage supplied from the outside; A switch unit configured to switch between a fuse node and a latch node using the internal power supply voltage; A fuse unit for changing a voltage of the fuse node according to whether a fuse is programmed by a current flowing through the switch unit; And And a latch unit configured to precharge the latch node using the internal power supply voltage and latch the voltage of the latch node. The method of claim 5, wherein And the internal power supply voltage maintains a constant voltage level even when a high voltage is applied to the power supply voltage during a high voltage test. The method of claim 5, wherein Wherein the fuse is anti-fuse programming circuit, characterized in that the fuse. The method of claim 5, wherein And the fuse is programmed or not determined. The fuse is programmed to determine whether to fix the defect of the semiconductor memory device.

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