KR20060026235A - Apparatus for testing semiconductor memory module and method thereof - Google Patents

Abstract

A semiconductor memory module test facility is provided. The semiconductor memory module test facility includes an input module for receiving a plurality of sets of management numbers of semiconductor memory modules to be tested, a storage module for storing a plurality of sets of management numbers of pretested semiconductor memory modules, and a stored set with the input set of management numbers. And a control module for comparing the management number sets to determine whether the test is to proceed. In addition, a semiconductor memory module test method is provided.

Semiconductor Memory Modules, Tests, SPD

Description

Apparatus for testing semiconductor memory module and method

1 is a block diagram illustrating a semiconductor memory module test facility in accordance with an embodiment of the present invention.

2 is a flowchart illustrating a method of testing a semiconductor memory module according to an embodiment of the present invention.

3 is a flow chart showing in detail the step (S230) of determining whether to proceed with the test of FIG.

(Explanation of symbols for the main parts of the drawing)

10: input module 20: first storage module

30: control module 40: output module

50, 60, 70, 80: test system

55, 65, 75, 85: semiconductor memory module

57, 67, 77, 87: second storage module

100: semiconductor memory module test facility

The present invention relates to a semiconductor memory module test facility and a test method, and more particularly, to a semiconductor memory module test facility and a test method for shortening the semiconductor memory module test time and increasing the test efficiency.

In recent years, electronic devices and semiconductor devices have gradually required miniaturization, high integration, and high speed signals. In particular, a method of modularizing a plurality of semiconductor devices on a separate module substrate is used as a means for improving the information storage capability of the semiconductor device.

As the semiconductor memory module is widely used in this way, the test in the semiconductor memory module is also becoming increasingly important. The main purpose of semiconductor memory module testing is to detect basic assembly failures that can occur during module assembly and to detect failures inherent in semiconductor memory modules.

Basically, the test of the semiconductor memory module generates more noise than when the individual memories operate because several memories operate at the same time. Therefore, much time is required to test it.

In addition, the semiconductor memory module test performs a test by combining many kinds of memory modules and many kinds of test systems (for example, desktop computers, notebook computers, etc.). In the conventional case, a test is often repeated to test a combination that has already been tested. Therefore, there is a problem that the test time due to the duplicated test is lost and the test efficiency is lowered.

An object of the present invention is to provide a semiconductor memory module test facility for shortening the semiconductor memory module test time and increasing the test efficiency.

Another object of the present invention is to provide a semiconductor memory module test method for shortening a semiconductor memory module test time and increasing test efficiency.

Technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

In accordance with an aspect of the present invention, a semiconductor memory module test facility includes an input module that receives a plurality of management number sets of a semiconductor memory module to be tested and a plurality of management number sets of pre-tested semiconductor memory modules. A storage module for storing the control module, and a control module for comparing the input management number set with the stored management number set to determine whether to proceed with the test.

According to another aspect of the present invention, there is provided a method of testing a semiconductor memory module, the method comprising: receiving a plurality of management number sets of a semiconductor memory module to be tested, and a plurality of management number sets of pretested semiconductor memory modules And loading the management number set and the loaded management number set, respectively, to determine whether to proceed with the test.

Other specific details of the invention are included in the detailed description and drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

1 is a block diagram illustrating a semiconductor memory module test facility in accordance with an embodiment of the present invention.

Referring to FIG. 1, the semiconductor memory module test facility 100 includes a server 5 and a plurality of test systems 50, 60, 70, and 80. The server 5 also includes an input module 10, a first storage module 20, a control module 30, and an output module 40.

The plurality of test systems 50, 60, 70, and 80 are devices capable of mounting semiconductor memory modules 55, 65, 75, 85, such as desktop computers, notebook computers, palmtop computers, and network computers. It is possible. In general, since each manufacturer and each model is tested, the test system 50, 60, 70, 80 may be hundreds to thousands. Thus, each test system 50, 60, 70, 80 is assigned a unique test system control number. In addition, as an embodiment of the present invention, four test systems are represented as being connected to the server 5 via a LAN line, but is not limited thereto.

As described above, each test system 50, 60, 70, 80 is equipped with semiconductor memory modules 55, 65, 75, 85 to be tested. Each memory module includes a separate second storage module 57, 67, 77, 87. The second storage modules 57, 67, 77, and 87 generally use Serial Presence Detect (SPD).

The SPD is a ROM that contains basic information of the semiconductor memory module. When the test system is booted, the information of the SPD is read by the semiconductor memory controller. The read information is used for semiconductor memory initialization and initial timing setting of the test system.

For example, the information may be the size, speed, voltage, drive capability, number of matrix addresses, DIMM maker and RAM maker, etc. of a dual in-line memory module (DIMM). In one embodiment of the present invention, the management number of the semiconductor memory module is further input to the SPD. The control number is used to prevent duplicate testing. The method of assigning a management number is not limited to a predetermined method, and may be modified by those skilled in the art.

SPDs typically use an 8-pin serial EEPROM chip that is typically available in SDRAM (synchronous DRAM). However, the present invention is not limited thereto, and any storage medium capable of storing the above-described information may be used.                     

The input module 10 receives a plurality of sets of management numbers of semiconductor memory modules to be tested. The management number set includes one or more of a management number of a semiconductor memory module, a management number of a test system, and a test program management number. In general, the semiconductor memory modules 55, 65, 75, and 85 mounted in the test systems 50, 60, 70, and 80 are subjected to several tests. Therefore, each test program is also given a management number like the semiconductor memory module and the test system. By the way, the test program management number may exist in the test system 50, 60, 70, 80, or may be collectively managed in the server 5. If present in the test system 50, 60, 70, 80, it is entered into the input module 10 along with other management numbers, and if present in the server 5, loaded on the first storage module 20.

The first storage module 20 stores a plurality of sets of management numbers of pretested semiconductor memory modules. In other words, evaluation histories of semiconductor memory modules are stored. The first storage module 20 is divided into a RAM and a ROM, and information to be used in the control module 30 is loaded into the RAM from the ROM and used.

The control module 30 compares the management number set input through the input module 10 with a plurality of management number sets stored in the first storage module 20. The test results are determined based on the comparison result. The management number set means one or more of a semiconductor memory module management number, a test system management number, and a test program management number. Of course, the present invention is not limited thereto and may be modified within the scope of recognition by those skilled in the art.                     

Preferably, the test stops when all of the entered management number sets coincide with the pretested management number set. And, it outputs an error message and asks the user whether to retest even if the current test is already tested. If the entered control number set does not match the pretested control number set, the test is continued. Detailed test procedures will be described later.

The output module 40 receives a command from the control module 30 to stop the operation of the test systems 50, 60, 70, and 80, and outputs an error message through a display device (not shown). In addition, when the test is performed, the test result is output through a display device (not shown).

2 is a flowchart illustrating a method of testing a semiconductor memory module according to an embodiment of the present invention. 3 is a flow chart showing in detail the step (S230) of determining whether to proceed with the test of FIG.

2 and 3, first, a semiconductor memory module management number is input to the second storage modules 57, 67, 77, and 87 (S210). The test system management number and the test program management number have already been determined, and it is common to enter the predetermined storage medium.

The semiconductor memory module in which the semiconductor memory module management number is input is mounted in the test system (S220). After that, it is determined whether the test proceeds (S230).

Referring to FIG. 3, the test progress determination is performed by first inputting a plurality of management number sets of a semiconductor memory module to be tested to the server through the input module 10 (S232). The management number set means one or more of a semiconductor memory module management number, a test system management number, and a test program management number.

Thereafter, the management number sets of the semiconductor memory modules pretested into the RAM are loaded from the ROM in the first storage module 20 (S233). The control number set of the semiconductor memory module to be tested and the control number sets of the previously tested semiconductor memory modules are compared with each other to determine whether to continue the test.

First, it is determined whether the management numbers of the semiconductor memory modules are the same among the management number sets (S234). If the same, it is determined whether the test system management number is also the same (S236). If the test program management number is the same (S238), the test is stopped by interlocking (S260).

If any one of the management number set is not the same, the test is started because it has not been tested before (S240).

Referring back to FIG. 2, after stopping the test (S260), the control module 30 outputs an error message indicating that the semiconductor memory modules 55, 65, 75, and 85 to be tested are previously tested semiconductor memory modules. (S270). In addition, optionally, the user may be required to determine whether to retest even the same test that has already been tested (S280). That is, it is determined whether the same semiconductor memory modules 55, 65, 75, 85 are mounted in the same test system 50, 60, 70, 80 and retested with the same program. If the user determines to retest, the test starts (S240), otherwise the test ends.

On the other hand, when the test is completed by starting the test (S240) (S250), the control module 30 provides the test result to the display device (not shown) through the output module 40 and ends the test.

When the semiconductor memory module test is performed in this manner, the redundant test of the semiconductor memory modules 55, 65, 75, and 85 may be prevented, thereby reducing the test time. It can also help improve productivity.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

According to the semiconductor memory module test facility and test method described above, one or more of the following effects are obtained.

First, the test time of the semiconductor memory module can be shortened.

Second, it can help to increase the productivity of the semiconductor memory module by preventing duplicate testing.

Claims (9)

An input module configured to receive a plurality of management number sets of the semiconductor memory module to be tested; A first storage module for storing a plurality of management number sets of pretested semiconductor memory modules; And And a control module for comparing the input management number set with the stored management number set to determine whether to proceed with a test. The semiconductor memory module test fixture of claim 1, wherein the plurality of management number sets are semiconductor memory module management numbers, test system management numbers, test program management numbers, or a combination thereof. 3. The semiconductor memory module test fixture of claim 2, wherein the semiconductor memory module management number is stored in a second storage module located on the semiconductor memory module. 4. The semiconductor memory module test fixture of claim 3, wherein the second storage module is a Serial Presence Detect (SPD). (a) receiving a plurality of management number sets of the semiconductor memory module to be tested; (b) loading a plurality of management number sets of pretested semiconductor memory modules; And (c) comparing the input management number set with the loaded management number set to determine whether to proceed with a test. 6. The method of claim 5, wherein the plurality of management number sets are semiconductor memory module management numbers, test system management numbers, test program management numbers, or a combination thereof. The method of claim 6, wherein the semiconductor memory module management number is stored in a storage module located on the semiconductor memory module. The method of claim 5, wherein the determining of whether to proceed with the test stops the test when the input management number set and the stored management number set are the same. The method of claim 8, wherein the determining of whether to proceed with the test requires the user to decide whether to proceed with the test.

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