KR20060023427A - Nand flash memory device and error detection method detecting error during copy_back program operation - Google Patents

Abstract

The present invention relates to a NAND flash memory device and an error detection method for detecting an error during a copyback program operation. The NAND flash memory device according to the present invention includes a cell array for storing data, a page buffer for copying back the data, and an error detector for detecting an error in parallel with a copyback program operation. Here, the operation of detecting the error is terminated before the copyback program verify operation is performed. According to the present invention, an error generated during the copyback operation can be detected without additional delay time.

Description

NAND flash memory device that detects errors during copyback program operation and error detection method {NAND FLASH MEMORY DEVICE AND ERROR DETECTION METHOD DETECTING ERROR DURING COPY_BACK PROGRAM OPERATION}

1 is a block diagram illustrating a NAND flash memory device according to an exemplary embodiment of the present invention.

2 is a flowchart illustrating an error detection method of a NAND flash memory device according to the present invention.

* Description of the symbols for the main parts of the drawings *

100: NAND flash memory device 110: cell array

120: page buffer 130: column selection circuit

140, 150: parity generator 160: data input buffer

170: comparator 180: control logic

181: Status register 190: Clock generator

210: redundancy cell array 220: redundancy page buffer

The present invention relates to a NAND flash memory device, and more particularly, to a NAND flash memory device and an error detection method for detecting an error during a copyback program operation.

A NAND Flash Memory Device is a semiconductor memory device that stores data and can be read out when needed. Nonvolatile Memory that does not lose its stored data even when its power is cut off. Device).

NAND flash memory devices are made up of a large number of memory cells having a string structure. This set of memory cells is called a cell array. In a NAND flash memory device, a cell array is divided into a plurality of blocks, and each block is composed of a plurality of pages. Each page consists of a plurality of memory cells that share one word line.

NAND flash memory devices perform read and write operations in units of pages, and erase operations in units of blocks. The NAND flash memory device supports a copy_back operation in addition to read, write, and erase operations. The copyback operation is an operation of moving data stored in the first page (or source page) to the second page (or target page). In general, the copyback operation includes a copy_back read operation, a copy_back program operation, and a copy_back program verify operation.

The copyback read operation reads data stored in the source page and stores the data in the page buffer. The copyback program operation is an operation of directly reprogramming the target page without reading data stored in the page buffer to the outside. Copyback program Verify operation is to check whether data is programmed correctly in target page. Using the copyback operation, the process of reading data stored in the page buffer to the outside and loading data to the page buffer from the outside can be omitted, thereby speeding up the NAND flash memory device.

However, in the copyback operation, an error of 1 bit may occur during the copyback read operation, and an additional 1 bit error may occur during the copyback program operation and the copyback program verification operation. Therefore, there is a possibility that a 2-bit error occurs after completing the copyback operation. In a typical NAND flash memory device, the memory controller may correct only one bit of error per page. Therefore, when a 2-bit error occurs on one page by the copyback operation, error correction is impossible.

Thus, one way to prevent a 2-bit error from being generated by the copyback operation is to investigate whether an error has occurred in the data sensed from the source page to the page buffer by the copyback read operation. However, stopping the copyback operation and examining whether an error has occurred requires an additional delay time, which does not meet the tendency of the NAND flash memory device for high speed operation.

 SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems, and an object of the present invention is to provide a NAND flash memory device and an error detection method capable of detecting an error generated during a copyback operation without additional delay time.

An error detection method of a NAND flash memory device according to the present invention for achieving the above object comprises the steps of: a) reading data stored in a cell array; And b) detecting the error generated in step a) in parallel with the operation of copyback programming the read data.

In this embodiment, the time point at which the error detection ends is at least before the program verify operation is performed.

In this embodiment, before the step a), the method may further include generating a first parity with respect to the data while inputting data into the cell array. And detecting the error in step b) comprises: b1) generating a second parity from data stored in the page buffer; b2) comparing the first and second parities to generate a detection signal; And b3) storing the detection signal in a status register.

Another aspect of an error detection method of a NAND flash memory device according to the present invention includes: a) inputting data into a cell array; b) reading data stored in the cell array and storing it in a page buffer; c) in parallel with the copyback program operation, detecting an error generated in step b); And d) checking whether the error detection is completed and performing a program verify operation.

In this embodiment, the step of performing the copyback program in step c),

Generating a high voltage and setting up the bit line; Applying the high voltage to a selected word line; And performing program recovery.

In this embodiment, in step a), generating a first parity with respect to data stored in the cell array. And in step c), detecting an error comprises: c1) generating a second parity from data stored in the page buffer; c2) comparing the first and second parities to generate a detection signal; And c3) storing the detection signal in a status register. Here, the detection signal stored in the status register is output to the outside through the input / output line.

A NAND flash memory device according to the present invention includes a cell array for storing data; A page buffer for copying back the data; And an error detector for detecting an error in parallel with the copyback program operation.

In this embodiment, the NAND flash memory device according to the present invention further includes a control device for controlling the error detector such that error detection is terminated before the program verify operation is performed.

In this embodiment, the cell array stores a first parity for the data. The error detector may include a parity generator for receiving data stored in the page buffer and generating a second parity; And a comparator for comparing the first and second parities to generate a gum origin. The control device controls the parity generator and the comparator so that the detection signal is generated before the program verify operation is performed. Here, the control device includes a status register for storing the detection signal. The detection signal stored in the status register is output to the outside through an input / output line.

Another aspect of the NAND flash memory device according to the present invention includes: a cell array storing data and a first parity with respect to the data; A page buffer for copying back the data and the first parity; A first parity generator which receives data stored in the page buffer during a copyback program operation and generates a second parity in synchronization with a first clock signal; A comparator for comparing the first and second parities and generating a detection signal in synchronization with a second clock signal; And a control device for controlling the first and second clock signals so that the detection signal is generated before the program verify operation is performed.

In this embodiment, the cell array includes a main cell array and a redundant cell array; The main cell array stores the data; The redundancy cell array stores the first parity. And the page buffer includes a main page buffer and a redundancy page buffer; The main page buffer copies back data stored in the main cell array; The redundancy page buffer copies back the first parity stored in the redundancy cell array.

In this embodiment, the control device includes a state register for storing the detection signal. The detection signal stored in the status register is output to the outside via the input / output line.

In this embodiment, the NAND flash memory device according to the present invention further includes a second parity generator for generating the first parity while inputting data to the cell array.

The NAND flash memory device and the error detection method thereof according to the present invention do not require an additional time for the error detection operation because the error detection operation is performed in parallel with the copyback program operation.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

1 is a block diagram illustrating a NAND flash memory device according to an exemplary embodiment of the present invention. Referring to FIG. 1, the NAND flash memory device 100 includes a cell array 110, a page buffer 120, a column selection circuit 130, parity generators 140 and 150, a data input buffer 160, and a comparator. 170, the control logic 180, the clock generator 190, the redundancy cell array 210, and the redundancy page buffer 220.

The data input buffer 160 receives data through an input / output line IO. The data is usually input in units of 1 byte or 1 word. Here, one byte is 8 bits and one word is 16 bits. The data input buffer 150 supplies the received data to the column selection circuit 130 and the first parity generator 150.

The column selection circuit 130 transfers data provided from the data input buffer 160 to the page buffer 120 in response to the column address ADDR and the address clock signal ACLK. The column address ADDR is externally applied and decoded by a column decoder (not shown) inside the column selection circuit 130. The decoded address signal turns on a transistor in a Y_Gate Circuit (not shown) inside the column select circuit 130. The address clock signal ACLK sequentially increases column addresses by operating an address counter (not shown) inside the column select circuit 130. By such an operation, data provided from the data input buffer 160 is input to the page buffer 120 through the column selection circuit 130. Since the column decoder, the wire gate circuit, and the address counter in the column selection circuit 130 are well known to those skilled in the art, detailed description thereof will be omitted.

Meanwhile, the first parity generator 150 receives data provided from the data input buffer 160 to generate an error detection code (EDC). The error detection code generated by the first parity generator 150 is defined as a first parity. The first parity generator 150 generates a first parity having one bit of error information on one page of data input in synchronization with the parity clock signal PCLK. The first parity generator 150 supplies the generated first parity to the redundancy page buffer 220.

The page buffer 120 and the redundancy page buffer 220 temporarily store the received data and the first parity. The data and the first parity are programmed into source pages of the cell array 110 and the redundancy cell array 210, respectively, by a program operation.

Although not shown in FIG. 1, the cell array 110 is divided into a plurality of blocks, each block consisting of a plurality of pages, and each page shares a word line. It consists of a plurality of memory cells (Memory Cells). In general, each block is composed of 16, 32, or 64 pages, and each page is composed of 512 bytes or 2048 bytes of memory cells.

Data programmed in the source pages of the cell array 110 and the redundancy cell array 210 are stored in the page buffer 120 and the redundancy page buffer 220 again by a copyback read operation. In this case, an error of 1 bit may occur in the process of reading data programmed in the source page of the cell array 110.

Data stored in the page buffer 120 and the redundancy page buffer 220 are again copied to the target pages of the cell array 110 and the redundancy cell array 210 by a copyback program operation. At this time, while the data stored in the page buffer 120 is copied back to the target page, the data stored in the page buffer 120 is input to the second parity generator 140 through the column selection circuit 130. .

The second parity generator 140 generates an error detection code EDC by the same operation as that of the first parity generator 150. The error detection code generated by the second parity generator 140 is defined as a second parity. The second parity is generated in synchronization with the parity clock signal PCLK, and the generated second parity Y is provided to the comparator 170.

The comparator 170 generates a detection signal by comparing the second parity Y provided by the second parity generator 140 with the first parity X provided by the redundancy page buffer 220. If a fail has not occurred, the first parity X and the second parity Y have the same value. At this time, the comparator 170 generates a pass signal Pass in synchronization with the clock signal FCLK. However, if a fail occurs and the first parity X and the second parity Y do not coincide, the comparator 170 generates a fail signal in synchronization with the clock signal FCLK. The pass signal or fail signal is provided to the control logic 180.

The control logic 180 has a status register 181 therein. The status register 181 stores a pass signal or a fail signal provided by the comparator 170. The pass signal or fail signal stored in the status register 181 is output to the outside through the input / output line IO. On the other hand, the control logic 180 controls the overall operation of the NAND flash memory device 100, in particular the clock generator 190 so that the error detection operation (or EDC scan operation) proceeds in parallel with the copyback program operation. ).

The clock generator 190 is controlled by the control logic 180, and the address clock signal ACLK, the first and the first, for operating an address counter (not shown) in the column selection circuit 130. A parity clock signal PCLK for generating first and second parities from the two parity generators 140 and 150 and a clock signal FCLK for generating a pass signal or a fail signal from the comparator 170 are generated. .

The clock generator 190 controls the address clock signal ACLK, the parity clock signal PCLK, and the clock signal FCLK so that the EDC scan operation is terminated before the copy_back program verify operation is started. do. This is because when the data stored in the page buffer 120 is copied back to the target page, the data of the page buffer 120 is changed from "0" to "1" by a program verify operation.

The NAND flash memory device 100 according to the present invention generates a first parity when data is input and stores the first parity in the redundancy cell array 210. In order to detect an error generated during the copyback read operation, a second parity is generated and compared with the first parity. This EDC scan operation is performed in parallel with the copyback program operation to avoid additional delay time. However, the EDC scan operation is terminated before the copyback program verify operation is performed.

2 is a flowchart illustrating an error detection method of a NAND flash memory device according to an exemplary embodiment of the present invention. An error detection method of the NAND flash memory device according to the present invention will be described sequentially with reference to FIG. 2.

First, in step S110, data is input to the cell array and a first parity is generated for the data. The first parity is generated while inputting data into the cell array 110 (see FIG. 1). The data is stored in the source page of the cell array 110, and the first parity is stored in the source page of the redundancy cell array (see FIG. 1) 210.

In operation S120, the data and first parity stored in the source page of the cell array 110 and the redundancy cell array 210 are read, and the read data and the first parity are stored in the page buffer (see FIG. 1) 120 and the redundancy page. It is stored in the buffer 220 (see FIG. 1). This is called a copy_back read operation. One bit error may occur during the copyback read operation.

Next, an operation of programming data and a first parity stored in the page buffer 120 and the redundancy page buffer 220 to a target page of the cell array 110 and the redundancy cell array 210 is performed. This operation is called a copy_back program operation. In FIG. 2, the copyback program operation includes steps S130, S140, and S150.

In step S130, as a preparation for the copyback program operation, a high voltage is generated and a bit line is set up. Here, the high voltage is generated in a high voltage generating circuit (or charge pump circuit) in the NAND flash memory device as is well known, and the generated high voltage is supplied to the word line. Setting up the bit line (set_up) means applying a program voltage (for example, 0V) to the bit line.

In step S140, a copyback program is executed by applying a high voltage (for example, 15V to 20V) to the selected word line.

In step S150, after executing the copyback program, the word line and the bit line are initialized for the next operation. This is called a program recovery operation.

Referring to FIG. 2, an EDC scan operation is performed in parallel with the copyback program operation steps S130, S140, and S150. The EDC scan operation includes steps S210, S220, and S230.

In operation S210, data stored in the page buffer 120 is input in operation S120 to generate a second parity.

In step S220, the first parity stored in the redundancy page buffer 220 in step S120 is compared with the second parity generated in step S210. If the first and second parities coincide, a pass signal is generated. If the first and second parities coincide, a fail signal is generated. Here, the generation of the pass signal means that no error occurred during the copyback read operation, and the generation of the fail signal means that an error occurred during the copyback read operation.

In step S230, the pass signal or fail signal generated in step S220 is stored in the status register (see FIG. 1) 181, and the EDC scan operation is terminated. Data stored in the status register 181 is output to the outside through an input / output line.

Referring back to FIG. 2, the EDC scan operation may be terminated before or after the program recovery step S150. However, the time point for confirming whether the EDC scan operation is completed is before the program recovery step S150 ends and the program verify step S160 is performed.

In step S160, after the program recovery step S150 ends, it is determined whether the EDC scan operation S200 ends. If the EDC scan operation is completed, the next step S170 is performed. If the EDC scan operation is not completed, the check operation is repeatedly performed until the EDC scan operation is finished.

In operation S170, the data stored in the page buffer 120 is scanned to determine whether the copyback program has been performed. This scanning operation is called a program verify operation. If data stored in the page buffer 120 is programmed in the target page, the data of the page buffer 120 is changed from "0" to "1". The program verify operation checks whether data "0" exists in the page buffer 120.

In step S180, it is checked whether the program is correct. That is, it is checked whether all data stored in the page buffer 120 is changed to "1" in step S170. If the data of the page buffer 120 are all "1", the copyback operation is terminated. However, if "0" exists in the data of the page buffer 120, the next step S190 is performed.

In step S190, as a preparation step for executing the copyback program again, the word line and the bit line are set up. That is, a voltage slightly higher than the high voltage generated in step S130 is applied to the word line, and a program voltage (for example, 0V) is applied to the bit line. Then, the steps S140 to S180 are repeated.

 The error detection method of the NAND flash memory device according to the present invention ends the EDC scan operation S200 before the program verification operation S170 in which data stored in the page buffer 120 is changed is performed. This is because when the data stored in the page buffer 120 is changed, the second parity generated during the EDC scan operation S200 is changed to make the EDC scan meaningless. According to the error detection method according to the present invention, since the EDC scan operation (S200) is performed in parallel with the copyback program operations (S130, S140, S150), an error generated during the copyback read operation (S120) without additional delay time is detected. Can be detected.

On the other hand, in the detailed description of the present invention has been described with respect to specific embodiments, various modifications are of course possible without departing from the scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

As described above, according to the NAND flash memory device and the error detecting method according to the present invention, since the EDC scan is performed in parallel during the copyback program, an error generated during the copyback read operation can be detected without additional delay time.

Claims (26)

In the error detection method of the NAND flash memory device: a) reading data stored in the cell array; And b) detecting an error generated in step a) in parallel with the copyback programming of the read data. The method of claim 1, The time point at which the error detection ends is at least before the program verify operation is performed. The method of claim 1, And the data read in step a) is stored in a page buffer. The method of claim 3, wherein Prior to step a), further comprising generating a first parity for the data while inputting data to the cell array. The method of claim 4, wherein Detecting the error in step b), b1) generating a second parity from data stored in the page buffer; And b2) comparing the first and second parities to generate a detection signal. The method of claim 5, wherein b3) storing the detection signal in a status register. The method of claim 6, And a detection signal stored in the status register is output to the outside through an input / output line. In the error detection method of the NAND flash memory device: a) inputting data into the cell array; b) reading data stored in the cell array and storing it in a page buffer; c) in parallel with the copyback program operation, detecting an error generated in step b); And d) checking whether the error detection is terminated and performing a program verify operation. The method of claim 8, Performing a copyback program in step c), Generating a high voltage and setting up the bit line; Applying the high voltage to a selected word line; And An error detection method comprising performing program recovery. The method of claim 8, In step a), generating a first parity for data stored in the cell array. The method of claim 10, Detecting the error in step c), c1) generating a second parity from data stored in the page buffer; And c2) comparing the first and second parities to generate a detection signal. The method of claim 11, c3) storing the detection signal in a status register. The method of claim 12, And a detection signal stored in the status register is output to the outside through an input / output line. A cell array for storing data; A page buffer for copying back the data; And A NAND flash memory device including an error detector for detecting an error in parallel with a copyback program operation. The method of claim 14, And a controller for controlling the error detector to terminate error detection before a program verify operation is performed. The method of claim 14, And the cell array stores a first parity with respect to the data. The method of claim 16, The error detector may include a parity generator for receiving data stored in the page buffer and generating a second parity; And And a comparator for comparing the first and second parities to generate a detection signal. The method of claim 17, And a control device for controlling the parity generator and the comparator such that the detection signal is generated before a program verify operation is performed. The method of claim 18, And the control device includes a status register to store the detection signal. The method of claim 19, And a detection signal stored in the status register is output to the outside through an input / output line. A cell array storing data and a first parity for the data; A page buffer for copying back the data and the first parity; A first parity generator which receives data stored in the page buffer during a copyback program operation and generates a second parity in synchronization with a first clock signal; A comparator for comparing the first and second parities and generating a detection signal in synchronization with a second clock signal; And And a control device for controlling the first and second clock signals so that the detection signal is generated before a program verify operation is performed. The method of claim 21, The cell array includes a main cell array and a redundant cell array; The main cell array stores the data; And the redundancy cell array stores the first parity. The method of claim 22, The page buffer includes a main page buffer and a redundancy page buffer; The main page buffer copies back data stored in the main cell array; And wherein the redundancy page buffer copies back the first parity stored in the redundancy cell array. The method of claim 21, And the control device includes a status register for storing the detection signal. The method of claim 24, And a detection signal stored in the status register is externally output through an input / output line. The method of claim 21, And a second parity generator for generating the first parity while inputting data to the cell array.

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