KR20060019028A - Thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor array panel, wherein a gate line including a gate electrode, a gate insulating film, a semiconductor layer, an ohmic contact member, a data line and a drain electrode are formed on a substrate, and the exposed gate insulating film and the exposed semiconductor layer And a lower protective film of an inorganic material and an upper protective film of a photosensitive organic material are sequentially deposited on the data line and the drain electrode. Subsequently, after patterning the upper passivation layer so that the lower passivation layer is exposed, the lower passivation layer and the gate insulating layer below are etched using the upper passivation layer as a mask to expose a portion of the trench and the gate line, part of the data line, and part of the drain electrode. To form. Next, a transparent conductive film is formed to form a pixel electrode connected to the drain electrode, a contact auxiliary member connected to a part of the gate line and a part of the data line, a lower conductor formed in the trench, and a lower conductor formed in the upper protective film. The furrow has an undercut shaped sidewall and the contact hole has a sidewall of a stepped profile. For this reason, the lower conductor is disconnected from the pixel electrode and the contact auxiliary member, and the upper conductor is also disconnected from the pixel electrode and the contact assist member by this groove.

Thin Film Transistor Display Board, Slit, Mask, Undercut, Double Protection

Description

Thin film transistor array panel and manufacturing method thereof

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

2A and 2B are cross-sectional views of the thin film transistor array panel of FIG. 1 taken along lines IIa-IIa 'and IIb-IIb', respectively.

3 and 6 are layout views at intermediate stages of the method for manufacturing the thin film transistor array panel shown in FIGS. 1 to 2B according to one embodiment of the present invention, respectively, and are arranged in the order of the process.

4A and 4B are cross-sectional views of the thin film transistor array panel of FIG. 3 taken along lines IVa-IVa 'and IVb-IVb', respectively.

5A and 5B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 3 taken along the Va-Va 'line and the Vb-Vb' line, respectively, and shown in the subsequent steps of FIGS. 4A and 4B.

7A and 7B are cross-sectional views of the thin film transistor array panel of FIG. 6 taken along lines VIIa-VIIa 'and VIIb-VIIb', respectively.

8A and 8B are cross-sectional views of the thin film transistor array panel of FIG. 6 taken along lines VIIIa-VIIIa 'and VIIIb-VIIIb', respectively, and are views of the next steps of FIGS. 7A and 7B.

9A and 9B are cross-sectional views of the thin film transistor array panel of FIG. 6 taken along lines IXa-IXa 'and IXb-IXb', respectively, and are views of the next steps of FIGS. 8A and 8B.

The present invention relates to a thin film transistor array panel and a method of manufacturing the same.

A thin film transistor (TFT) is used as a circuit board for independently driving each pixel in a liquid crystal display device, an organic electroluminescence (EL) display device, or the like.

The thin film transistor array panel includes a gate line transferring a gate signal, a data line transferring a data signal, a thin film transistor connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, and the like.

The thin film transistor is a switching element that controls a data signal transmitted to a pixel electrode through a data line according to a gate signal transmitted through a gate line. The thin film transistor includes a semiconductor layer and a data line forming a channel and a gate electrode connected to the gate line. A source electrode and a drain electrode facing the source electrode are mainly formed around the semiconductor layer.

However, in order to manufacture the thin film transistor array panel, several photolithography processes are required. Each photolithography process includes a number of complex details, so the number of photolithography processes determines the time and cost of the thin film transistor array panel manufacturing process.

One technical problem to be achieved by the present invention is to simplify the manufacturing process of the thin film transistor array panel.

According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor array panel, the method including forming a gate line on a substrate, forming a gate insulating film on the gate line, and forming a semiconductor layer on the gate insulating film. Forming a resistive contact member on the semiconductor layer; forming a data line and a drain electrode on the resistive contact member; and depositing a lower passivation layer and an upper passivation layer on the data line and the drain electrode in order; Patterning a passivation layer to expose the lower passivation layer; etching the lower passivation layer to form a first contact hole exposing the drain electrode and a first furrow surrounding the first contact hole; Depositing, draining through the first contact hole Forming a pixel electrode connected to the electrode and isolated by the first groove, and a first conductor formed in the first groove and separated from the pixel electrode.

It is preferable that the sidewall of the first furrow is steeper than the sidewall of the first contact hole. The sidewall of the first furrow may have an undercut, and the sidewall of the first contact hole may have a stepped profile.

The upper protective film is preferably made of a photosensitive material.

The upper passivation layer may be formed using an optical mask having a light blocking region, a transflective region, and a transmissive region.

In this case, the transmission region includes a first transmission region corresponding to the first furrow and a second transmission region corresponding to the first contact hole, and the transflective region is disposed around the second transmission region. It is preferable.

In the forming of the first contact hole and the first furrow, the lower protective film portion corresponding to the first transmission region may be undercut below the upper protective film.

In the forming of the first contact hole and the first furrow, the lower passivation layer may be etched to form a second contact hole exposing the end portion of the first contact hole and the data line, and the upper sidewall of the first furrow and the first furrow may be formed. Forming an upper sidewall of the second furrow surrounding the second contact hole and an upper sidewall of the third contact hole above the end of the gate line and an upper sidewall of the third furrow surrounding the third contact hole; and Etching the gate insulating film to complete the first to third grooves and the third contact hole, wherein the forming of the pixel electrode and the first conductor comprises: forming the gate electrode through the second and third contact holes; A plurality of contact auxiliary members connected to an end portion of the data line and an end portion of the gate line and surrounded by the second and third grooves, and formed in the second and third grooves, respectively. And it can form an entire second view separated from the contact assistant member.

The pixel electrode and the first conductor forming step are separated by the pixel electrode, the contact auxiliary member, and the first to third grooves, and are formed on the upper passivation layer on the gate line and the data line. 3 conductors can be formed.

The sidewalls of the first to third furrows have an undercut, and the sidewalls of the first to third contact holes have a stepped profile.

The forming of the semiconductor layer and the forming of the data line and the drain electrode may include sequentially depositing a gate insulating film, an intrinsic amorphous silicon layer, an impurity amorphous silicon layer, and a data conductive layer on the gate line, and in position on the data conductive layer. Forming a photosensitive film having a different thickness, and selectively etching the data conductive layer, the impurity amorphous silicon layer, and the intrinsic amorphous silicon layer using the photosensitive film as a mask to form the photosensitive film. It may include forming a.

The photosensitive film may be formed using a photomask having a light blocking area, a transflective area, and a transmissive area.

According to another aspect of the present invention, a method of manufacturing a thin film transistor array panel includes a gate line formed on a substrate, a gate insulating film formed on the gate line, a semiconductor layer formed on the gate insulating film, and data formed on the semiconductor layer. A lower passivation layer and an upper passivation layer formed on a line and drain electrode, the data line and the drain electrode, and a pixel electrode formed on the upper passivation layer, wherein the lower passivation layer and the upper passivation layer expose the drain electrode. A first contact hole and a first furrow surrounding the pixel electrode are provided, and the pixel electrode is connected to the drain electrode through the first contact hole.

The lower passivation layer and the upper passivation layer further include a second contact hole exposing an end portion of the data line, wherein the lower passivation layer, the complementary passivation layer, and the gate insulating layer surround the second contact hole, the gate. And a third contact hole exposing an end portion of the line, and a third furrow surrounding the third contact hole, wherein the thin film transistor array panel is formed through the second and third contact holes to form an end portion of the data line and the gate line. A contact auxiliary member connected to an end portion and surrounded by the second and third grooves, and a first conductor formed in the first to third grooves and separated from the pixel electrode and the contact auxiliary member. Can be.

The thin film transistor array panel further includes a second conductor separated by the pixel electrode, the contact auxiliary member, and the first to third grooves, and formed on an upper passivation layer on the gate line and the data line. can do.

Preferably, the sidewall of the first, second or third furrow has an undercut, and the sidewall of the first, second or third contact hole has a stepped profile.                     

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity, and like reference numerals designate like parts throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Hereinafter, a thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 2B.

FIG. 1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIGS. 2A and 2B illustrate a liquid crystal display device including the thin film transistor array panel of FIG. 1, respectively, with lines IIa-IIa ′ and IIb-IIb ′. It is an example of the sectional drawing shown along the cut.

The liquid crystal display according to the exemplary embodiment of the present invention includes a thin film transistor array panel 100 and a common electrode panel 200 facing the thin film transistor array panel 100, and a liquid crystal layer interposed between the thin film transistor array panel 100 and the common electrode panel 200. Includes 3)                     

First, the thin film transistor array panel 100 will be described in detail.

As shown in FIGS. 1 and 2B, a plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on the insulating substrate 110.

The gate line 121 mainly extends in the horizontal direction and transmits a gate signal, and has a wide end portion for connection with another layer or an external device. A portion of each gate line 121 protrudes upward to form a plurality of gate electrodes 124.

The storage electrode line 131 extends mainly in the horizontal direction and receives a predetermined voltage such as a common voltage applied to a common electrode (not shown) of another display panel (not shown). It includes an extension 137 that extends up and down in width.

The gate line 121 and the storage electrode line 131 may be formed of a silver-based metal such as silver (Ag) or a silver alloy, an aluminum-based metal such as aluminum (Al) or an aluminum alloy, and a copper-based metal such as copper (Cu) or a copper alloy, or chromium. And a conductive film made of (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo), and alloys thereof. However, the gate line 121 and the storage electrode line 131 may have a multilayer film structure including two conductive films (not shown) having different physical properties. In this case, one conductive film is made of a low resistivity metal such as an aluminum-based metal, a silver-based metal, or a copper-based metal so as to reduce signal delay or voltage drop between the gate line 121 and the sustain electrode line 131. . In contrast, the other conductive film is made of a material having excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as chromium, molybdenum, titanium, tantalum or alloys thereof. Examples of the structure in which a low resistivity conductive film comes on the top and a conductive film having excellent contact properties on the bottom include a chromium bottom film and an upper film made of aluminum-neodymium (Nd) alloy, and vice versa, an aluminum-neodymium bottom film and molybdenum And an upper film.

Side surfaces of the gate line 121 and the storage electrode line 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is in the range of about 30-80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121 and the storage electrode line 131.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. The linear semiconductor 151 extends mainly in the longitudinal direction from which a plurality of projections 154 extend toward the gate electrode 124.

A plurality of linear and island ohmic contacts 161 and 165 made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration are formed on the semiconductor 151. have. The linear contact member 161 has a plurality of protrusions 163, and the protrusions 163 and the island contact members 165 are paired and positioned on the protrusions 154 of the semiconductor 151.                     

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165 are also inclined with respect to the surface of the substrate 110, and the inclination angle is 30-80 °.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165.

The data line 171 transferring the data voltage mainly extends in the vertical direction to cross the gate line 121 and has a wide end portion for connection with another layer or an external device. A plurality of branches extending from the data line 171 toward the drain electrode 175 forms a source electrode 173. Each drain electrode 175 has a wide area for connection with the other layer and has one end portion linear with one end portion 177 overlapping the extension portion 137 of the storage electrode line 131. Each source electrode 173 is bent to partially surround the other end of the drain electrode 175. The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor together with the protrusion 154 of the semiconductor 151, and a channel of the thin film transistor is a source electrode 173 and a drain electrode. It is formed in the protrusion 154 between the (175).

The data line 171 and the drain electrode 175 may be made of a refractory metal such as chromium, titanium, tantalum, molybdenum, or an alloy thereof, and may also be formed of a conductive film made of a silver metal or an aluminum metal. And other conductive films made of chromium, titanium, tantalum, molybdenum, and alloys thereof.

Sides of the data line 171 and the drain electrode 175 are also inclined, and the inclination angle is in the range of about 30-80 ° with respect to the water plane.

The ohmic contacts 161 and 165 exist only between the semiconductor 151 below and the data line 171 and the drain electrode 175 above and serve to lower the contact resistance.

The linear semiconductor 151 has substantially the same shape as the data line 171, the drain electrode 175, and the ohmic contacts 161 and 165 thereunder. However, it has a portion exposed between the source electrode 173 and the drain electrode 175, and not covered by the data line 171 and the drain electrode 175.

A lower passivation layer 180p formed of an inorganic material such as silicon nitride or silicon oxide (SiOx) is formed on the data line 171, the drain electrode 175, the exposed semiconductor 151, and the exposed gate insulating layer 140. The upper passivation layer 180q formed of a photosensitive organic material having excellent planarization characteristics is formed thereon.

The lower and upper passivation layers 180p and 180q and the gate insulating layer 140 have a region around the end portion 46 of the gate line 121 and a region around the end portion 47 of the data line 171 and the gate line 121. A plurality of grooves 41, 42, 43 are formed to surround the region 48 surrounded by the and data lines 171 in a ring shape. The furrows 41, 42, and 43 expose the substrate 110 mainly, but also the gate line 121, the data line 171, and the drain electrode 175, respectively. The furrow 43 also exposes the gate insulating layer 140 covering the storage electrode line 1231. The furrows 41, 42, and 43 have an undercut shape in which the sidewall portion under the upper passivation layer 180q is inserted.                     

In the island regions 46, 47, and 48 surrounded by the furrows 41, 42, and 43, the ends of the gate line 121 are exposed through the lower and upper passivation layers 180p and 180q and the gate insulating layer 140, respectively. A plurality of contact holes 182 penetrating through a plurality of contact holes 181, lower and upper passivation layers 180p and 180q, respectively, to expose the end portion 171 of the data line 171 and the drain electrode 175, respectively. , 185 is formed. The contact holes 181, 182, 185 have side walls of the stepped profile as opposed to the furrows 41, 42, 43.

In the island-like regions 46, 47, 48, the furrows 41, 42, 43, and the other regions 49, a transparent conductive film 80 made of ITO or IZO is formed.

The transparent conductive film 80 includes a plurality of contact auxiliary members 81 and 82 positioned on the upper passivation layer 180q of the islands 46 and 47 and a plurality of upper passivation layers 180q of the island area 48. A plurality of conductors 88 positioned in the pixel electrode 190, the grooves 41, 42, and 43, and a plurality of conductors 89 disposed on the upper passivation layer 180q of the other region 49. . When the pixel electrode 190, the contact auxiliary members 81 and 82 and the conductors 88 and 89 are disposed on the same plane, a continuous surface is formed.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 through the contact hole 185 to receive a data voltage from the drain electrode 175.

The pixel electrode 190 to which the data voltage is applied generates an electric field together with the common electrode 270 of the common electrode display panel 200 to which the common voltage is applied, thereby generating a liquid crystal layer between the two electrodes 190 and 270 ( Rearrange the liquid crystal molecules in 3).

In addition, the pixel electrode 190 and the common electrode 270 form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain the applied voltage even after the thin film transistor is turned off. Another capacitor is connected in parallel with the liquid crystal capacitor and is called a storage capacitor. The storage capacitor is formed by overlapping the pixel electrode 190 and the storage electrode line 131, and the expansion portion 137 is provided on the storage electrode line 131 to increase the capacitance of the storage capacitor, that is, the storage capacitance. do. In this case, a part 177 of the drain electrode 175 connected to the pixel electrode 190 overlaps the storage electrode line 131 with the gate insulating layer 140 interposed therebetween.

The contact auxiliary members 81 and 82 are connected to the ends of the gate lines 121 and the ends of the data lines 171 through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 complement the adhesion between the end portion of the gate line 121 and the end portion of the data line 171 and the external device, and do not necessarily serve to protect them. Whether is optional.

The conductor 89 extends along and covers the gate line 121 and the data line 171 to shield interference between the common voltage and the gate signal and the data voltage applied to the common electrode 270 of the common electrode display panel 200. It plays a role.

The pixel electrodes 190, the ohmic contacts 81 and 82, and the conductors 88 and 89 are physically separated from each other by undercuts on the sidewalls of the grooves 41 and 42. 43. On the other hand, the conductor 88 of the groove 43 around the pixel electrode 190 is connected to the exposed drain electrode 175 but not to the storage electrode line 131 covered with the gate insulating layer 140. The conductors 88 of the furrows 41 and 42 around the contact auxiliary members 81 and 82 are connected to the exposed gate line 121 part and the exposed data line 171 part, respectively.

The common electrode display panel 200 will now be described in detail.

A light blocking member 220 called a black matrix is formed on an insulating substrate 210 such as transparent glass. The light blocking member 220 serves to prevent light leakage between the pixel electrodes 190 and defines an opening area facing the pixel electrode 190.

A plurality of color filters 230 are formed on the substrate 210 and the light blocking member 220. The color filter 230 is disposed to almost enter the opening area defined by the light blocking member 220. The color filters 230 disposed between two neighboring data lines 171 and arranged in the vertical direction may be connected to each other to form a band. Each color filter 230 may represent one of three primary colors such as red, green, and blue.

An overcoat 250 made of an organic material is formed on the color filter 230 and the light blocking member 220 to protect the color filter 230 and to flatten the surface.

The common electrode 270 made of a transparent conductive material such as ITO or IZO is formed on the overcoat 250.

Next, a method of manufacturing the thin film transistor array panel illustrated in FIGS. 1 to 2B according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 to 11B and FIGS. 1 to 2B.

3 and 6 are layout views at intermediate stages of the method for manufacturing the thin film transistor array panel shown in FIGS. 1 to 2B according to one embodiment of the present invention, respectively, and are arranged in the order of the process. 4A and 4B are cross-sectional views of the thin film transistor array panel of FIG. 3 taken along lines IVa-IVa 'and IVb-IVb', respectively, and FIGS. 5A and 5B respectively illustrate the thin film transistor array panel shown in FIG. 4A and 4B are cross-sectional views taken along the lines -Va 'and Vb-Vb', and shown in the following steps. 7A and 7B are cross-sectional views of the thin film transistor array panel of FIG. 6 taken along the lines VIIa-VIIa 'and VIIb-VIIb', respectively. 8A and 8B are cross-sectional views of the thin film transistor array panel of FIG. 6 taken along the lines VIIIa-VIIIa 'and VIIIb-VIIIb', respectively, and are shown in the next steps of FIGS. 7A and 7B, and FIGS. 9A and 9B are FIGS. 6 is a cross-sectional view of the thin film transistor array panel of FIG. 6 taken along lines IXa-IXa 'and IXb-IXb', respectively, and shown in FIG. 8A and FIG. 8B next steps.

First, as shown in FIGS. 3 to 4B, a conductive layer such as a metal is deposited on the insulating substrate 110 made of transparent glass to a thickness of 1,000 kPa to 3,000 kPa by a sputtering method, and photo-etched to form a plurality of gates. The plurality of gate lines 121 including the electrodes 124 and the storage electrode lines 131 including the extension parts 137 are formed.

Next, as shown in FIGS. 5A and 5B, the gate insulating layer 140, the intrinsic amorphous silicon layer 150, and the impurity amorphous silicon layer 160 are successively laminated by chemical vapor deposition (CVD) or the like. Subsequently, a conductive layer 170 such as metal is deposited to a predetermined thickness by a sputtering method, and then a photosensitive film 50 is applied thereon to a thickness of 1 μm to 2 μm.                     

Thereafter, the photosensitive film 50 is irradiated with light through a photomask (not shown) and then developed. The thickness of the developed photoresist film varies depending on the position. In FIGS. 5A and 5B, the photoresist film 50 is composed of first to third portions whose thickness becomes smaller. The first part located in the area A (hereinafter referred to as the wiring area) and the second part located in the area B (hereinafter referred to as the channel area) are denoted by reference numerals 52 and 54, respectively, and the area C (hereinafter referred to as "other"). Reference numerals are not given to the third portion located in the region, because the third portion has a thickness of zero, so that the lower conductive layer 170 is exposed. The ratio of the thicknesses of the first portion 52 and the second portion 54 varies depending on the process conditions in the subsequent process, but the thickness of the second portion 54 is 1/2 of the thickness of the first portion 52. It is preferable to set it as the following, for example, it is good that it is 4,000 Pa or less.

As such, there may be various methods of varying the thickness of the photoresist film according to the position. The transmissive area as well as the light transmitting area and the light blocking area may be provided in the exposure mask. For example. The semi-transmissive region includes a slit pattern, a lattice pattern, or a thin film having a medium or medium transmittance. When using the slit pattern, it is preferable that the width of the slits and the interval between the slits are smaller than the resolution of the exposure machine used for the photographic process. Another example is to use a photoresist film that can be reflowed. That is, a thin portion is formed by forming a reflowable photoresist film with a conventional mask having only a transmissive area and a light shielding area, and then reflowing so that the photoresist film flows into an area where no photoresist film remains.                     

Given the appropriate process conditions, the underlying layers can be selectively etched due to the difference in thickness of the photoresist films 52 and 54. Therefore, the plurality of drain electrodes 175 including the plurality of data lines 171 including the plurality of source electrodes 173 and the extension 177 as shown in FIGS. 6 through 7B are formed through a series of etching steps. A plurality of linear ohmic contacts 161 including a plurality of protrusions 163 and a plurality of island-like ohmic contacts 165, and a plurality of linear semiconductors 151 including a plurality of protrusions 154. Form.

For convenience of description, portions of the conductor layer 170 located in the wiring region A, the impurity amorphous silicon layer 160, and the intrinsic amorphous silicon layer 150 are referred to as first portions, and the conductor layer located in the channel region B. A portion of the impurity amorphous silicon layer 160 and the intrinsic amorphous silicon layer 150 is referred to as a second portion, and the conductor layer 170 located in the other region C, the impurity amorphous silicon layer 160, and the intrinsic A part of the amorphous silicon layer 150 is called a third part.

One example of the order of forming such a structure is as follows.

(1) removing the third portion of the conductor layer 170, the impurity amorphous silicon layer 160 and the intrinsic amorphous silicon layer 150 located in the other region (C),

(2) removing the second portion 54 of the photosensitive film located in the channel region B,

(3) removing the second portion of the conductor layer 170 and the impurity amorphous silicon layer 160 located in the channel region B, and

(4) Removal of the first portion 52 of the photosensitive film located in the wiring region A. FIG.

Another example of this order is as follows.                     

(1) removing the third portion of conductor layer 170 located in other region (C),

(2) removing the second portion 54 of the photosensitive film located in the channel region B,

(3) removing the third portions of the impurity amorphous silicon layer 160 and the intrinsic amorphous silicon layer 150 located in the other region (C),

(4) removing the second portion of conductor layer 170 located in channel region B,

(5) removing the first portion 52 of the photosensitive film located in the wiring region A, and

(6) Removal of the second portion of the impurity amorphous silicon layer 160 located in the channel region B. FIG.

When the second portion 54 of the photoresist film is removed, the thickness of the first portion 52 of the photoresist film will decrease, but since the thickness of the second portion 54 of the photoresist film is thinner than the first portion 52 of the photoresist film, the lower layer The first portion 52 which prevents it from being removed or etched away is not removed.

By selecting an appropriate etching condition, the impurity amorphous silicon layer 160 and the intrinsic amorphous silicon layer 150 and the second portion 54 of the photoresist film under the third part of the photoresist film may be removed at the same time. Similarly, the portion of the impurity amorphous silicon layer 160 under the second portion 54 of the photosensitive film and the first portion 52 of the photosensitive film may be removed at the same time. If the photoresist residue remains on the surface of the conductor layer 170, it is removed through ashing.

8A and 8B, on the data line 171 and the drain electrode 175, for example, a lower passivation layer 180p that is a silicon nitride film and an upper passivation layer 180q that is a positive photosensitive organic film, for example. ) Are stacked in order, and the photomask 60 is aligned thereon.

The photomask 60 is composed of a transparent substrate 61 and an opaque light shielding layer 62 thereon, the light shielding layer 62 having a width of at least a predetermined width and a light shielding of a predetermined width or more. The light shielding area E with the layer 62, and the slit-like transflective area F whose width or spacing of the light shielding layer 62 is below a predetermined value are included.

The transmission region D1 faces the center of the end of the gate line 121, the center of the end of the data line 171, and the center of the extension 177 of the drain electrode 175, and the transmission region D2 is the gate line. A periphery of the end portion 121, a periphery of the end portion of the data line 171, and a periphery of an area surrounded by the gate line 121 and the data line 171 are encountered. The semi-transmissive region F is a first portion positioned around the transmission region D1 and a second portion facing the sustain electrode line 131 around the region surrounded by the gate line 121 and the data line 171. It includes. The light blocking region E faces the rest of the substrate 110. In this case, an interval between the slits of the first portion of the transflective region F may be greater than an interval between the slits of the second portion.

When the light is irradiated to the upper passivation layer 180q through the photomask 60 and developed, a thick portion and a thin portion remain. The thick portion corresponds to a portion facing the light shielding area E, and the thin portion is Corresponds to the part facing the transflective area (F).

9A and 9B, the lower passivation layer 180p and the gate insulating layer 140 below are etched using the remaining upper passivation layer 180q as an etch mask, and the end portion and data of the gate line 121 are etched. The contact holes 181 and 182 exposing the ends of the line 171 and the contact holes 185 exposing the drain electrode 175, and the periphery of the area surrounded by the gate line 121 and the data line 171, and the gate line. The furrows 41, 42, 43 are formed around the end of the end of the 121 and the end of the end of the data line 171.

The sidewalls of the contact holes 181, 182, and 185 have a stepped profile due to the thin portion of the upper passivation layer 180q after development, and the lower passivation layer 180p and the lower portion in the furrows 41, 42, and 43. The gate insulating layer 140 is cut into the upper passivation layer 180q. However, the portion of the gate insulating layer 140 on the storage electrode line 131 in the furrow 43 is not removed due to the thin portion of the upper passivation layer 180q.

Subsequently, an IZO or ITO or a-ITO film is sputtered on the substrate 110 to form a transparent conductive film 80 on the upper passivation layer 180q, the contact holes 181, 182, and 185 and the trenches 41, 42 and 43. . At this time, since the undercut exists in the sidewalls of the furrows 41, 42, and 43, the conductors 88 falling into the furrows 41, 42, and 43 are separated from other portions, but the sidewalls of the contact holes 181, 182, and 185 are separated. Has a stepped profile, so that the conductive film 80 is not broken in the contact holes 181, 182, and 185. At this time, when the thickness of the lower passivation layer 180p is, for example, about 3000 or more to increase the degree of undercut, the conductors 88 and 89 can be more easily separated.

As a result, a plurality of portions of the transparent conductive layer 80 on the upper passivation layer 180q isolated by the furrows 41, 42, and 43 are connected to the gate line 121, the data line 171, and the drain electrode 175, respectively. Contact auxiliary members 81 and 82 form a plurality of pixel electrodes 190 (see FIGS. 1 and 2A and 2B).

Meanwhile, the upper passivation layer 180q may be formed of a material having a negative photoresist characteristic rather than positive. In this case, the side surface of the upper passivation layer 180q may have a reverse taper structure, which may further deepen the undercut.

In the present exemplary embodiment, the data line 171, the drain electrode 175, the ohmic contacts 161 and 165 and the semiconductor 151 under the same are formed in one photo process, and the pixel electrode 190 and the contact auxiliary member are formed. A separate photographic step for forming (81, 82) is omitted to simplify the overall process.

In addition, since a separate process of patterning the transparent conductive film 80 is not necessary, manufacturing time and manufacturing cost are greatly reduced.

As described above, according to the present invention, the entire process may be simplified by omitting a separate photolithography process for forming the pixel electrode by simultaneously forming the contact hole and the pixel electrode connecting the drain electrode and the pixel electrode. Therefore, manufacturing time and cost of the thin film transistor array panel can be reduced.

Since a separate process of patterning the transparent conductive film is not necessary, manufacturing time and manufacturing cost are greatly reduced.

Moreover, the interference between the common voltage applied to the common electrode, the gate signal, and the data voltage is shielded by the conductive film covering the gate line and the data line, so that the image quality deterioration due to the change of the gate signal or the data voltage is reduced.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (18)

Forming a gate line on the substrate, Forming a gate insulating film on the gate line; Forming a semiconductor layer on the gate insulating film, Forming an ohmic contact on the semiconductor layer, Forming a data line and a drain electrode on the ohmic contact member; Sequentially depositing a lower passivation layer and an upper passivation layer on the data line and the drain electrode; Patterning the upper passivation layer to expose the lower passivation layer; Etching the lower passivation layer to form a first contact hole exposing the drain electrode and a first furrow surrounding the first contact hole, and Depositing the conductive layer on the entire surface to form a pixel electrode isolated through the first contact hole, the pixel electrode isolated by the first groove, and a first conductor formed in the first groove and separated from the pixel electrode. Forming steps Method of manufacturing a thin film transistor array panel comprising a. In claim 1, And a sidewall of the first furrow is inclined more rapidly than the sidewall of the first contact hole.       In claim 2, And a sidewall of the first groove has an undercut.       The method of claim 2 or 3, And a sidewall of the first contact hole has a stepped profile. In claim 1, And the upper passivation layer is formed of a photosensitive material. In claim 5, The upper passivation layer is formed using a photomask having a light blocking region, a transflective region, and a transmissive region. In claim 6, The transmission region includes a first transmission region corresponding to the first furrow and a second transmission region corresponding to the first contact hole, And the transflective region is arranged around the second transmissive region. In claim 7, The forming of the first contact hole and the first furrow may undercut the lower passivation layer portion corresponding to the first transmission region under the upper passivation layer.       In claim 1, The first contact hole and the first groove forming step, The lower passivation layer is etched to form a second contact hole exposing the first contact hole and the end portion of the data line, and an upper sidewall of the second furrow surrounding the upper sidewall of the first furrow and the second contact hole. And forming an upper sidewall of a third contact hole over an end of the gate line and an upper sidewall of a third furrow surrounding the third contact hole; and Etching the gate insulating film to complete the first to third grooves and the third contact hole Including, In the forming of the pixel electrode and the first conductor, a plurality of contact assistants connected to the end of the data line and the end of the gate line through the second and third contact holes, respectively, are surrounded by the second and third grooves. Forming a member and a second conductor formed in the second and third furrows and separated from the contact assist member. Method of manufacturing a thin film transistor array panel. In claim 9, The pixel electrode and the first conductor forming step are separated by the pixel electrode, the contact auxiliary member, and the first to third grooves, and are formed on the upper passivation layer on the gate line and the data line. 3 Manufacturing method of thin film transistor array panel which forms conductor.  In claim 9, The sidewalls of the first to third grooves have an undercut, and the sidewalls of the first to third contact holes have a stepped profile. In claim 1, The semiconductor layer forming step, the data line and the drain electrode forming step, Depositing a gate insulating film, an intrinsic amorphous silicon layer, an impurity amorphous silicon layer, and a data conductive layer in order on the gate line; Forming a photosensitive film having a different thickness depending on a position on the data conductive layer; and Selectively etching the data conductive layer, the impurity amorphous silicon layer and the intrinsic amorphous silicon layer using the photosensitive film as a mask to form the data line, the drain electrode, and the ohmic contact member Containing Method of manufacturing a thin film transistor array panel. In claim 12, And the photosensitive film is formed using a photomask having a light blocking region, a transflective region, and a transmissive region. A gate line formed on the substrate, A gate insulating film formed on the gate line, A semiconductor layer formed on the gate insulating film, A data line and a drain electrode formed on the semiconductor layer; A lower passivation layer and an upper passivation layer formed on the data line and the drain electrode; A pixel electrode formed on the upper passivation layer Including, The lower passivation layer and the upper passivation layer include a first contact hole exposing the drain electrode and a first furrow surrounding the pixel electrode. The pixel electrode is connected to the drain electrode through the first contact hole. Thin film transistor array panel. The method of claim 14, The lower passivation layer and the upper passivation layer, A second contact hole exposing an end portion of the data line More, The lower passivation layer, the complementary passivation layer, and the gate insulation layer may include A second furrow surrounding the second contact hole, A third contact hole exposing an end portion of the gate line, and A third furrow enclosing the third contact hole And The thin film transistor array panel is connected to an end portion of the data line and an end portion of the gate line through the second and third contact holes, respectively, and is surrounded by the second and third grooves, and the first to third grooves. And a first conductor formed at the first electrode and separated from the pixel electrode and the contact auxiliary member. Thin film transistor array panel. The method of claim 15, The thin film transistor array panel further includes a second conductor separated by the pixel electrode, the contact auxiliary member, and the first to third grooves, and formed on an upper passivation layer on the gate line and the data line. Thin film transistor array panel.       The method according to any one of claims 14 to 16, The sidewalls of the first, second or third furrows have an undercut.       The method of claim 17, The sidewalls of the first, second or third contact holes have a stepped profile.

Images