KR20050121811A - Method of fabricating of an array substrate for liquid crystal display device - Google Patents

Abstract

The present invention relates to a drive circuit-integrated liquid crystal display device array substrate using a polycrystalline silicon thin film transistor as a drive element and a switching element, and a method of manufacturing the same.

The present invention is characterized in that the fabrication of the array substrate for the liquid crystal display device integrated with the driving circuit can be made by the six mask process, which was produced by the nine mask process.

In this case, in reducing the mask during the n-impurity doping and forming the storage capacitor, the storage wiring may be formed in a process of forming a gate electrode, and the storage electrode may be formed in a process of forming a source and a drain electrode to reduce a mask. .

In addition, the mask may be reduced by using a lift off method when forming the pixel electrode.

Therefore, there is an advantage that can reduce the process cost while reducing the process time by simplifying the process.

In addition, by simplifying the process, there is an advantage that can reduce the probability of failure during the process.

Description

Method of fabricating an array substrate for liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a method of manufacturing an array substrate for a liquid crystal display device including a driving circuit including a polycrystalline silicon thin film transistor.

In general, a liquid crystal display device injects a liquid crystal between an array substrate including a thin film transistor (TFT) and a color filter substrate, and displays an image by using a difference in refractive index of light due to the anisotropy of the liquid crystal. It is a display device.

Currently, an active matrix liquid crystal display (AM-LCD) in which the thin film transistor and the pixel electrode are arranged in a matrix manner has been attracting the most attention because of its excellent resolution and video performance. Hydrogenated amorphous silicon (a-Si: H) is mainly used because it is possible to use low-temperature insulating substrates because of low temperature processing.

However, since hydrogenated amorphous silicon has a disordered atomic arrangement, weak Si-Si bonds and dangling bonds exist, and thus, they are changed to a quasi-stable state when irradiated with light or applied with an electric field, and used as a thin film transistor device. It is difficult to use as a driving circuit due to poor stability and low electrical characteristics (low field effect mobility: 0.1 to 1.0 cm2 / V · s).

On the other hand, since polysilicon has a higher field effect mobility than amorphous silicon, a driving circuit can be made on a substrate.If the driving circuit is directly made on a substrate using polysilicon, the mounting becomes very simple and the liquid crystal panel is more compact. There is an advantage that can be produced.

1 is a schematic view of an array substrate for a liquid crystal display device integrated with a general driving circuit unit.

As illustrated, the insulating substrate 10 may be largely defined as a display unit D1 and a non-display unit D2, and a plurality of pixels P are arranged in a matrix form on the display unit D1, and a switching element for each pixel. T and the pixel electrode 78 connected thereto are configured.

In addition, a gate line GL extending along one side of the pixel P and a data line DL perpendicular to the gate line GL are formed.

The non-display part D2 includes driving circuit parts DP and GP, and the driving circuit parts DP and GP are located on one side of the substrate 10 to apply a signal to the gate line GL. GP and a data driving circuit part DP positioned on the other side of the substrate 10 that is not parallel thereto and applying a signal to the data line DL.

In addition, the gate and data driving circuit units GP and DP are connected to an external signal input terminal OL.

The gate and data driving circuit units GP and DP control an internal signal input through the external signal input terminal OL therein and control the display to the pixel unit P through the gate and data lines GL and DL, respectively. Apparatus for supplying signals and data signals.

Accordingly, the gate and data driver circuits GP and DP are configured as thin film transistors having a complementary metal-oxide semiconductor (CMOS) structure that is an inverter to properly output an input signal.

The CMOS is a semiconductor technology used in a thin film transistor for driving circuits requiring high-speed signal processing. The CMOS uses extra electrons (n-type semiconductor) and negatively charged holes (p-type semiconductor) charged with negative electricity. It is used as a complementary method for forming a conductor and forming a current gate by effective electrical control of the two kinds of semiconductors.

In the related art, a polycrystalline thin film transistor is used as the CMOS device and the switching device.

2 is an enlarged plan view illustrating a configuration of a single pixel of a conventional array substrate including a polycrystalline thin film transistor.

As illustrated, a gate line GL extending in one direction on the substrate 10 and a data line DL defining a pixel region P by crossing each other perpendicularly.

At the intersection of the gate line GL and the data line DL, an active layer 18 formed of polysilicon, a gate electrode 34 formed on the active layer 18, and the active layer 18 The thin film transistor T including the source electrode 70 and the drain electrode 72 in contact with each other is configured.

In the pixel region P, a pixel electrode 78 in contact with the drain electrode 72 is formed.

In addition, a storage capacitor C _ST is formed in the pixel region P. The storage wiring 36 that intersects the pixel region P is used as a second electrode, and is disposed below the second electrode and doped with impurities. The used polycrystalline pattern 20 as a first electrode.

3A and 3B, the cross-sectional structure of the above-described CMOS element of the driving circuit unit and the cross-sectional structure of the pixel region including the switching element will be described.

FIG. 3A is a cross-sectional view illustrating a CMOS structure thin film transistor, and FIG. 3B is a cross-sectional view of a pixel region including a switching element, taken along line II-II of FIG. 2.

As shown in FIGS. 3A and 3B, a buffer layer 12 is formed on the insulating substrate 10, and the driving circuit regions A and B and the switching region C of the substrate 10 are formed. A CMOS device (a combination of an n-type thin film transistor and a p-type thin film transistor) and an n-type thin film transistor are positioned, and in the pixel region P, a pixel electrode 78 and a storage capacitor C _ST contacting the n-type thin film transistor are disposed. It is composed.

The cross-sectional structure of each area described above will be described below.

As illustrated, the first active pattern 14, the second active pattern 16, and the third active pattern 18 are formed in each of the regions A, B, and C on the buffer layer 12.

The first and third active patterns 14, 16, and 18 are patterns of polysilicon layers, and each of the first and third active patterns 14, 16, and 18 may be defined as a first active region V1 and a second active region V2.

In this case, the third active pattern 18 includes an extension part 20 extending to the pixel area P. FIG.

A gate insulating layer 22 is disposed on an entire surface of the substrate 10 including the first to third active patterns 14, 16, and 18, and each of the active patterns 14, 16, and 18 is disposed on the gate insulating layer 28. The first, second, and third gate electrodes 30, 32, and 34 are respectively configured to correspond to the first active region V1 of.

At the same time, the storage wiring 36 crossing the pixel region P is formed.

The storage wiring 36 is positioned above the extension 20 of the third active pattern 18. At this time, the storage wiring 36 is the first electrode, and the storage wiring 36 is removed. The storage capacitor C _ST which uses two electrodes is comprised.

An interlayer insulating film 48 is formed on the entire surface of the substrate 10 including the first to third gate electrodes 30, 32, 34 and the storage wiring 36, and the interlayer insulating film 48 and a gate below the interlayer insulating film 48 are formed. First source and drain electrodes 62 and 64 and second source and drain contacts the second active regions V2 of the active patterns 14, 16, and 18 exposed by etching the insulating layer 28. Electrodes 66 and 68 and third source and drain electrodes 70 and 72 are configured.

In the above-described configuration, the first active pattern of the driving circuit regions A and B, the switching region C, and the second active region V2 of the third active patterns 14 and 18 are connected to the gate electrodes 30 and 34. N-ions doped LDD (Lightly Doped Drain) region (F) adjacent to both sides and the region except the LDD region is composed of an ohmic contact region doped with n + ions.

The LDD region F is configured to disperse hot carriers. Since the LDD region has a low doping concentration, the LDD region F prevents an increase in the leakage current I _off , thereby preventing the increase of the on-state current. It prevents the loss.

In the pixel region P, a pixel electrode 78 connected to the drain electrode 72 of the switching region C is formed.

The n-type thin film transistors in the switching region C and the n-type and p-type thin film transistors constituting the CMOS elements in the driving circuit regions A and B are constructed in the same process on a single substrate.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device including a driving circuit according to the related art including the aforementioned polycrystalline silicon thin film transistor will be described.

4A and 4B are cross-sectional views illustrating a first mask process, FIGS. 5A and 5B are cross-sectional views illustrating a second mask process, and FIGS. 6A and 6B are views illustrating a third mask process, and FIGS. 7A and 7B. 8A and 8B are cross-sectional views illustrating a fifth mask process, FIGS. 9A and 9B show a sixth mask process, and FIGS. 10A and 10B show a seventh mask process. 11A and 11B are views illustrating an eighth mask process, and FIGS. 12A and 12B are cross-sectional views illustrating a ninth mask process.

(At this time, 4b, 5b, 6b, 7b, 8b, 9b, 10b, 11b, and 12b are cross-sectional views taken along the line II-II of FIG. 2.)

As shown in the drawing, a pixel region including driving circuit regions A and B consisting of N regions A and P regions B, a switching region C, and a storage region ST is formed on the substrate 10. P) is defined and silicon oxide (SiO ₂ ) is deposited to form the buffer layer 12.

The first active pattern 14 and the second active patterned by the first mask process on the driving circuit regions (N region A, P region B) and the switching region C on the buffer layer 12. The pattern 16 and the third active pattern 18 are formed.

The first to third active patterns 14, 16, and 18 are formed of polycrystalline silicon layers, and for convenience, each pattern includes a second active region located at both sides of the first active region V1 and the first active region V1. It is defined as (V2).

In addition, the LDD region F is defined at both sides of the first active region V1 of the N region and the switching regions A and C. FIG.

In this case, the third active pattern 18 includes an extension part 20 extending to the storage area ST.

5A and 5B illustrate a second mask process step, wherein a photoresist is applied to the entire surface of the substrate 10 on which the active patterns 14, 16, and 18 are formed. By patterning the first, second, and third photosensitive patterns 22, 24, and 26 covering the first to third active patterns 14, 16, and 18 of the driving regions A and B and the switching region C, respectively. ). In this case, the extension of the third active pattern 18, that is, the polycrystalline silicon pattern 20, is exposed.

Next, a process of doping n + or p + impurity ions to the exposed surface of the polycrystalline silicon pattern 20 is performed.

The polycrystalline silicon pattern 20 doped with impurities may serve as a first electrode of the storage capacitor.

6A and 6B are cross-sectional views illustrating a third mask process. As illustrated, silicon nitride (SiN _X ) and oxide of the substrate 10 having the first to third active patterns 14, 16, and 18 are formed. A gate insulating film 28 is formed by depositing one selected from the group of inorganic insulating materials including silicon (SiO ₂ ).

Aluminum (Al) and aluminum alloy (AlNd) are deposited on the entire surface of the substrate 10 on which the gate insulating layer 28 is formed, and patterned using a third mask process to form the first to third active patterns 14, 16, and 18. Gate electrodes 30, 32, and 34 are formed respectively corresponding to the first active regions V1 of the "

At the same time, the storage wiring 36 is formed on the storage region ST in the pixel region P, that is, on the polycrystalline silicon pattern 20 doped with the impurity ions.

In this case, a storage capacitor C _ST having the polycrystalline silicon pattern 20 as the first electrode and the upper storage wiring 36 as the second electrode is configured.

Next, a process of doping n-ion (low concentration n-type impurity ion doping) is performed on the entire surface of the substrate 10 on which the gate electrodes 30, 32, and 34 are formed.

In the above-described doping process, the surfaces of the first to third active patterns 14, 16, and 18 exposed to the periphery of the gate electrodes 30, 32, and 34 are doped with n-ions.

7A and 7B illustrate a fourth mask process, wherein a photoresist is formed on the entire surface of the substrate 10 subjected to n-ion doping on the exposed surfaces of the first to third active patterns 14, 16, and 18. (photoresist) and then patterned by a fourth mask process to cover the first photoresist pattern 38, which covers the LDD region F defined in the N region A of the driving regions A and B, and P The second photoresist pattern 40 covering the region B and the third photoresist pattern 42 covering the LDD region F of the switching region C are formed.

At this time, the second active regions V2 of the first and third active patterns 14 and 18 of the N region A and the switching region C are exposed.

Next, a process of doping n + ions (high concentration n-type ions) is performed on the entire surface of the substrate 10 on which the photosensitive patterns 38, 40, and 42 are formed.

In this case, n + ions are doped on the exposed active pattern 14 of the N region A and the exposed active pattern 18 of the switching region C, and this portion is an ohmic contact layer. function as a contact layer.

Next, a process of removing the first to third photoresist patterns 38, 40, and 42 is performed.

8A and 8B illustrate a fifth mask process. As shown in FIG. 8A and FIG. 8B, a photoresist is applied to the entire surface of the substrate 10 subjected to the process of doping the n + impurity ions, and then patterned using a fifth mask process. The first photoresist pattern 44 and the second photoresist pattern 46 covering the N region A and the switching region C are formed.

Next, a process of doping p + impurity ions (high concentration p + impurity ions) is performed on the entire surface of the substrate 10 on which the first and second photoresist patterns 44 and 46 are formed. The surface of the exposed second active pattern 16 (in detail, the second active region) is doped with p + ions.

The region doped with p + ions also serves as an ohmic contact layer.

9A and 9B are diagrams illustrating a sixth mask process. As illustrated, silicon oxide (SiO ₂ ) is deposited on the entire surface of the substrate 10 subjected to the p + ion doping process, and the interlayer insulating film 48 is illustrated. The first contact hole 50 and the second contact hole exposing the second active region (the region doped with V 2, n + ions) of the N-type region A are formed by patterning by a sixth mask process. 52 and a third contact hole 54 and a fourth contact hole 56 exposing the second active region V2 (p + ion doped region) of the P-type region B, The fifth contact hole 58 and the sixth contact hole 60 exposing the second active region V2 (the region doped with n + ions) of the switching region C are formed.

10A and 10B illustrate a seventh mask process, and as shown in FIG. 10A, a selected one of the conductive metal groups as described above is deposited on the entire surface of the substrate 10 on which the interlayer insulating layer 48 is formed. Patterned in a seven-mask process, the source electrode 62, 66, 70 and the drain electrode 64 in contact with each of the exposed second active regions V2 of the first to third active patterns 14, 16 and 18. , 68,72).

11A and 11B illustrate an eighth mask process, and as shown, an inorganic insulating material on the entire surface of the substrate 10 on which the source and drain electrodes 62, 66, 70/64, 68, and 72 are formed. Is deposited to form a protective film 74.

Next, the passivation layer 74 is patterned by an eighth mask process to form a drain contact hole 76 exposing the drain electrode 72 of the switching region C.

12A and 12B illustrate a ninth mask process. Indium-tin-oxide (ITO) is deposited and patterned on the entire surface of the substrate 10 on which the passivation layer 74 is formed to expose the exposed drain electrode 72. ) And the pixel electrode 78 positioned in the pixel region P is formed.

Through the above-described process, a conventional array substrate for a liquid crystal display device including a CMOS element and a switching element composed of a polycrystalline thin film transistor in a driving region and a switching region can be manufactured.

However, the manufacturing method of the array substrate for a liquid crystal display device according to the related art belongs to a very large number of processes, and when such a large number of processes increases, the probability of defects in manufacturing a liquid crystal display device is increased, and process time delay and process cost are increased. It becomes a problem to increase the yield of the product.

In addition, since an inorganic insulating film having a high dielectric constant is used as the protective film, the pixel electrode cannot be formed to overlap with the gate wiring and data wiring.

Therefore, the parasitic capacitance does not occur between the pixel electrode, the gate wiring, and the data wiring only when the pixel electrode, the gate wiring, and the data wiring are spaced apart from each other.

Therefore, there is a problem that the opening area is encroached as much as the spaced area and the opening rate is lowered.

An object of the present invention is to solve the above problems, and proposes a method of fabricating an array substrate by reducing the mask process using a conventional 9 mask process using a six mask process.

The first object of the present invention is to reduce the number of processes to significantly reduce the probability of failure, reduce the process time and reduce the process cost.

In addition, it is a second object to enable a high opening ratio structure by using an organic film as a protective film positioned below the transparent pixel electrode.

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a liquid crystal display device, the method comprising: defining a substrate as a pixel region including a switching region and a storage region, and a driving region; A first mask process step of forming first and second active patterns in the driving region and a third active pattern in the switching region; First, second and third gate electrodes, respectively, on the upper portion of the first, second and third active patterns, the storage wirings in the storage region, and the first and second gate electrodes on the gate electrodes. A second mask process step of forming a fourth photosensitive pattern on the first, second and third photosensitive patterns and the storage wiring; Dry etching the first, second, and third photosensitive patterns to expose the gate electrodes around the respective photosensitive patterns; Doping n + ions onto surfaces of the first to third photosensitive patterns corresponding to the periphery of the gate electrode; Etching the exposed gate electrode and doping n-ions to the surfaces of the first and third active patterns corresponding to the portions where the gate electrode is etched; A third mask process step of forming a photosensitive pattern covering a region other than the second active pattern of the driving region; Doping p + ions to the surface of the second active pattern corresponding to the periphery of the second gate electrode; Forming a first interlayer insulating film on the entire surface of the first to third gate electrodes and the substrate on which the storage wirings are formed, and patterning the first and third gate electrodes to expose both sides of the first to third active patterns, and to expose the storage wirings. A fourth mask process step; A fifth mask process step of forming first to third source and drain electrodes in contact with both sides of the exposed first to third active patterns, and a metal pattern in contact with the storage wiring; A protective film is stacked and patterned on top of the second interlayer insulating film and the second interlayer insulating film on the entire surface of the substrate on which the first to third source and drain electrodes are formed, to expose the drain electrode of the switching area and to the storage area. And etching a portion of the corresponding passivation layer and the interlayer insulating layer, and forming a pixel electrode positioned in the pixel region while being in contact with the exposed drain electrode.

The second interlayer insulating film is formed by stacking a silicon oxide film (SiO ₂ film) and a silicon nitride film (SiO _N film).

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device with integrated driving circuit according to an embodiment of the present invention will be described.

Example

Hereinafter, a configuration of an array substrate for a polycrystalline liquid crystal display device according to the present invention will be described with reference to the drawings.

13 is an enlarged plan view of one pixel of an array substrate for a polycrystalline liquid crystal display according to the present invention.

As illustrated, the gate line GL extending in one direction on the substrate 100 and the data line DL defining the pixel region P by perpendicularly crossing the gate line GL.

At the intersection of the gate line GL and the data line DL, an active layer (active pattern) 108 formed of polysilicon, a gate electrode 116 formed on the active layer 108, and the active layer ( A thin film transistor T including a source electrode 132a and a drain electrode 132b in contact with 108 is configured.

The pixel region P includes a transparent pixel electrode 148 in contact with the drain electrode 132b.

In addition, a storage capacitor C _ST is formed in the pixel region P. An island-shaped metal pattern 134 contacting the storage wiring 118 crossing the pixel region P is used as the first electrode. A part of the pixel electrode 148 formed above the first electrode is used as the second electrode.

In this case, the island-shaped metal pattern 134 is formed in the process of forming the source and drain electrodes 132a and 132b.

Hereinafter, a method of manufacturing an array substrate for a liquid crystal display device including a driving circuit according to the present invention will be described with reference to the above-described plan view.

14A and 14B are cross-sectional views illustrating a first mask process, and FIGS. 15A and 17B are cross-sectional views illustrating a second mask process, and FIGS. 18A and 18B illustrate a third mask process. 19A and 19B are cross-sectional views illustrating a fourth mask process, FIGS. 20A and 20B are cross-sectional views illustrating a fifth mask process, and FIGS. 21A and 21B to 28A and FIG. It is a figure which shows the 6th mask process.

14B to 28B are cross-sectional views taken along the line VIII-VIII of FIG. 13.

14A and 14B are diagrams illustrating a first mask process, and drive circuit regions A and B, a switching region C, and storage, each of which includes N regions A and P regions B, on a substrate 100. The pixel region P including the region ST is defined, and a silicon insulating material (silicon nitride (SiN _X ) or silicon oxide (SiO ₂ )) is deposited to form a buffer layer 102.

The first active pattern 104 and the second active patterned by the first mask process on the driving circuit regions (N region B, P region C) and the switching region C on the buffer layer 102. The pattern 106 and the third active pattern 108 are formed.

The first to third active patterns 104, 106 and 108 are formed of polycrystalline silicon, and for convenience, each pattern is defined as a second active region V2 positioned at both sides of the first active region V1 and the first active region V1. do.

In addition, the LDD region F is defined at both sides of the N region A of the driving region and the first active region V1 of the switching region C.

15 (a, b) to 17 (a, b) show a second mask process, and b in each drawing is a cross-sectional view taken along the line VIII-V of FIG.

As shown in FIGS. 15A and 15B, one selected from the group of inorganic insulating materials including silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) is formed on the entire surface of the substrate 100 on which the active patterns 104, 106, and 108 are formed. The vapor deposition is performed to form the gate insulating layer 110.

A conductive metal including aluminum (Al), aluminum alloy (AlNd), copper (Cu), molybdenum (Mo), tungsten (W), and chromium (Cr) on the entire surface of the substrate 100 on which the gate insulating layer 110 is formed. One selected from the group is deposited and patterned by a second mask process to form gate electrodes 112, 114, and 116, respectively, corresponding to the first active regions V1 of the first to third active patterns 104, 106, and 108.

At the same time, the storage wiring 118 extending in one direction is formed in the pixel region P. FIG.

At this time, although not shown, a gate wiring (GL in FIG. 13) in contact with the gate electrode is formed.

The first to fourth photosensitive patterns 120a, 120b, 120c, and 120d formed to pattern them are left on the gate electrodes 112, 114, and 116 of the regions A, B, and C and the storage wiring 118. .

In this case, the gate electrodes 112 and 116 are formed to correspond to the N region A of the driving circuit regions A and B and the LDD region F of the switching region C.

As shown in FIGS. 16A and 16B, a process of dry etching (ashing) ashing the first to fourth photosensitive patterns 120a, 120b, 120c and 120d is performed.

In this case, the ashing process may include the gate electrodes 112 and 116 corresponding to the N region of the driving circuit region and the LDD region F of the switching region A and C, respectively, around the first and third photosensitive patterns 120a and 120c. Proceed to the extent of exposure.

At this time, the periphery of the gate electrodes 114 and 118 and the storage wiring formed under the second and fourth photosensitive patterns 120b and 120d are also exposed.

Subsequently, a process of doping n + impurities to the entire surface of the substrate 100 is performed while leaving the first to fourth photosensitive patterns 120a, 120b, 120c, and 120d.

At this time, n + impurity is doped to both the driving circuit region and the second active region V2 of the switching regions A, B, and C.

As shown in FIGS. 17A and 17B, the gate electrodes 112, 114, and 116 exposed under the first to third photosensitive patterns 120a, 120b, and 120c and the lower portion of the fourth photosensitive pattern 120d are exposed. A process of removing the exposed portion of the storage wiring 118 is performed.

In this case, when the gate electrodes 110, 112, 114, and 116 of the exposed portion are removed, in particular, the LDD region F of the N region A and the switching region C is exposed.

Next, when the n- impurity is doped on the entire surface of the substrate 100 where the LDD region F of each region is exposed, n-impurity is doped in the LDD region F.

Finally, before the second active region V2, the N region A and the switching region C are doped with n + impurities in the process, and n-impurities are doped in the LDD region F.

Next, a process of removing the remaining first to fourth photosensitive patterns 120a, 120b, 120c, and 120d is performed.

18A and 18B illustrate a third mask process, after depositing a photoresist on the entire surface of the substrate 100 and patterning the third mask process, the P region B is formed. The photosensitive pattern 122 is formed in all regions except for the above.

Subsequently, a process of doping p + impurities is performed on the entire surface of the substrate 100 on which the photosensitive pattern 122 is formed.

In this case, p + impurities are doped into the second active region V2 of the second active pattern 106 formed in the P region B. FIG. In this case, since the n + impurity is already doped in the second active region, the p + ion is doped with a concentration greater than that of the n + impurity to have a p-type characteristic of the second active pattern 106.

When the doping process is completed, a process of removing the photosensitive pattern 122 is performed.

19A and 19B illustrate a fourth mask process. After completion of the doping process, silicon nitride (SiN _X ) and silicon oxide (SiO ₂ ) are formed on the entire surface of the substrate 100 on which the gate electrodes 110, 112, 114, and 116 are formed. The first interlayer insulating layer 124 is formed by depositing one or more materials selected from the group of inorganic insulating materials including a.

The interlayer insulating layer 124 is patterned by a fourth mask process, so that both sides of the first to third active patterns 102, 104, and 106 formed in the N region A, the P region B, and the switching region C are active. The first contact hole 126a, the second contact hole 126b, the third contact hole 126c, the fourth contact hole 126d, the fifth contact hole 126e, and the sixth contact exposing the region V2. The seventh contact hole 126g exposing the hole 126f and the storage wiring 118 corresponding to the pixel area P is formed.

20A and 20B illustrate a fifth mask process, in which chromium (Cr), molybdenum (Mo), tungsten (W), and aluminum alloy (AlNd) are formed on the entire surface of the substrate 100 on which the interlayer insulating layer 124 is formed. And depositing and patterning a selected one of the conductive metal groups including the first and second conductive metal groups including the first and second drain electrodes 128b and 128b in contact with the first active pattern 104 of the P region A. FIG. In addition, a second source electrode 130a and a second drain electrode 130b are formed to contact the second active pattern 106 of the N region A. FIG.

At the same time, the third source electrode 132a and the third drain electrode 132b contacting the third active pattern 108 of the switching region C, and the island-shaped metal pattern contacting the storage wiring 118. 134 is formed.

At this time, although not shown, a data line (DL in FIG. 13) is formed to contact the source electrode 132a corresponding to the switching region C. Referring to FIG.

21 (a, b) to 28 (a, b) show a sixth mask process, in which b is a cross-sectional view taken along the line VII-VII of FIG. 13.

As shown in FIGS. 21A and 21B, silicon oxide (I) may be formed on the entire surface of the substrate 100 on which the source and drain electrodes 128a, 130a, 132a / 128b, 130b, and 132b and the island-shaped metal pattern 134 are formed. A second interlayer insulating film 136 is formed by stacking an oxide film layer D1 on which SiO ₂ ) is deposited and a nitride film layer D2 on which silicon nitride (SiN _X ) is deposited.

   Next, in order to remove defects on the surfaces of the active patterns 104, 106 and 108 doped with impurities, a process of hydrogenating the substrate 100 on which the nitride layer D2 is formed is performed.

In this case, it is common to form a silicon nitride film (D2) containing hydrogen in the uppermost layer of the substrate 100 before the hydrogenation process, and when the thickness of the nitride film becomes thick, the parasitic cap capacity between the upper and lower electrodes increases, so as to reduce the above-mentioned. The silicon oxide film D1 having a lower dielectric constant is formed below the silicon nitride film.

Subsequently, a protective film 137 is formed of an organic insulating film on the entire surface of the substrate 100 on which the second interlayer insulating film 136 on which the hydrogenation process is performed is formed.

The organic insulating layer may be formed by coating one or more materials selected from the group of organic insulating materials including benzocyclobutene (BCB) and an acrylic resin.

Next, a photosensitive layer 138 having a photoresist deposited thereon is formed on the passivation layer 137, and a transmissive part A1 and a blocking part A2 are spaced apart from the photosensitive layer 138. ), And a sixth mask M composed of the first transflective portion A3 and the second transflective portion A4.

In this case, the transmission part A1 is positioned to correspond to the drain electrode 132b of the switching area C, and the first transflective part A3 is disposed on the metal pattern 134 of the storage area ST. The second transflective portion A4 is positioned to correspond to the pixel area P excluding the storage area ST and the switching area C except the drain electrode 132b. The portion A1 is positioned to correspond to a boundary between the driving circuit regions A and B and the neighboring pixel region P, that is, a boundary region between a gate line and a data line (not shown).

In this case, the first semi-transmissive portion (A3) has a greater density of slit (slit) than the second semi-transmissive portion (A4), the intensity of light passing through the first semi-transmissive portion (A3) is the second half. It was made larger than the intensity of light passing through the transmissive portion A4.

The semi-transmissive portion may use a semi-transparent film instead of a slit.

The process of exposing and developing the lower photosensitive layer 138 by irradiating light to the upper portion of the mask (M).

22A and 22B, the photosensitive layer 138 is developed to expose the lower passivation layer 137 corresponding to the drain electrode 132b of the switching region C, and the pixel region P ) To form a stepped photosensitive pattern 140.

In this case, the portion corresponding to the pixel area P is in a state where the portion corresponding to the storage area ST is more removed from the upper part, and the portion corresponding to the pixel area P except for the storage area ST. Is less removed than the storage area.

The portions corresponding to the boundary regions of the driving circuit regions A and B and the neighboring pixel regions P are left at their original heights.

As shown in FIGS. 23A and 23B, the protective layer and the second interlayer insulating layer 137 and 136 exposed between the photosensitive patterns 140 are removed to correspond to the drain electrode 132b of the switching region C, and the drain contact is removed. The hole 142 is formed.

As shown in FIGS. 24A and 24B, the photoresist pattern 140 is first dry-etched to remove all of the lower photoresist patterns corresponding to the storage area ST, thereby removing the lower protective layer 137. ) To proceed with the exposure.

In this case, the dry etching process may be performed to the extent that the photosensitive pattern 140 of the lower portion is removed corresponding to the storage area ST.

25A and 25B, a process of removing the silicon nitride film D2 of the passivation layer 137 and the second interlayer insulating layer 136 exposed corresponding to the pixel region P is performed.

As shown in FIGS. 26A and 26B, a process of secondary dry etching of the photosensitive pattern is performed.

In this case, the photosensitive pattern remaining in the pixel area P except for the storage area ST may be removed to the extent that all of the photosensitive patterns are removed.

Accordingly, the photosensitive pattern 140 remains in correspondence with the boundary between the driving circuit regions A and B and the neighboring pixel region P. FIG.

As shown in FIGS. 27A and 27B, an indium tin oxide (ITO) is formed on the entire surface of the substrate 100 having a photosensitive pattern at the boundary between the driving circuit regions A and B and the adjacent pixel region P. FIG. One selected from the group of transparent conductive metals including and indium zinc oxide (IZO) is deposited to form a transparent metal layer 146.

In this case, the transparent metal layer is in contact with the exposed drain electrode 132b.

As shown in FIGS. 28A and 28B, when the process of removing the photosensitive pattern is performed, the transparent electrode deposited on the photosensitive pattern is also removed, and the switching region C for each pixel region P is removed. The transparent pixel electrode 148 in contact with the drain electrode 132b is formed.

As such, the method of forming the pixel electrode 148 by removing the photosensitive pattern is called a lift-off method.

In this case, the pixel electrode 148 is formed to extend in an upper portion of the gate line and the data line in a planar manner, and this structure has an advantage of further securing an opening area as compared with the related art.

When the above-described process is completed, the pixel electrode 148 formed on the first electrode is made of the metal pattern 134 in contact with the storage wiring 118 as the first electrode in the storage area ST. ) Is used as a second electrode, and a storage capacitor C _ST having an oxide layer D1 positioned between the first and second electrodes as a dielectric is formed.

Through the six mask process described above, an array substrate for a liquid crystal display device with integrated driving circuit according to the present invention can be manufactured.

The manufacturing method of the array substrate for the driving circuit-integrated polycrystal liquid crystal display device according to the present invention can reduce the three mask process as compared with the prior art has the following effects.

First, since the process is reduced, there is an effect that can significantly reduce the probability of failure that can occur during the process.

Second, the process time can be shortened and the process cost can be lowered.

Third, there is an effect of improving the yield by the first and second effects.

Fourth, it is possible to configure the pixel electrode to extend over the gate wiring and the data wiring, thereby ensuring a high opening ratio.

1 is a plan view schematically showing a general liquid crystal panel integrated with a driving circuit unit;

2 is an enlarged plan view showing one single pixel region of an array substrate,

3A and 3B are cross-sectional views of a switching element configured in a pixel region of a conventional array substrate for a liquid crystal display device and a CMOS element configured in a driving circuit region,

4A and 4B are cross-sectional views illustrating a first mask process step of a conventional manufacturing process of an array substrate for a liquid crystal display device;

5A and 5B are cross-sectional views illustrating a second mask process step of a conventional manufacturing process of an array substrate for a liquid crystal display device;

6A and 6B are cross-sectional views illustrating a third mask process step of a conventional manufacturing process of an array substrate for a liquid crystal display device;

7A and 7B are cross-sectional views illustrating a fourth mask process step of a conventional manufacturing process of an array substrate for a liquid crystal display device;

8A and 8B are cross-sectional views illustrating a fifth mask process step of a conventional manufacturing process of an array substrate for a liquid crystal display device;

9A and 9B are cross-sectional views illustrating a sixth mask process step of a conventional manufacturing process of an array substrate for a liquid crystal display device;

10A and 10B are cross-sectional views illustrating a seventh mask process step of a conventional manufacturing process of an array substrate for a liquid crystal display device;

11A and 11B are cross-sectional views illustrating an eighth mask process step of a conventional manufacturing process of an array substrate for a liquid crystal display device;

12A and 12B are cross-sectional views illustrating a ninth mask process step of a manufacturing process of a conventional array substrate for a liquid crystal display device;

13 is an enlarged plan view showing a single pixel of an array substrate for a liquid crystal display device according to the present invention;

14A and 14B are process cross-sectional views showing a first mask process of the present invention;

15 (a, b) to 17 (a, b) are cross-sectional views illustrating a second mask process;

18A and 18B are process cross-sectional views showing a third mask process;

19A and 19B are process sectional views showing a fourth mask process,

20A and 20B are cross-sectional views illustrating a fifth mask process;

21 (a, b) to 28 (a, b) show a sixth mask process

<Description of Symbols for Main Parts of Drawings>

100 substrate 102 buffer layer

108: third active pattern 110: gate insulating film

116: third gate electrode 118: storage wiring

124: first interlayer insulating film 132a, 132b: source electrode and drain electrode

134: metal pattern 136: second interlayer insulating film

137: protective film 138: photosensitive layer

M: Mask

Claims (10)

Defining a substrate as a pixel region including a switching region and a storage region, and a driving region; A first mask process step of forming first and second active patterns in the driving region and a third active pattern in the switching region; First, second and third gate electrodes, respectively, on the upper portion of the first, second and third active patterns, the storage wirings in the storage region, and the first and second gate electrodes on the gate electrodes. A second mask process step of forming a fourth photosensitive pattern on the first, second and third photosensitive patterns and the storage wiring; Dry etching the first, second, and third photosensitive patterns to expose the gate electrodes around the respective photosensitive patterns; Doping n + ions onto surfaces of the first to third photosensitive patterns corresponding to the periphery of the gate electrode; Etching the exposed gate electrode and doping n-ions to the surfaces of the first and third active patterns corresponding to the portions where the gate electrode is etched; A third mask process step of forming a photosensitive pattern covering a region other than the second active pattern of the driving region; Doping p + ions to the surface of the second active pattern corresponding to the periphery of the second gate electrode; Forming a first interlayer insulating film on the entire surface of the first to third gate electrodes and the substrate on which the storage wirings are formed, and patterning the first and third gate electrodes to expose both sides of the first to third active patterns, and to expose the storage wirings. A fourth mask process step; A fifth mask process step of forming first to third source and drain electrodes in contact with both sides of the exposed first to third active patterns, and a metal pattern in contact with the storage wiring; A protective film is stacked and patterned on top of the second interlayer insulating film and the second interlayer insulating film on the entire surface of the substrate on which the first to third source and drain electrodes are formed, to expose the drain electrode of the switching area and to the storage area. Etching a portion of the corresponding passivation layer and the interlayer insulating layer, and then contacting the exposed drain electrode to form a pixel electrode positioned in the pixel region; Array substrate manufacturing method for a liquid crystal display comprising a. The method of claim 1, And the second interlayer insulating film is formed by stacking a silicon oxide film (SiO ₂ film) and a silicon nitride film (SiN _X film). The method of claim 1, And a storage capacitor having the metal pattern as the first electrode, the pixel electrode as the second electrode, and the silicon oxide film positioned between the metal pattern and the pixel electrode as a dielectric. The method of claim 1, And forming a surface of the first to third active patterns by performing a hydrogenation process after forming the second interlayer insulating layer. The method of claim 1, The sixth mask process step Stacking a second interlayer insulating film, an organic film, and a photosensitive layer on an entire surface of the substrate on which the metal patterns contacting the first to third source and drain electrodes and the storage wiring are formed; Placing a mask comprising a transmissive portion, a blocking portion, a first transflective portion, and a second transflective portion spaced apart from the photosensitive layer; Exposing and developing the photosensitive layer to expose a passivation layer corresponding to the drain electrode of the switching region, and a portion corresponding to the storage region is partially removed from a surface and has a height of a, except for the storage region. A portion corresponding to the region is removed from the surface to form a photosensitive pattern having a height of a + b, the photosensitive pattern being left at its original height corresponding to a boundary between the driving circuit region and a neighboring pixel region; Etching the exposed passivation layer and a second interlayer dielectric layer below the semiconductor substrate to expose a portion of the drain electrode; First dry etching (ashing) the photosensitive pattern to expose a lower passivation layer by removing the low height a photosensitive pattern corresponding to the storage area; Removing a portion of the exposed passivation layer and a second interlayer insulating layer below the exposed passivation layer; Exposing the lower passivation layer by second dry etching the photoresist pattern having a height of b left in the pixel area except the storage area; Forming a transparent conductive layer on the front surface of the substrate having the photosensitive pattern left over the boundary of the pixel area and the driving circuit area; Removing the photosensitive pattern to form a pixel electrode in contact with the drain electrode in each of the pixel regions; Array substrate manufacturing method for a liquid crystal display device comprising a. The method of claim 5, The blocking unit is positioned to correspond to a boundary between a driving circuit region and the neighboring pixel region, the first transflective unit is positioned corresponding to the storage region, and the second transflective unit is positioned at a pixel region other than the storage region, And wherein the transmissive portion is positioned at a drain electrode corresponding to the switching region. The method of claim 6, And an intensity of light passing through the first transflective portion is greater than an intensity of light passing through the second transflective portion. The method of claim 1, The passivation layer is formed of one selected from the group of organic insulating materials including benzocyclobutene (BCB) and acrylic resin (resin). The method of claim 1, And a gate wiring in contact with the gate electrode, and further comprising a data wiring in contact with the source electrode. The method of claim 9, And the pixel electrode extends over the gate line and the data line.